The receiver comparator signals of satellite radio navigation systems

 

The invention relates to measuring technique and can be used to determine the relative detuning of the frequency of the reference oscillators and frequency standards and time. The technical task, which is achieved by the proposed device is to improve the accuracy of determination of the relative error of the local frequency of verification or synchronized by signals GPSr generator (reducing its own introduced errors in the measurement of the detuning frequency) that under the same requirements on the accuracy of the comparison frequency of the local oscillator reference signals GPSr can reduce the measurement time and improving the accuracy of formation and synchronization of the local (primary) SEAM to SEAM UTC when receiving signals GPSr. The essence of the technical solutions is that in the receiver comparator signals GPSr containing the receiving device signals GPSr introduced two switches, circuit control the reference frequency driver 1 Hz, the synchronizer, the device control unit and the display LCD. 2 C.p. f-crystals, 3 ill.

The invention relates to measuring technique and can be used to determine the relative detuning frequency driver or external) reference oscillator and the local timeline (CHF) with exemplary signal based on the received signals of satellite navigation systems (SNS) GLONASS/GSP and synchronized with the assigned system time scale.

The invention can be used in Metrology systems for comparison and verification of frequency and time scales of local generators of exemplary signals GPSr, and synchronized by signals GPSr standards of frequency and time.

The known device for receiving and processing signals from satellite navigation systems (SNS) GLONASS/GSP (sensor “NAVIOR-SN-3834 KB “NAVIS” [1], module priamosmaritime clock To 161 rill [2], the microwave receiver of signals of satellite radio navigation systems by RF patent No. 2097919, CL 6 H 04 1/06 [3], the receiver synchronizer according to the testimony of the Russian Federation for useful model No. 18812, CL 7 H 03 D 13/00, H 04 Q 9/04, 2001 [4], which receive signals from SRNS and, in addition to solving the navigation task, demodulator, decode and process the temporal information form from the local oscillator that is synchronized by signals GPSr, the output signal of the reference frequency, determine the relative error of the local frequency generator, form a local SWISS synchronized with SWISS UTC.

As the closest analogue we offer tehomet signals SRNS GLONASS/GSP using a receptor-type SN-3834 or “Palisade”, handles and displays for the visual display of temporal information in the mode “STANDARD” forms from the built-in local synchronized by signals GPSr generator output signal frequency reference mode “CALIBRATOR” defines the relative error of the local frequency internal or external oscillator, using the receiving device generates a local SWISS synchronized with SWISS UTC.

The disadvantages of the above analogs and prototypes should be attributed to their lack of accuracy in the determination of the relative error of the local frequency of a highly stable oscillators (rubidium, cesium, hydrogen frequency standards) and forming with them SEAM, synchronized with the SEAM UTC, causing the need to increase the measurement time.

So, the typical value of the mean square error of formation of the SEAM relative to the SEAM UTC for most modules, the synchronization signals GPSr (including the prototype) is 100 NS, which determines the amount of their own made relative error of measurement of the relative detuning frequency of the local oscillator 110-12for a measurement time of 1 day. Then, as for example, the value of n is 10-12hydrogen frequency standard is (12)10-13or less.

The technical task, which is achieved by the proposed device is to improve the accuracy of determination of the relative error of the local frequency of verification or synchronized by signals GPSr generator (reducing its own introduced errors in the measurement of the detuning frequency) that under the same requirements on the accuracy of the comparison frequency of the local oscillator reference signals GPSr can reduce the measurement time, as well as to improve the accuracy of formation and synchronization of the local (primary) SEAM to SEAM UTC when receiving signals SRNS.

The essence of the technical solutions is that in the receiver comparator signals GPSr containing the receiving device signals GPSr, the entrance of which is the antenna input of the first output of which is connected to the first input of the pair of the receiving device, the output of which is connected to the third input of the synchronizer, the synchronizer, the first output of which is connected to the input of the tuning frequency of the reference oscillator, a second output of which is connected with a control unit, the output koto entered serially connected switch 1, the first input is the input of an external reference signal receiver-comparator, a second input connected to the output of the reference oscillator, and circuit control reference frequency, the output of which is connected with the second clock input, a third output which is the output of the main SEAM of the receiver-comparator; connected in series shaper 1 Hz (DPCD), the first input which is the input of an external investigated sinusoidal signal device, a switch 2, a second input which is the input of an external SEAM device (receiver-comparator signals crns), and key the output of which is connected to the fourth input (reset to “0” pulse counter) synchronizer, the first input connected to the output of the switch 2; a timing diagram FSW, the first input of which is connected with the second output of the synchronizer, the second input of which is connected to the fourth output of the synchronizer, and the output is connected with the second input key; a device for calculating the moving average, the first input (input set the number of averages (N) is connected to the second output of the synchronizer, the second input is connected to the fourth output of the synchronizer, the third entrance gate connected to the output of the switch 2, and the output connection is agenia receiving device and shaper 1 Hz (DPCD) and third inputs of the switch 1 and switch 2, the fourth input connected to a second output of 1 Hz SEAM GPSr receptor signals SRNS.

In Fig.1 shows a structural circuit diagram of the receiver-comparator signals GPSr; Fig.2 is a timing diagram form the receiver signals GPSr pulses of 1 Hz SEAM GPSr and generated by the receiver-comparator pulses main SEAM; Fig.3 - distribution function of the probability densities of the absolute time error pulse shaping SEAM SRNS and the main SEAM receiver-comparator in relation to the ideal of the true position of the pulses SEAM UTC.

The receiver comparator signals GPSr contains the receiving device signals GPSr (1), the input of which is the antenna input of the first output of which is connected to the first input of the pair of the receiving device (3), the output of which is connected to the third clock input (2), clock (2), the first output of which is connected to the input of the tuning frequency of the reference oscillator (4), the second output of which is connected with a control unit (5), the output of which is connected to the LCD display (not shown), a second input connected to the keyboard (not shown), connected in series, the switch 1 (10), the first Wes output of the reference oscillator (4), and the scheme of the HRA reference frequency (11), the output of which is connected with the second input of the synchronizer (2), the third output which is the output of the main SEAM of the receiver-comparator; connected in series shaper 1 Hz (DPCD) (12), a first input which is the input of an external investigated sinusoidal signal device, the switch 2 (13), a second input which is the input of an external SEAM device (receiver-comparator signals crns), and key (14), the output of which is connected to the fourth input (reset to “0” pulse counter (8)) synchronizer (2), the first input connected to the output switch 2 (13); timing diagram FSW (15), the first input of which is connected with the second output of the synchronizer (2), the second input of which is connected to the fourth output of the synchronizer (2), and the output is connected with the second input key (14); the device calculate the moving average (16), the first input (input set the number of averages (N) is connected to the second output of the synchronizer (2), the second input is connected to the fourth output of the synchronizer (2), the third entrance gate connected to the output switch 2 (13), and the output is connected to the fourth clock input (2), the second output of which is connected with the second input device with the OPA 2 (13), the fourth input connected to a second output of 1 Hz SEAM GPSr receptor signals GPSr (1).

The operation of the receiver-comparator signal SNS is the following. The reference frequency signal from an internal or external of the generator through the switch 1 (10), which is controlled by a signal from the second output clock generated in the driver control signals calculations and parameters of the algorithms 71comes on the scheme of the HRA reference frequency (11), which is designed for forming a high reference frequency (100 MHz) to increase the resolution of the measurement of time intervals between pulses of the main SEAM and SEAM GPSr with a receptor signals GPSr, external SEAM or SEAM formed by the imaging unit 1 Hz (DPCD) 12 from the external input sinusoidal signal, which through a switch 2 (13), controlled by signals from the 2nd output of the synchronizer, depending on the selected measurement mode is fed to the input of the census information buffer memory register 9 mainly FSW (digital phase detector) 6. The main FSW 6, comprising a pulse counter with parallel poll 8, at the counting input of which goes to a high reference frequency from the circuit control frequency reference 11, and regier, in addition to the function of forming the main SEAM, the function of measuring time intervals between the pulses of the main SEAM and the pulse time scales at the input of the census information in the memory register 9, as stored in the memory register 9 a number corresponding to the state of the counter 8, multiplied by the period of the high frequency reference with the schema frequency frequency reference 11, will be numerically equal to the time intervalsupplies.between the time of formation of the pulse front master SWISS test.SWcorresponding to the state “0” of the counter 8, and the moment of arrival at the entrance of the census memory register 9 (1st clock input 2) pulse selected by the switch 2 (13) CHFm(Fig.2). Next, the code of the measured time interval tm-test.SWevery second goes to the processing at the transmitter amendments frequency 72in the processor 7, which is part of the synchronizer 2, and the fourth output of the synchronizer 2 is supplied to the second inputs of the synchronization circuitry FSW 15 and the device calculate the moving average of 16, to the first inputs of which are respectively supplied code given interval recorded by scheme code generation interval TC151and the mode of operation for the SRNS signals in the timing diagram FSW 15 are compared by the comparison circuit 152measured |tm-test.SW| with the value of the predetermined interval T3generated by the circuit 151. If the value of |tm-test.SW|TCon first login “reset to 0” of the counter 153modulo q signal is output to reset the counter 153in the original zero state from the comparison circuit 152. If the value of |tm-test.SW|>TCon the second counting input of the counter 153from the comparison circuit 152signal, increasing the numerical value of the state counter 153per unit. If the counter 153has not reached its module account q, whose code is received at the first input of the synchronization circuit of FSW (15) and recorded by scheme code generation q given 154the key 14 is closed by a signal from a casting device 155and synchronization of the pulse counter 8 main FSW 6 pulse SEAM GPSr coming from the output of the receiver signals GPSr through the switch 2 (13) does not occur. If the number of consecutive exceedance values |tm-test.SW| the values of TCreaches the account module q of the counter 153the key 14 is opened RA is Alov GPSr (1) pulse SEAM GPSr will be held on the main FSW and implement it in sync.

In the prototype, each pulse SEAM GPSr with a receptor signals GPSr (1) is fed directly to the input of census information about the state of the pulse counter 8 memory register 9, which means that the processor (7) in the prototype receives numeric data for processing on the temporary differencesupplies.between the implicitly generated internal SEAM and SEAM GPSr. When this SEAM GPSr has a root mean square random deviation (RMS)Ref.=FR.=CPHCfrom the true time tandthe formation of the SEAM UTC equal to the average quadratic deviationxrandom variable x=tm-tandwhere tm- the time of issuance of the next pulse SEAM GPSr with a receptor signals GPSr (1), tand- the corresponding “true” time of issuance of the pulse SEAM UTC (Fig.2).

Under ideal internal synchronized or external researched reference generator prototype made in the measurement of relative frequency offset its own root mean square relative errorfthe FDS.FR./The magnetism.when faturamento Metohija.

For most industrial receivers of signals SRNS, including for the prototype, typicalSRNS=(25100) na, so,

While we believe that the value of x is normally distributed with zero mean.

In the proposed receiver-comparator, it is obvious that the value of y=test.SW-tandwill also be normally distributed, since its value selected from the values of the random variable x (see Fig.2). When this value x is “far” from the center of the distribution, i.e. from zero, leading to the fact that the value of |tm- test.SW|>TCnot selected during synchronization (or are very rarely) with proper choice of q and TCand are replaced by the values of x (closer to the center of the distribution), in which |tm- test.SW|TC.

Thus, the random variable y will have a more “narrow” the probability density function of Wy(see Fig.3), and hence the smaller the standard deviation.

Value (tm-test.SW) can be represented as follows:

.

Variance the difference between a random amount is e q and TC, q should not be too large, since with increasing q increases the transition time - the time at which the counter 153not counted to your module, i.e., increases the proportion of time the transition state in the total observation time, which, in practice, of course. This increases the probability of “error” forming the main SEAM (beyond the time specified TC) when it first happened synchronization counter 8 main FSW pulse SEAM GPSr, which was outside the TC. In addition, TCshould not be too small that the probability of a position pulse SEAM GPSr outside TCwas less than 0.5, otherwise the probability of erroneous synchronization counter 8 will be more likely to “correct” synchronization, i.e., must be q=5-20 and.

Obviously, if the proposed receiver-comparator to use the same faturamento method of measuring the relative frequency offset, which is based on measuring the relative phase shift in the time domain pulse reference SEAM, which in the prototype is used to CHF GPSr, and the proposed receiver-comparator may be used formed its about the CSOs sinusoidal (block 12) or pulse signals, which are passed to the input of the census information memory register 9 switch 2 (13) once per second at the beginning of the measurement time TMEAs.and 1 time per second at the end, we measured the interval will correspond to the shift between the test SEAM and the main SEAM, fluctuations which are already smaller in scale compared to the SWISS SRNS.

Thus, when perfectly accurate external investigated the generator in the proposed receiver-comparator circuit that is synchronized FSW 15 and the key 14 are made in the measurement of the relative detuning of the frequency of the external oscillator own root mean square relative errorfy own. for magnetismwhen the same processing as in the prototype, data discrepancy main SEAM and SEAM GPSr will be determined by the expression:

.

A further increase in accuracy (reducing its own insertion RMS relative deviation of the measured relative frequency offset in the proposed receiver-comparator is achieved through the operation of the device calculate the moving average 16 that every second calculates and outputs, starting with the (N+1)-th second after the start of measurement, for ashodaya (phase shift (in seconds) (tm-test.SW) 1 with her previous N values in accordance with the expression:

where i=N+l, N+2,...

t=1; s=const.

From (3) and (6) it follows that the varianceaveragewill be expressed as follows [5]:

wheret=1 sec.

Provided.

Thus under ideal accurate internal synchronized or external investigated generators, which in the proposed receiver-comparator used to generate the reference frequency, and the measurement algorithm, defined by expression (6), own made root mean square relative errorwill be determined under these conditions, the expression (8), that is,

;t=1;

N is the number of seconds when calculating the moving average.

If the CPU 7 will still determine the relative phase shift of the moving averaget, wheret=l (C) for the measurement time TISMin soo is i=N+1, N+2,...,

then, obviously, your own make the mean square relative error of the proposed receiver-comparatorfPR-ka of ownership. for magnetism.will be determined by the expression:

While we believe that the calculated values ofandare independent.

Thus, from expressions (10) and (1) follows that the proposed receiver-comparator GPSr error will betimes less than in the prototype, but the total measurement time (including time spent on the calculation of the previous value of the moving average values of) increases only for N seconds.

To measure the relative frequency offset generator, the signals which are fed to the inputs of the external SEAM and external investigated sinusoidal signal generated corresponding SEAM. When the division ratio of the former to 1 Hz (DPCD) 12 sets the control signals from the driver control signals calculations and parameters of the algorithms 71in the processor 7 in accordance with a given frequency of the input investigated the ISI information memory register 9 or impulse SEAM GPSr, either impulse SEAM to the study of the external signal (sinusoidal or pulsed depending on operation mode). Every two seconds and calculates a difference value (tm-test.SW) received in the first and second values (tEXT.SW(...)-test.SW) obtained in the second moment,

For this value (tm-tEXT.SWISS(...)) (compare (2)), the CPU 7 and the block 16 conduct operations and calculations, similar transactions and calculations for the value defined by expression (2), only with discrete time in 2 seconds, including operations on expressions (6) and (9). This achieves the same native introduced measurement error, but with increasing time of measurement and treatment 2 times.

The calculated values of the detuning frequency of the internal reference synchronized or external reference of the studied generator, or external signals SEAM or external investigated sine wave multiplied by the CPU 7 in the transmitter amendments frequency 72on the conversion rate of the DAC. The synthesized control signal frequency control unit DAC 73similar to the prototype is given in the reference generator 4.

Praktijkregels or programmatically.

Units 1-9 can be performed similarly to the prototype.

The block 10 may be performed on the electronic relay rack-11, and the outputs a, B are the inputs of the control signal, the inputs 11 and 13 (or 21 and 23) are the inputs of the reference signals, and the output 12 (or 22) is the output signal of the reference frequency (10 MHz).

The unit 11 includes:

GONG high frequency (100 MHz) block 111that can be made under the scheme capacitive treatacne transistor TA, quartz resonator K1-PK-100 MHz RC.382.255 TU, varicap VG and comparator-driver signal AD8561AN;

the frequency divider 10 block 112that can be performed on the chip IE, however the output of 5 - counting input, findings 6 and 12 outputs the divided frequency output 14 (K) on the housing, the output 11- on +5V, pin 8 - case, output 16 -+5 V;

- CFD block 113that can be executed on RS-trigger of the logic elements AND circuits LA, where conclusions 1, 2; 4, 5; 9, 10; 12, 13 are the input signals, and conclusions 3, 6, 8, 11 outputs, pin 7 on the housing, the output 14 to +5 V, and the active filter on the chip UE, where the output 2 via a 3.9 kω is connected to the output of the integrating circuit after the RS-flip-flop of one of the input signals, conclusion 3 - the output of the integrating circuit is, ivod 4 at -15 C.

The block 12 is made on the shaper pulse signal from a sine wave to the comparator-shaper AD8561AN, the output of which is connected to the input DPCD with a division ratio of 1.5 or 10 on the chip CIE (programmable counter input for switching the division ratio), the output 9 - counting input, conclusions 4, 1, 14, 15, 2, 3 - inputs bitwise permissions E0E5 conclusion 13 - R total reset (high level), the output 5 - output of the counter to the counting input of the next decade counter output 16 - power supply +5 V, pin 8 - housing; or DPCD 1, 5 or 10 can be performed by switching on the logical elements And the control signals of the input signal TTL level on one of their inputs chip II-14-th output when connected to 12-m and 1-Ohm findings for dividing by 10, - 1-th output for divide by 5, and bypassing this chip to the counting input of the next decade counter - divider ratio of 1. To DPCD 1, 5, 10 connected connected in series (the output to the input of the next six decade counters IE (output 5 - counting input to increase output 12 output, the output 14 (R) on the housing, the output 16 -+5V, pin 8 - case). The output of the last counter output 1 Hz unit 12.

Block 13 (Switch 2) mo - inputs, output 5 output (the output switch 2), the conclusions 11, 10, 9 is the control input, pin 7 - management of the third condition on the housing, the output 16 - +5 V, pin 8 - case.

Block 14 (Key) can be performed on the logical element AND-NOT circuits LA, conclusions 1, 2 - inputs, output 3 - output, output 14 - +5 V, pin 7 - case.

Blocks 15 and 16 can be performed programmatically micro RC company Ostagon.

The proposed receiver comparator GPSr has a higher precision (smaller average quadratic deviation) of the formation that is synchronized by signals GPSr main SEAM relative to the SEAM UTC due to the operation of the synchronization circuit of FSW 15 and key 14, as the formation of the main SEAM is carried out without large deviations caused by the distortions and errors in the reception of the SRNS signals due to noise on the highway distribution and priemyselna module synchronization due to the fact that the values of X far from the center of the distribution, i.e. from zero, leading to the fact that the value of |tm-test.SW|>TCdo not pass on the synchronization of the main FSW (block 8) and are replaced by the values of X (closer to the center of the distribution), in which |tm-test.SW|Tthe th intimes own you make the mean square relative error of measurement of the relative frequency offset test generators) due to the operation of the device calculate the moving average 16 and circuit control frequency reference 11, which increases the resolution in the measurement.

LITERATURE

1. Brochure-Board navigation sensor “NAVIOR-WITH” KB “NAVIS”, 2001,

2. Navigation-time receiver K-161 satellite systems GLONASS/GPS. Brochure, FSUE RIRV, 2000

3. The microwave receiver of signals of satellite radio navigation systems. RF patent №2097919, CL 6 H 04 1/06.

4. The receiver synchronizer. Evidence of the Russian Federation for useful model No. 18812, CL 7 H 03 In 13/00, H 04 Q 9/04, 2001 (prototype).

5. Handbook of higher mathematics. // Edited by G. Korn and T. Korn.

Claims

1. The receiver comparator signals of satellite navigation systems (SNS), containing the receiving device signals GPSr, the entrance of which is the antenna input of the first output of which is connected to the first input of the pair of the receiving device, the output of which is connected to the third input of the synchronizer, the synchronizer, the first output of which connection, the output of which is connected with the display liquid crystal display (LCD), a second input connected to the keyboard, characterized in that it additionally introduced serially connected switch 1, the first input which is the input of an external reference signal receiver-comparator, a second input connected to the output of the reference oscillator, and the scheme of automatic reference frequency (frequency), the output of which is connected with the second clock input, a third output which is the output of the main timeline (SWISS) receiver-comparator; connected in series shaper 1 Hz, the first input is the input of an external investigated sinusoidal signal device, a switch 2, a second input which is the input of an external SEAM receiver-comparator signals GPSr, and the key, the output of which is connected to the fourth clock input, the first input connected to the output of the switch 2; a timing diagram of the shaper timeline (FSW), the first input of which is connected with the second output of the synchronizer, the second input of which is connected to the fourth output of the synchronizer, and the output is connected with the second input key; a device for calculating the moving average the synchronizer, the third entrance gate connected to the output of the switch 2, and the output is connected to the fourth clock input, the second output of which is connected with the second input device pairing receiving device and shaper 1 Hz and third inputs of the switch 1 and switch 2, a fourth input connected to a second output of 1 Hz SEAM GPSr receptor signals SRNS.

2. The device under item 1, characterized in that the circuit control frequency reference (11) includes connected in series a voltage controlled oscillator (VCO), high frequency (11), the frequency divider to frequency comparison frequency of the phase detector (CPD)1 (112), CFD (113), the control signal output of which is connected to the input of the control signal frequency of the VCO.

3. The device under item 1, characterized in that the timing circuit FSW (15) includes a serially concatenated scheme code generation interval (151and the comparison circuit (152), the second input is a second input of the synchronization circuit of FSW (15); and connected in series circuit code generation qspecified(154), the entrance of which is connected to the input schema code generation interval and is the first in is the first output of the comparison circuit 152and counting a third input connected to the second output of the comparison circuit 152and solver (155), the output of which is output in synchronization schemes FSW (15).

 

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