A method of manufacturing a mos transistor with local areas of the buried insulator

 

Usage: in electronic engineering, in the manufacture of integrated circuits with increased radiation resistance. The technical result of the invention is to simplify the process while improving the reliability of MOS devices. The essence of the invention: method of manufacturing a MOS transistor with local areas of the buried insulator on the surface of a substrate of silicon of the first conductivity type to form an insulating layer around the active areas of the transistor, forming a gate conducting the implantation of ions mainly of oxygen in the substrate before the formation of the depth of the substrate layer with a high concentration of oxygen atoms and silicon dioxide, after ion implantation mainly of oxygen on the side walls of the gate form the parietal region, then in the layer with a high concentration of oxygen atoms and silicon dioxide produce the implantation of ions of the second conductivity type, which use components that are included in which the atoms of matter have higher oxides, forming together with the silica glass, and a thin buried insulator layer, signalground the active area of the drain-source and low-alloy sections, the market softening, but the smaller the glass transition temperature of the resulting glass, and in the interval of time consisting of the time of migration of embedded atoms of the second conductivity type formed in the glass and the time of diffusion of the doping in the active regions of the drain-source, in this case the value of this time interval satisfies the condition of education under parietal regions in the direction of the shutter intermediate sections with all lesser degree of alloying. 4 Il.

The invention relates to electronic devices and can be used in the manufacture of integrated circuits with increased radiation resistance.

Modern design and technological requirements for the base of the high-speed integrated circuits based on MOS (metal-insulator-semiconductor) transistor structures involve the formation of small high-alloyed regions of the drain-source, minimizing the length of the channel and spuriouscapacitances of p-n junctions with a maximum attenuation of unwanted effects such as puncture channel. A key approach that resolves some of the problems is the use of substrates of type SOI (silicon-on-isoneway substrate by a continuous layer of ion-synthesized buried insulator, eliminating parasitic capacitive effects and leakage currents in the substrate. It is also known that the buried insulator layer prevents the transition to the diffusion of dopant on the tail sections of the concentration profile, which is the main cause of "blur" small alloyed regions of the drain-source (shallow junction) [2].

However, the SOI substrate manufactured by the SIMOX method, at relatively high cost have all the same high level of defects, and reliable operation of MOS devices on the substrates is prevented by the presence of floating charge potential at the top of the instrument silicon layer and the instability of the threshold voltage. To minimize the effect of the floating potential in the manufacture of MOS devices are sometimes used as a source of conventional silicon substrate (without SOI structures), and the buried insulator layer according to the method of SIMOX is formed through the mask locally, for example, only the active regions of the drain and source [3-7]. In this case, the shutter with vertical walls and a protective mask (from the effects of implanted ions) samozavest with the doped regions of the drain-source and positioned below the local layers of the buried insulator. Primasol the impurity diffusion area drain and the source, the reduction of the containers relative to the substrate due to the series capacitance of the insulator, and the flow of charge in a channel region of a transistor is directly in the substrate.

Closest to the claimed combination of features (prototype) is a method of manufacturing a MOS transistor with local areas of the buried insulator [8], including the formation on the surface of the substrate based on silicon of the first conductivity type isolation layer around the active areas of the transistor, forming a shutter with vertical side walls and a protective layer mask on the top, preventing the introduction of the ions in the conductive layer of the gate during subsequent implantation, subsequent implantation of ions mainly of oxygen in the substrate on both sides of the shutter with the dose and energy to education in the depth of the substrate layer with a sufficiently high concentration of oxygen atoms and silicon dioxide, bounding from below the active area of the drain-source, the formation of a thin buried insulator layer by stimulating the interaction of implanted atoms with the substrate by annealing, the formation adjacent on both sides to the gate of the active regions of the drain-source subactions areas preventing the introduction of ions into the substrate during subsequent implantation, subsequent implantation of ions of the second conductivity type in the substrate on both sides of the parietal regions, forming signalisierung active regions of the drain-source by annealing.

However, in the manner specified in the prototype, has its disadvantages:

- it is known that for the formation of the buried insulator layer on the basis of silicon dioxide require long-term high-temperature anneals, little compatible with the standard process of manufacturing devices on the basis of MOS transistor structures;

- as a buried layer of pure silicon dioxide leaves much to be desired (charge instability [9] or the mismatch of the physical parameters with the substrate);

the process of manufacturing a MOS transistor with samozavestna shutter according to the prototype involves two of postimplantation annealing (when forming the layer of the buried insulator and the doping regions of the drain-source).

The aim of the present invention is to simplify the process while improving the reliability of MOS devices.

This goal is achieved by the fact that m formation on the surface of the substrate based on silicon of the first conductivity type isolation layer around the active areas of the transistor, the formation of the gate with vertical side walls and a protective layer mask on the top, preventing the introduction of the ions in the conductive layer of the gate during subsequent implantation, subsequent implantation of ions mainly of oxygen in the substrate on both sides of the shutter with the dose and energy to education in the depth of the substrate layer with a sufficiently high concentration of oxygen atoms and silicon dioxide, bounding from below the active area of the drain-source, the formation of a thin buried insulator layer by stimulating the interaction of implanted atoms with the substrate by annealing, the formation adjacent on both sides to the gate of the active regions of the drain-source low-alloy sections of the second conductivity type, forming on the sidewalls of the gate dielectric wall areas, preventing the introduction of ions into the substrate during subsequent implantation, subsequent implantation of ions of the second conductivity type in the substrate on both sides of the parietal regions, forming signalisierung active regions of the drain-source by annealing after ion implantation mainly of oxygen on the side walls of the gate form the parietal region, then in kofodimos, where to use the components in which the atoms of matter have higher oxides, forming together with the silica glass, and a thin buried insulator layer, signalground the active area of the drain-source and low-alloy sections, adjacent on both sides of the shutter is formed simultaneously by annealing at a temperature higher than the softening temperature but lower the glass transition temperature of the resulting glass, and in the interval of time consisting of the time of migration of embedded atoms of the second conductivity type formed in the glass and the time of diffusion of the doping in the active regions of the drain-source, thus the value of this time interval satisfies the condition of education under parietal regions in the direction of the shutter intermediate sections with all lesser degree of alloying.

New in the invention is that after the ion implantation mainly of oxygen on the side walls of the gate form the parietal region, then in the layer with a high concentration of oxygen atoms and silicon dioxide produce the implantation of ions of the second conductivity type, which use components that are included in which the atoms of matter have higher oxide is the active area of the drain-source and low-alloy sections, adjacent on both sides of the shutter is formed simultaneously by annealing at a temperature higher than the softening temperature but lower the glass transition temperature of the resulting glass, and in the interval of time consisting of the time of migration of embedded atoms of the second conductivity type formed in the glass and the time of diffusion of the doping in the active regions of the drain-source, in this case the value of this time interval satisfies the condition of education under parietal regions in the direction of the shutter intermediate sections with all lesser degree of alloying.

The invention consists in the fact that although the method of ion-beam synthesis of glass as a buried insulator layer in the silicon substrate previously known [11], however, the method of manufacturing a MOS transistor with local areas of the buried insulator, which includes glass - source dopant for the active regions of the drain-source in the annealing process, is proposed for the first time. This allows us to conclude that the claimed method meets the criterion of "inventive step".

The drawings show a sequence of manufacturing a MOS transistor with local areas of the buried insulator according to C what you're after operations:

- formation on the surface of the layer of insulating dielectric around the active areas of the transistor 2 and the shutter with vertical side walls of the layer of gate dielectric 3, the conducting layer 4, protective layer mask on the top 5;

- ion implantation mainly of oxygen on both sides of the gate in the substrate before formation of a deep layer with a high concentration of oxygen atoms and silicon dioxide 6.

With different ways of creating an insulating layer 2 on the depth of its position relative to the surface of the substrate 1 should provide the closure with a layer of the buried insulator 10 (Fig.3) for the continuous isolation of the active regions of the transistor. As the material for the dielectric 2 and the gate dielectric layers 3 are commonly used silicon dioxide, the latter is preferable for nitridization in the process of its creation. For the material of the conductive layer of the gate electrode 4 using doped polysilicon or police (polysilicon formed with the top layer of the silicide of the metal). As a protective layer masks 5 using the photoresist layer or the combination with other layers of more radiation resistant organic or inorganic materials (such as films ri their formation. Implantation of ions predominantly oxygen does not exclude prior, subsequent or joint with the oxygen ions implanted small doses isovalent ions (germanium, silicon, carbon) or ions of inert gas, for example argon. The formation of a layer with a sufficiently high concentration of oxygen atoms and silicon dioxide in the range selected energies occurs when implantation of oxygen with doses more Q some Qmin. In this case thermodynamic stability of the buried layer of silicon dioxide during subsequent annealing and the formation of a continuous homogeneous layer with inclusions of amorphous precipitates.

In Fig.2 shows the same substrate 1 in a subsequent step, after forming the side walls of the gate parietal regions 7 and the ion implantation of the second conductivity type 8 directly in the layer with a high concentration of oxygen and silicon dioxide. As a result, the layer 6 in Fig.1 is transformed into a 9 in Fig.2. The near wall region is formed in two stages: the first is applied to the surface with a stepped relief in the form of side walls of the gate dielectric layer, the second conducting anisotropic plasma etching of this layer. In csega delete data areas after implantation more comfortable silicon nitride. As ions 8 use components that are included in which the atoms of matter have higher oxides capable together with the silica to form glass (boron, boron fluoride, phosphorus and so on)

In Fig.3 shows the same substrate 1 after the final stage of the simultaneous formation of a thin buried insulator layer 10 containing glass, doping of the glass hotspot runoff 11, a source 12 and the intermediate sections 13, for which the degree of alloying under parietal regions decreases with distance. The formation occurs as a result of annealing at a temperature higher than the softening temperature but lower the glass transition temperature of the resulting glass. The annealing occurs in the time interval resulting from the time migration of embedded atoms of the second conductivity type formed in the glass and time of diffusion alloying of their active areas of the drain-source 11, 12 and the intermediate sections 13 due to the lateral diffusion of impurities under parietal regions at a distance < t. Otherwise, when the output of the leading edge diffusion at the edge of the underlying layer of the buried insulator dramatically increase the capacity of the drain-substrate and source-substrate and snireangego invention.

Example. On the surface of the silicon substrate EFC-4,5 with orientation (100) of the first conduction type (n) by thermal oxidation with a mask of silicon nitride formed a local area of silicon dioxide with a thickness of 0.6 µm, isolating an active region formed of the transistor. Then put a gate silicon dioxide of a thickness oflayer doped with boron polysilicon with a thickness of 0.3 μm and a layer of low temperature silicon dioxide with a thickness of 0.3 μm, which is part of the protective layer of the mask during the subsequent implantation of oxygen. Then after forming the layer photomasks of the photoresist AZ5418 thickness of 1.5 μm, a projection photolithography on the installation EM-A on deposited layers form the area of the shutter with vertical walls and a channel length of 1.5 μm. Next, the substrate with undeleted by photomasks (5 in Fig.1) at an angle of 7implanted oxygen ions with an energy of 100 Kev and a dose of 11018About+/cm2. The energy and dose of oxygen is chosen in accordance with the curve shown in Fig.4, which was obtained based on the calculation of thermodynamic potentials of the system silicon - implanted oxygen [12]. After implantation photo is sure-Chemical-Vapour-Deposition) put a layer of silicon dioxide with a thickness of 0.65 μm and anisotropic plasma etching of the deposited layer on the installation 08-PHO-100T-004 created a wall surface of the dielectric region of thickness t=0.5 µm. Then in the same substrate implanted boron ions with an energy of 65 Kev and a dose of 1.651017In+/cm2(Fig.2). The control structures after implantation then examined by means of secondary ion mass spectrometry (Sims) using methods previously applied in [13]. Analysis of the distributions of boron and oxygen showed that the maximum concentrations of both elements are located at a depth of about 0.25 μm, which is quite satisfactory match with the simulation results of the implantation process by using the TRIM program (according to her the maxima of the distributions should be at a depth of 0.22 μm). After that, the substrate in the furnaces of the type SODOM-3 are annealed in an inert atmosphere with oxygen content less than 0.5% at a temperature of 1100C for 4 minutes, and the resulting structure is again examined by the method of VIMS. The results of the analysis showed that the annealing process has formed a buried layer of borosilicate glass containing 18% of In2About3thickness of ~ 140 nm, while in the areas of the drain and source doping level of boron was 11020cm-3.

Thus, the inventive method allows to significantly simplify technology thermal budget of thermal treatment.

The inventive method compared with the prototype has the following advantages:

- you can achieve better stability of MOS transistor when it reaches the minimum level of dangling bonds in the structure of the buried insulator layer of glass compared to silicon dioxide;

- reduced thermal budget postimplantation thermal treatments, since the softening temperature of the glass in a wide range of compositions, as a rule, do not exceed 1050S, i.e. the possibility of using the standard rapid annealing;

in the proposed method of manufacturing a MOS transistor, the number of annealing is reduced to one, since the formation of the buried insulator layer and the active regions of the drain-source occur simultaneously;

- the lateral diffusion of impurities in the annealing process leads to a smooth distribution, which reduces the likelihood of breakdown, the generation of hot electrons, their injection into the gate dielectric;

glass is a good generating centers uncontrolled and harmful impurities (iron, copper, gold) at temperatures of heat treatments ~ 1050With neutralized, forming a layer of glass persistent chemical ial. // MRS Bulletin. 1998, vol.23, No. 12, pp.25-29.

2. P. M. Rousseau, S. W. Crowder, P. B. Griffin, J. D. Plummer. Arsenic deactivation enhanced diffusion and the reverse short-channel effect. // IEEE Electron Device Letters, 1997, vol.18, No. 2, pp.42-44.

3. U.S. patent No. 5795800, H 01 L 021/00 (NCI 438/149), publ. 18.08.1998.

4. U.S. patent No. 4700454, H 01 L 21/265 (NCI 438/407), publ. 20.10.1987.

5. U.S. patent No. 6069054, H 01 L 21/76 (NCI 438/407), publ. 30.05.2000.

6. U.S. patent No. 5674760, H 01 L 21/336 (NCI 438/297), publ. 07.10.1997.

7. U.S. patent No. 6100148, H 01 L 21/336 (NCI 438/305), publ. 08.08.2000.

8. U.S. patent No. 5712173, H 01 L 21/84 (NCI 438/297), publ. 27.01.1998.

9. Devine R. A. V., et al. Oxygen gettering and oxide degradation during annealing of Si/SiO2/Si structures // J. Appl. Phys. 1995, vol.77, No. 1, pp.175-186.

10. A. I. Kurnosov, V. C. Yudin. Technology and equipment for production of semiconductor devices. Leningrad: Sudostroenie, 1971, S. 121.

11. RF application No. 2001100775/28, 09.01.2001, H 01 L 21/76. The decision to grant a patent dated 16.05.2001.

12. Krivelevich, S. A., Ciruli A. A. calculation of the free energy function and the modeling of evolution of the system silicon - implanted oxygen. Abstracts of the conference on crystal growth, films and defect structure of Silicon-2002", July 9-12, Novosibirsk, 2002

13. Krivelevich, S. A. and other Formation of SiO2-layer in silicon, implantirovannomu oxygen // high-purity substances. 1993, No. 6, S. 133-136.

Claims

The way izgatavot substrate based on silicon of the first conductivity type isolation layer around the active areas of the transistor, the formation of the gate with vertical side walls and a protective layer mask on the top, preventing the introduction of oxygen ions in the conductive layer of the gate during subsequent implantation, the implantation of ions mainly of oxygen in the substrate on both sides of the shutter with the dose and energy to education in the depth of the substrate layer with a sufficiently high concentration of oxygen atoms and silicon dioxide, bounding from below the active area of the drain-source, the formation of a thin buried insulator layer by stimulating the interaction of implanted atoms with the substrate by annealing, the formation adjacent on both sides to the gate of the active regions of the drain-source low-alloy sections of the second conductivity type, forming on the sidewalls of the gate dielectric wall areas, preventing the introduction of ions into the substrate during subsequent implantation, the implantation of ions of the second conductivity type in the substrate on both sides of the parietal regions, forming signalisierung active regions of the drain-source by annealing, characterized in that after the ion implantation mainly of oxygen on the side walls of the gate form the parietal region, the IPA conductivity, where to use the components in which the atoms of matter have higher oxides, forming together with the silica glass, and a thin buried insulator layer, signalground the active area of the drain-source and low-alloy sections, adjacent on both sides of the shutter is formed simultaneously by annealing at a temperature higher than the softening temperature but lower the glass transition temperature of the resulting glass and in the time interval resulting from the time migration of embedded atoms of the second conductivity type formed in the glass and the time of diffusion of the doping in the active regions of the drain-source, thus the value of this time interval satisfies the condition of education under parietal regions in the direction of the shutter intermediate sections with all lesser degree of alloying.

 

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