Integrated driver

 

The invention relates to a pulse technique for forming control pulses on the diode load. The technical result is to increase performance while reducing power consumption and symmetry of the weekend free. Integral driver includes first and second transistors (T) (1) and (2) n-p-n type, emitter T (1) is connected with the first power rail (GSR) (7), and the collector connected to the emitter and base T (2) respectively through first and second diodes (3) and (4) in the direct inclusion of the manifold T (2) is connected with noise reduction (8), its emitter is connected to the output bus, and the base through the first toksabay element (TE) (6) connected with noise reduction (8). Entered the third and fourth T (9) and (10) n-p-n type and the second TE (11) base T (9) is connected to the input bus, the emitter connected to the base of the T (1), and the collector is connected to the base T (10) and through the second TE (11) is connected to the WOOFER (8), the emitter T (10) is connected to the base of the T (2) and the collector - current (8). While the first and second TE (6) and (11) is made of a T p-n-p type. 1 Il.

The invention relates to a pulse technique and can be used to generate control pulses on the diode load.

Known integral driver on the same type of transistors containing Patrascu this device does not provide the necessary amplitude and symmetry of output pulses relative to the power bus due to the high residual stresses in the composite transistor of the upper arm push-pull output stage, and also has increased power loss in the dynamic mode due to leakage currents through.

Closest to the invention to the technical essence is integral shaper, containing the first and second transistors are n-p-n type, the emitter of the first transistor is connected to the first power bus, and a collector connected to the emitter and base of the second transistor, respectively, through first and second diodes in the forward inclusion, the collector of the second transistor is connected to the second power bus, its emitter is connected to the output bus, and the base through the first toksabay element connected to the second power bus [2].

However, the known shaper is characterized by high power consumption and low performance due to the limited gain of the output transistors.

The aim of the invention is to increase performance while reducing power consumption and ensuring the symmetry of the output pulses.

This objective is achieved in that in the known integral shaper, containing the first and second transistors are n-p-n type, the emitter of the first transistor is connected to the first power bus, and a collector connected to the emitter and base of the second transistor of Kootenay power, its emitter is connected to the output bus, and the base through the first toksabay element connected to the second power bus, entered the third and fourth transistors are n-p-n type and the second toksabay element, the base of the third transistor is connected to the input bus, the emitter connected to the base of the first transistor, and the collector is connected to the base of the fourth transistor and through the second toksabay element connected to the second power bus, the emitter of the fourth transistor is connected to the base of the second transistor, and the collector with the second power bus (while the first and second tokisada elements performed on the transistors p-n-p type).

The drawing shows a circuit diagram of the proposed integrated driver.

Integral driver includes first and second transistors 1 and 2 n-p-n type, the first and second diodes 3 and 4, output bus 5, the first toksabay element 6, the first bus 7 power, a second bus-8 power supply, the third and fourth transistors 9 and 10 n-p-n type, the second toksabay element 11 and the input bus 12.

Integral driver works as follows. If the input bus 12 high-level signal, the first and third transistors 1 and 9 are open and dense. The load current flows Chatenay through the second diode 4 and through the first transistor 1. It is easy to see that the second and fourth transistors 2 and 10 are closed, because of the offset on them emitter junctions approximately zero, i.e., below the threshold of their release. The voltage level on the output bus 5 is determined by the voltage on the first bus 7 power minus the saturation voltage of the collector-emitter of the first transistor 1 and the voltage on pramosone the first diode 3.

The locking signal on the input bus 12 integral driver leads to locking of the first and third transistors 1 and 9. The currents from the first and second tokisada items 6 and 11 begin to increase the potentials at the bases of the second and fourth transistors 2, 10, and the rate of change of the potential is determined by the amperage dakotadashako element and the equivalent capacitance of the corresponding node in relation to the power bus. The second transistor 2 is output, designed for relatively large operating current, so it is obvious that equivalent capacity, refer to the base of the second transistor 2 is significantly greater than the capacity provided to the base of the fourth transistor 10, is designed for relatively low operating current. Consequently, the fourth and second transistors 10 and 2 at the stage of formation of the positive differential voltage is antistorm in the prototype) can improve performance for a given power level. At the final stage of the formation of the output voltage of the high level of the fourth transistor 10 is locked, and the load current is determined by a single output transistor, the second transistor 2. The steady-state value of the high voltage level on an output bus 5 is determined by the voltage on the second bus 8 power minus the voltage drop on the ground tacosode element 6 (in this example implementation, this voltage collector-emitter saturation of the p-n-p transistor) and pramosone emitter transition of the second transistor 2, there is provided the symmetry of the output signals relative to the voltage on the power bus.

When applying to the input bus 12 driver enabling signal potential on the base of the fourth transistor 10 decreases faster than the potential on the base of the second transistor 2 (through the appropriate choice of the modal currents in the driver). In the fourth transistor 10 at a stage of forming a negative differential voltage on the output bus 5 is in the cutoff mode. The second transistor 2 is turned off, because it works at zero bias emitter junction. Thus, the through current in the push-pull output stage form is useful through current) and minimum power consumption.

The novelty of the invention lies in the fact that in the integral shaper introduced additional elements capable of forming a positive differential voltage in two stages: 1) accelerated growth due to the cascade connection of the second and fourth transistors, and 2) an additional increase of the output voltage after turning off the fourth transistor of the second transistor and the first takasedani element. Through appropriate linkages, as well as by performing tokisada elements in the p-n-p transistors in the proposed driver improved performance, comparable with the scheme on a composite transistors excluded through current and provides a high degree of symmetry of output pulses.

The technical result of the invention is realized only when the total use of its distinguishing features.

The obviousness of the invention can be illustrated by the fact that, for example, the implementation of the first and second transistors in the prototype in the form of a composite transistors though and can improve performance, but reduces the amplitude of the output pulses due to a larger (compared to the single transistor) oszustwa technical solution (prototype), in which the phasing of the shoulders push-pull output stage has already been secured, an additional cascade in the form of gazorazdelitel. This in conjunction with the execution tokisada elements in the p-n-p transistors and helped to solve the problem, namely, to improve performance at a given power consumption, eliminate through current, to provide a high degree of symmetry of output pulses and the maximum utilization voltage power sources.

Sources of information

1. Analog and digital integrated circuits. C. C. Jakubowski, N. A. Barkanov, B. P. Kudryashov and others /edited by S. C. Jakubowski. - M.: Owls. radio, 1979, S. 59, Fig. 3.8.

2. Greben A. B. Design of analog integrated circuits. TRANS. from English. - M.: Energy, 1976, S. 131, Fig. 6-7, b.

Claims

Integral driver containing the first and second transistors are n-p-n type, the emitter of the first transistor is connected to the first power bus, and a collector connected to the emitter and base of the second transistor, respectively, through first and second diodes in the forward inclusion, the collector of the second transistor is connected with the second power bus, its emitter is connected to the output bus, and the base through the first tokisada is n type and the second toksabay element, the base of the third transistor is connected to the input bus, the emitter connected to the base of the first transistor, and the collector is connected to the base of the fourth transistor and through the second toksabay element connected to the second power bus, the emitter of the fourth transistor is connected to the base of the second transistor, and the collector - with the second power bus, the first and second tokisada elements performed on the transistors p-n-p type.

 

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1 dwg

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1 dwg

FIELD: physics.

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