The pulse generator

 

The invention relates to a pulse technique and can be used in devices of computer engineering and control systems. The technical result is to increase the reliability of operation. The device has an RS-trigger element ILI, item 2I-NO, two inverter, four resistors, two capacitors. 1 Il.

The invention relates to a pulse technique and can be used in computer equipment and control systems.

Known pulse generator (see and.with. The USSR №482878 from 24.04.72, MKI N 03 To 5/01, N 03 To 3/26, “Multivibrator” authors B. A. Krylov and B. C. Mjateznikov, publ. 30.08.75, bull. No. 34), containing two triggers, two capacitor and two diodes. The first and second outputs of the first flip-flop connected respectively with the first and second inputs of the second trigger. The first output of the second trigger is connected to the cathode of the first diode, the anode of which is connected to a second input of the first flip-flop and the first output of the second capacitor, the second terminal of which is connected to a common bus. The second output of the second trigger is connected to the cathode of the second diode, the anode of which is connected to the first input of the first flip-flop and the first output of the first capacitor, the second is ment because of the possibility of “freezing” of the circuit when power is applied.

Closest to the claimed invention, the essential features is the pulse generator (see and.with. The USSR №1019592 from 06.01.82, MKI N 03 To 3/281, “Multivibrator” author B. N. Belousova, publ. 23.05.83, bull. No. 19), containing RS-trigger capacitor connected between the trigger inputs, the first and second diodes, the anodes of which are connected respectively with S - and R-inputs of the flip-flop, and a logical inverter. The cathode of the first diode is connected to the inverse output of the flip-flop.

The input of logic inverter connected to invert the trigger output, and the output to the cathode of the second diode.

The disadvantage of the pulse generator is the low reliability due to a sharp increase in the repetition rate of output pulses at failure (breakage) of the capacitor.

The problem solved by the invention is the creation of a pulse generator with high reliability.

The technical result consists in increasing the reliability of operation is achieved in that in the pulse generator containing RS-flop inverted output of which is connected to the input of the inverter, and a capacitor entered the second capacitor element 2, element ILI, the second inverter and four resistor, is connected with the first pins of the first and second resistors, the second terminal of the first resistor is connected with the first inputs of the element 2 and element ILI-NO, the second terminal of the second resistor is connected directly to the output of the first inverter and through the third resistor to the second output of the second capacitor and the first output of the fourth resistor, the second terminal of which is connected to the second inputs of the element ELI and element 2I, the output of which through a second inverter connected to the R input of the RS-flip-flop S-input of which is connected with the output element ILI.

This set of features allows to increase the reliability of operation of the pulse generator due to the fact that the failure (breakage) of one of the capacitors repetition rate of output pulses is determined by another capacitor.

The drawing shows a schematic diagram of the pulse generator.

The pulse generator contains the RS-trigger 1, the first 2 and second 3 inverters, item 2I-4, item ILI-5, the first 6 and second 7 capacitors, the first 8, second 9, the third 10 and fourth resistors 11. Inverted output of the RS flip-flop 1 is connected to the input of the inverter 2 and the first terminals of the capacitors 6 and 7. The second lead of the capacitor 8 is connected with the first terminals of the resistors 8 and 9. The second terminal of the resistor 8 is connected with the first whre 2 and through a resistor 10 to the second output capacitor 7 and the first output resistor 11, the second output of which is connected to the second inputs of the element ILI-5 and item 2 IS NOT 4, the output of which through the inverter 3 is connected to the R input of RS flip-flop 1, S-input connected to the output element ILI-5.

The pulse generator operates as follows.

After applying power, RS-flip-flop 1 is set in one of the stable positions. Consider the case when the inverted output of the RS flip-flop 1 is set to the logical level "1". At the output of the inverter 2 is set to logic level "0". Since the capacitors 6 and 7 at the initial moment is discharged, the input elements 2I-4 and ILI-5 through resistors 8 and 11 receives a logic level "1". The outputs of the elements 2I-4 and ILI-5 level is set to a logical "0", and the R and S inputs of the RS-flip-flop 1 levels logic "1" and logical "0", confirming the initial state of the RS-flip-flop 1. The capacitor 6 starts to charge through the chain of "inverted output of the RS flip-flop 1, resistor 9, the inverter output is 2". Simultaneously, the capacitor 7 starts to charge through the chain of "inverted output RS-Triger 1, resistor 10, the inverter output is 2". As the charge of the capacitors 6 and 7, the voltage at the inputs of the elements 2I-4 and ILI-5 begins to decrease. Due aidenteitei speed. For definiteness, let us assume that the constant of the charge circuit of the capacitor 6 is less than the constant of the charge circuit of the capacitor 7. Therefore, the voltage at the first input element 2I-4 and ILI-5 will reach the switching threshold earlier than the second input. At this moment the output of the element 2I-4 will be a logic level "1", and the output element ILI-5 will remain a logic level "0" when both inputs of the RS-flip-flop 1 will be a logic zero and the trigger will be in the mode information storage. When the voltage on the second input elements 2I-4 and ILI-5 level switching threshold at the output of the latter will be a logic level "1", which, acting on the S-input of the RS flip-flop 1, install it in one state. On the inverted output of the RS flip-flop 1 will receive a logic level "0" and starts charging the capacitors 6 and 7. As in the initial moment of time at both entrances of the elements 2I-4 and ILI-5 will be a logic level "0", and the R and S inputs of the RS-flip-flop 1 will have to do the logical levels "0" and logical "1", then the status of the RS-flip-flop 1 will not change. As overcharging of the capacitor 6 and 7 the voltage at the inputs of the elements 2I-4 and 2H switch, however, this will not lead to the overturning RS-Triger 1, since its inputs are logic "0". When the voltage on the second input elements 2I-4 and ILI-5 will reach the switching threshold, the output element 2I-4 will be a logic level "0", and the R input of the RS-trigger 1 level logic "1". RS-trigger 1 will be set to the state corresponding to the logical level "1" at its inverted output. The process of generating output pulses is repeated.

In case of failure (breakage) of one of the capacitors increase the frequency of generation of output pulses will not occur because of the job description it is seen that the switching frequency of the RS-flip-flop 1 is determined by the capacitor with the highest capacity.

Made the layout generator. Tests confirmed the operability of the claimed device and its practical value.

Claims

The pulse generator containing RS-flop inverted output of which is connected to the input of the inverter, and a capacitor, characterized in that the input of the second capacitor element 2, element ILI, the second inverter and four resistor, and the inverted output of the RS flip-flop connected to the first terminals of the capacitors, a resistor connected with the first inputs of the element 2 and element ILI, the second terminal of the second resistor is connected directly to the output of the first inverter and through the third resistor to the second output of the second capacitor and the first output of the fourth resistor, the second terminal of which is connected to the second inputs of the element ELI and element 2I, the output of which through a second inverter connected to the R input of the RS-flip-flop S-input of which is connected with the output element ILI.

 

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FIELD: measurement technology; pulse stream generators.

SUBSTANCE: proposed Poisson pulse stream generator has k + 1 memory devices, comparison unit, k digital-to-analog converters, control circuit, register, counter, selector, k bell-shaped pulse generators, adder, voltage-to-current converter, and clock generator.

EFFECT: enlarged generation range of pulses adequate to ionization chamber signals.

1 cl, 2 dwg

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