Device for synchronization cycles

 

The invention relates to telecommunication and can be used in the receiving device sync cycles of transmission of discrete messages. The technical result is to increase the noise immunity and performance of the device for synchronization cycles. The device includes a detector clock element of the ban, the first element And the adder, the unit shift registers, the driver of such pulses, the element OR the cycle counter, the counter distorted signals, the block select more undistorted singlesymbol, the block selection threshold, the block selection coefficient accounts, the counter out of synchronism, as well as a crucial node containing the first block of comparison, a memory unit, a subtraction unit, a second unit of comparison, the count comparison, the second element And. the Technical result is achieved by adapting the Recognizer clock and counter out of synchronism to the change in the probability of erroneous reception of the synchronization signal. 6 Il.

The invention relates to telecommunication and can be used in the receiving device sync cycles of transmission of discrete messages.

A device d is e device Recognizer clock, the adder, the unit shift registers, a crucial node, and the output of the detector clock connected to the first input of the adder, the output of which is connected to the signal input of the shift registers, the main output of which is connected to the second input of the adder. In addition, in the known device, the main output of the unit shift registers is connected with the signal input of the decision making node. This adder is made in the form of n-bit reversible counter which performs a counting function response of the detector clock on each of the pulse positions of cycles of the observation interval, and n shift registers of unit shift registers perform the saving of the results account for the duration of the cycle. In clock intervals defined by clock pulses from a clock pulse is cheating values of bits of the n-bit counter in the first cell of the corresponding shift registers and write to the same counter values of the last cells of the shift registers. If the heartbeat interval is the response of the detector clock, the n-bit counter is added to the unit, and thus the value of the binary number corresponding to the number off the and the detector, the number written in parallel binary code into an n-bit counter with the last cell of register is decreased by one. After a cycle in cells of registers in a parallel binary code are recorded the results of the response of the detector for all N pulse positions. Based on the analysis of these results, a crucial node determines the position number, which corresponds to the largest binary number of responses of the detector clock, and thus decides the position of synchronism. The output of the decision making node is an output device. A disadvantage of the known device is the low immunity, defined high probability of false positives (false detection of synchronism) with distortion of the clock noise. When the distortion of at least one sync pulse at the output of the Recognizer clock, there is no response. The value of the binary number corresponding to the number of responses accumulated previously in the position loop is decreased by one, i.e., there is loss of the accumulated synchroinformation. At other positions of the cycle may be the accumulation response of the detector clock on false singlegroup that uvelichivaetsya synchro-characters dramatically increases the probability of detection by the detector of false singlegroup (see Koltunov M. N., Konovalov, C., leaf monkeys H. I. Synchronization cycles in digital communication systems. - M.: Communication, 1980. - S. 134), which also increases the probability of false detection of synchronism.

A device for the synchronization cycle.with. The USSR № 1085006 class H 04 L 7/08, publ. 07.04.84, bull. No. 13, containing, as the proposed device, the detector clock, the shift register, the first and second And gate, and the driver of such pulses, a clock input which is combined with a clock input of the shift register and a clock input of the detector clock and is clocked by the input device and the information input device connected to the signal input of the Recognizer clock, the output of which is connected to the second input of the first element And to the first input of which is connected to the output of the shaper cyclic pulses, which are output devices, and to the reset input of the shaper cyclic pulses connected to the output of the second element I. in Addition, the known device comprises an element OR the third element And the decoder specified state, a trigger and an additional shift register. Thus the output of the detector clock also combined with the first input member OR the output of which with the NTA And, the output of which is connected with the second input of the OR element and the second input of the third element And is connected to the trigger output. In addition, the output of the shaper cyclic pulses also jointly connected to the clock input of the shift register and the second input of the trigger, and the output of the first element And is connected to the signal input of the shift register, the outputs of which are connected to the second group of inputs of the second element And. an Additional output of the shift register is connected to the input of the decoder of the set state, the output of which is jointly connected to the first input of the trigger and the first input of the second element I. However, a disadvantage of the known device is the low immunity caused by the fixed factor accumulation drive on exit from the state of synchronism (a fixed number of additional outputs of the shift register), when low probability of erroneous reception of the synchronization signal leads to an increase in recovery time cycle of synchronism when the true failure, but with a high probability of erroneous reception of the synchronization signal increases the probability of false detection of synchronism. In addition, when the correction of the detector when infragroup, that also increases the probability of false detection of synchronism.

Closest to the present invention is a device for synchronizing the cycles of as. C. the USSR № 1172052 class H 04 L 7/08, publ. 07.08.85, bull. No. 29, prototype, containing, as the proposed device, the detector clock element of the ban, the adder, the unit shift registers, a crucial node, the driver of such pulses, the cycle counter, the counter distorted signals, the block selection threshold. Moreover, the output of the detector clock jointly connected with the second input element of the ban and the first input of the adder, the output of which is connected to the signal input of the shift registers. The main output of the unit shift registers connected to the second input of the adder, and an additional output unit shift registers to the signal input of the decision making unit, which consists of the first block compare block of memory, the subtraction unit, the second unit of comparison and counter comparison. Thus the output of the first unit of comparison is connected to the control input of the memory block, the output of which is connected to the second input of the first unit of comparison and the first input of the subtraction unit. The second input of the subtraction unit is combined with data input of the memory block, the first input pervohody second unit of comparison. The output of the second unit of comparison is connected to the reset input of the counter comparison. While managing and clock inputs of the decision making node are, respectively, the first input of the second block comparison and the clock input of the counter comparison. The output of the decision making node is connected to the reset inputs of the memory block unit shift registers of the imaging unit cyclic pulses. The output of shaper cyclic pulses jointly connected to the first input element of the ban and the input of the cycle counter, the output of which is connected to the control input of the counter distorted signals. The output element of the ban is connected to the counting input of the counter distorted signals, the output of which is connected to the address input of the block selection threshold. The clock input of the unit shift registers combined with a clock input of the Recognizer clock, a casting site and shaper of such pulses, and the control input of the decision making node coupled to the output of the block selection threshold. When this signal input, a clock input of the detector clock and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices. The disadvantage of the prototype is a low noise immunity and performance, OBU clock, what prevents the accumulation response of the detector clock in the unit shift registers and lengthens the process of finding the clock. In addition, in the mode matching with regular repetition at some position loop false singlegroup and random distortion of the true singlegroup may shaper installation cycle pulses in the wrong phase, i.e., fails to sequential matching, although the true singlegroup will come at the specified position in the cycle.

Transmission feature of deterministic sequential clock is the frequency of its repetition on the same positions of the transmission cycle of the group signal. This Recognizer clock can recognize in the received multicast signal is not only true singlegroup, but false, randomly generated information on the positions of the cycle. When forming the output of the Recognizer trigger responses in the form of units (identified on singlegroup) and zeros (the unidentified singlegroup) the required accuracy of decision-making decisive node is achieved through the accumulation of responses in the unit shift registers. This leads to low noise immunity of the device to synchronize the cycles, since the arrival of synchroinformation in cells of the unit shift registers are not implemented. In addition, it lengthens the search process and, accordingly, increases the detection time of a cyclical clock. Recognition by the Recognizer clock code group information on the positions of the cycle leads to the accumulation of responses in cells of the unit shift registers corresponding to a false synchrogram. Mode matching with regular repetition at some position loop false singlegroup and random distortion of the true singlegroup may shaper installation cycle pulses in the wrong phase, i.e., fails to sequential matching, although the true singlegroup will come at the specified position in the cycle. These factors have high requirements to noise immunity and performance of the device for synchronization cycles.

Device for synchronizing the cycles contains Recognizer clock element of the ban, the adder, the unit shift registers, a crucial node, the driver of such pulses, the cycle counter, the counter distorted signals, the block selection threshold. Moreover, the output of the detector clock jointly connected with the second input element of the ban and the first input of the adder, the output of which is connected to the signal input blocky output unit shift registers - to the signal input of the decision making node. At this crucial node consists of the first block compare block of memory, the subtraction unit, the second unit of comparison and counter comparison. The output of the first unit of comparison is connected to the control input of the memory block, the output of which is connected to the second input of the first unit of comparison and the first input of the subtraction unit. The second input of the subtraction unit is combined with data input of the memory block, the first input of the first unit of comparison is the signal input of the decision making node. The output of the subtraction unit is connected to the second input of the second unit of comparison. The output of the second unit of comparison is connected to the reset input of the counter comparison. While managing and clock inputs of the decision making node are, respectively, the first input of the second block comparison and the clock input of the counter comparison. The output of the decision making node is connected to the reset inputs of the unit shift registers of the imaging unit cyclic pulses. The output of shaper cyclic pulses jointly connected to the first input element of the ban and the input of the cycle counter, the output of which is connected to the control input of the counter distorted signals. The output element of the ban is connected to the counting input of the counter distorted signals, you are the clock inputs of the detector clock casting site and shaper of such pulses, and the control input of the decision making node coupled to the output of the block selection threshold. When this signal input, a clock input of the detector clock and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices.

The technical result in the implementation of the invention is the increased robustness and performance of the device to synchronize the cycles achieved by the introduction of block select a valid number undistorted sync symbols, the block selection coefficient accounts, counter out of synchronism, the element OR the first element I. in Addition, at the crucial site introduces the second element And. While the output of detector clock is also connected to the second input of the first element And the first input of the first element And connected to the output device. The output of the first element And connected to the first input of the OR element. The second input element OR is connected to the output of the decision making node. The output element OR is connected to the reset input of the counter out of synchronism, the data input of which is connected to the output of the block selection coefficient accounts, and the counting input of the counter output from the synchronism connected to the enta And to the second input of which is connected to the output of the counter comparison. The output of the second element And is connected to the reset input of the memory block. The output of the second element is the output of the decision making node. In addition, the address input unit to specify a valid number of undistorted singlesymbol and block selection factor accounts jointly connected to the output of the counter distorted signals. The output unit selecting a valid number undistorted singlesymbol connected to the control input of the detector clock.

Thanks to the application of the detector clock correction distorted singlesymbol increases the robustness and performance of the device to synchronize the cycles, because the result of this operation, when the distortion of a certain number of pulses at the output of the detector clock generated single response and synchroinformation not excluded from the process of accumulation in the unit shift registers. In addition, with the introduction of the counter out of synchronism, OR element, and the first and second element And increases the immunity of the device to synchronize the cycles in the mode of synchronism, because with regular repetition at some position the CEC will change. The phase change of the shaper cycle pulses (true or false) is only possible in the case of distortion (or lack of) true singlegrouptimes (wherethe factor accounts for the counter out of synchronism) and the detection of a critical node clock (true or false). In addition, the maximum number k of undistorted singlesymbol in the detector clock and coefficientaccount counter out of synchronism adaptive change depending on the probability of erroneous reception of the synchronization signal, which provides in each specific case (at a certain value of the probability of erroneous reception clock) minimum recovery time, sequential matching, which will ensure the required immunity.

Conducted by the applicant's analysis of the prior art, including searching by the patent and scientific and technical information sources, and identify sources that contain information about the equivalents of the claimed invention, has allowed to establish that the applicant had not discovered similar, characterized by signs, identical with all the essential features of the claimed invention. The choice of perevalil to identify a set of essential towards perceived by the applicant to the technical result of the distinctive features in the claimed device, set forth in the claims. Therefore, the claimed invention meets the criterion of "novelty."

To check the compliance of the claimed invention, the criterion of "inventive step", the applicant conducted an additional search of the known solutions to identify signs that match the distinctive features of the prototype of the characteristics of the claimed device. The search results showed that the claimed invention not apparent to the expert in the obvious way from the prior art, as defined by the applicant. Not identified the impact of changes under the essential features of the claimed invention, to achieve a technical result. In particular, the claimed invention does not provide the following transformations: addition of known means of any known part attached to it according to certain rules, to achieve a technical result, in respect of which it is the effect of such additions; the replacement of any part of the other known means known part to achieve a technical result, in respect of which it is the effect of such a change; the exclusion of any part of the funds with a simultaneous drop the use of identical elements to enhance the technical result due to the presence in the vehicle is of such elements; the execution of a known drug or part of a known material to achieve a technical result due to the known properties of the material; the creation of tools, consisting of well-known parts, the choice of which and the relationship between them is carried out on the basis of known rules, recommendations and achievable technical result is due only to the known properties of the parts of this object and the relationships between them; change quantitative attributes or relations of signs, if known fact of the influence of each on the technical result and the new values of the signs or their relationship could be obtained from the known dependencies. Therefore, the claimed invention meets the criterion of "inventive step".

The invention is illustrated graphics, which depict: Fig.1 is a structural diagram of a device for synchronizing the cycles of Fig.2 is a block diagram of the detector of the clock of Fig.3 is a functional diagram of the shaper cyclic pulses of Fig.4 is a functional diagram of the counter out of synchronism, in Fig.5 is a functional diagram of the counter distorted the implement of the invention to provide the above technical result are the following.

Device for synchronizing the cycles contains Recognizer 1 clock, item 2 of the prohibition element 3 And the adder 4, block 5 shift registers, a crucial node 6, the imaging unit 7 cyclic pulses, item 8, OR, the counter 9 cycles, the counter 10 distorted signals, block 11 select a valid number undistorted singlesymbol, block 12 of the choice of the threshold, the block 13 ratio selection account, the counter 14 out of synchronism, the input signal 15, the clock input 16, output device 17. A crucial node 6 contains the block 18 comparison unit 19 of the memory block 20 subtraction unit 21 comparison, the counter 22 comparison and item 23 I. the Output of detector 1 clock jointly connected with the second input element 2 of the ban, the second input element 3 And to the first input of the adder 4, the output of which is connected to the signal input unit 5 shift registers. The main output unit 5 shift registers connected to the second input of the adder 4, and the additional output to the signal input of the decision making node 6. The signal input of the decision making node 6 is the first input unit 18 of the comparison. Thus the output of block 18 comparison is connected to the input of the control unit 19 of the memory, the output of which is connected to the second input unit 18 compared Ervin input unit 18 of the comparison signal is input decisive node 6. The output of block 20 of the subtractor is connected to the second input unit 21 of the comparison, the output of which is connected to the reset input of the counter 22 comparison. The output of counter 22 comparison is connected to the second input element 23 And. the Output element 23 And is connected to the reset input of block 19 of the memory. While managing and clock inputs of the decision making node 6 are, respectively, the first input unit 21 comparison and the clock input of the counter 22 comparison. Additional control input of the decision making node is the first input element 23 I. the Output of the decision making node 6 is the output element 23, which is connected to the reset inputs of the former (7 cyclic pulses, block 5 shift registers, and the second input element 8 OR. The output of the shaper 7 cyclic pulses jointly connected to the first input element 3 And the first input element 2, prohibition, and the input of the counter 9 cycles. The output of the counter 9 cycles connected to the control input of the counter 10 distorted signals. The output of the counter 10 distorted signals jointly connected to the address inputs of the block 11 select a valid number undistorted singlesymbol, block 12 of the choice of the threshold and the block 13 ratio selection account. The output of block 11 select a valid number undistorted singlesymbol podklad counter 14 out of synchronism and the counter 10 distorted signals. The output element 3 And connected to the first input element 8 OR the output of which is connected to the reset input of the counter 14 out of synchronism. To the data input of the counter 14 out of synchronism connected to the output of block 13 of the selection coefficient accounts.

The clock input of the shaper 7 cyclic pulses combined with a clock input detector 1 clock, unit 5 shift registers and decisive node 6. The control input of the decision making node 6 is connected to the output unit 12 of the choice of the threshold, and the complementary control input of the decision making node 6 is connected to the output of the counter 14 out of synchronism. When this signal input of the detector 1 clock, the clock input of the shaper 7 cyclic pulses and the output of the shaper 7 cyclic pulses are respectively the signal input 15, a clock input 16 and output 17 of the device.

Device sync cycles is as follows. At the signal input of the detector 1 clock group enters the digital signal containing the deterministic group of the synchronization signal that is repeated with a repetition rate of the cycles. Information items group code signal group information symbols, is identical to singlegroup, are formed occasionally armywide response in the form of a single pulse, coming next to the first input of the adder 4, the second input element 2 of the ban and the second input element 3 I. the control input of the detector 1 clock output unit 11 is supplied a valid number k undistorted singlesymbol. In Fig.2 presents a functional diagram of the detector 1 clock. For example, the length of the clock m=4, a structure (code) clock {m}=1101. The detector 1 clock consists of a shift register (DD6), the decoder clock (DD1.1, DD2), encoder (DD1.2, DD3.1-DD3.2, DD4, DD5.1-DD5.2), comparator (DD7, DD5.3). The shift register performs a conversion operation group of the digital signal at the input of DR shift register (DD6), from the sequence in the parallel code. During each clock interval in the shift register is written to one symbol of the received signal, and with the arrival of the next character previous moves to the next cell in the shift register. Thus, for m clock intervals in the register is written m character code combination. From the output of the shift register to the input of the decoder clock (DD1.1, DD2) in a parallel group served the signal. With the arrival of each clock pulse at clock input C of the shift register g Coder (DD1.2, DD3.1-DD3.2, DD4, DD5.1-DD5.2) is designed to generate binary numbers accurately detected singlesymbol. Comparing the device (DD7, DD5.3) performs the comparison operation numbers accurately detected singlesymbol in singlegroup (served on the input R of the comparator DD7) with a valid number k undistorted singlesymbol (served on the input Q of the comparator DD7). If the number is accurately detected singlesymbol greater than or equal to the allowable number k undistorted singlesymbol, the output element DD5.3, which is the output of the detector 1 clock generated single signal (response). Otherwise, the output of detector 1 is "zero" signal. The detector 1 clock can be implemented, for example, on the following chips: DD1 - CLN; DD2 - KID; DD3 - CLA; DD4 - CLA; DD5 - CLL; DD6 - CIR; DD7 - CSP.

The adder 4 is a parallel combinational adder, whose younger bit input of the first term (low-order bits of the n bit input and n-bit inputs of the second term are respectively the first and the second input of the adder, while the other (n-1) bit inputs of the first summand is connected to the source of the "zero" uriosity in one cycle) shift registers. United clock inputs and the United inputs reset shift registers are respectively a clock input and a reset input block 5 shift registers, and the signal inputs, the outputs of the last bits and outputs the first digits of all shift registers are respectively the signal input, main output and an additional output side 5 shift registers. Thus, the response of the detector 1 clock in the i-th clock interval, formed in the adder 4 with the previous account of the responses to the i-th position of the loop coming from the main output unit 5 shift registers. A new result of counting responses, larger one still written in the form n-bit binary number in the corresponding first cell (bits) shift registers block 5 shift registers. When this binary number recorded up to that in the first cell block 5 shift registers, and all other numbers are stored in subsequent similar cells, in parallel shifted by one digit, and the main output unit 5 shift registers to the second input of the adder 4 receives the result of counting responses (i+1)-th clock interval. If the response of the detector 1 clock (i+1)-th clock interlace 5 shift registers, and the other numbers stored in the same cell block 5 shift registers are shifted by one digit, and so on, Block 5 shift registers provides storage of account results of the responses to each position of the loop within the loop duration. The value of n determines the memory capacity of account results. At the same time the account of the responses to each of the positions of the cycle with an additional output unit 5 shift registers sequentially arrive at the signal input of the decision making node 6. In the final node 6, for example, in the i-th clock interval, the input binary number in parallel code representing the current account responses to the i-th position of the cycle, is simultaneously supplied to the first input unit 18 of the comparison, the data input block 19 memory and the second input unit 20 subtraction. In block 18 the comparison of the input number is compared with the binary number stored in block 19 of the memory and, if it exceeds the number of block 19 of the memory, the output unit 18 comparison is formed impulse, which, when the input control unit 19 memory provides the Erasure of the old and the new record (input) number. The input unit 18 of the comparison are equal to a binary number. If the input number is equal to or less than the number greaseable the current account responses to any of the position loop, which is then compared to the results account for the subsequent positions of the cycle. The resulting difference between the number of block 19 of the memory and the input number) at the output of block 20 subtraction in the form of binary numbers in parallel code is compared in block 21 comparison with a threshold number d received at its first input (which is the controlling input of the decision making unit (6) from the output unit 12 of the choice of the threshold. In this case, if the number from the output of block 20 of the subtraction is less than the threshold number d, the output of the second block 21 comparison to the reset input of the counter 22 comparison is "single" (prohibiting) the potential that sets and keeps it in the "zero" state. When the i-th clock interval number from the output of block 20 of the subtraction is equal to or greater than the number d, the output of the second block 21 comparison comes "zero" (enabling) potential, and the counter 22 comparison produces a single clock pulse received at its clock input, which is the clock input of the decision making node 6. If the largest binary number written in block 19 of the memory will exceed each of the N-1 subsequent numbers coming one after another with an additional output unit 5 shift registers, by an amount equal to or greater threshold number d, the counter 22 with the first pulse signal, which is supplied to the second input element 23 I. If the counter 14 out of synchronism made countingtimes "neopoznannyi" true singlegroup, at its output, a signal is generated logical unit, which receives at the first input element 23 And permitting the passage of a single pulse signal output from the counter 22 comparison of the output element 23, which is the output of the decision making node 6. The signal at the output of the decision making node 6 is an output clock signal which is supplied to the reset inputs of block 19 of the memory unit 5 shift registers of the imaging unit 7 cyclic pulses, and also to the second input element 8 OR. As a result, the block 19 of the memory block 5 shift registers and the counter 14 out of synchronism are reset to "zero". Then from the output of block 21 comparison begins to act prohibiting "single" potential and the counter 22 comparison is also reset to "zero". The output signal synchronized final node 6 is the phase shaper 7 cyclic pulses so that the output 17 of the device start coming regularly following cycle pulses, a time coinciding with the response of the detector 1 clock on the true singlegroup. the inalsa again when the next synchronization signal of the decision making node 6 will be formed only if the detection of the synchronization signal (single pulse at the output of the counter 22 comparisons) and the failure detection of synchronism (single pulse at the output of the counter 14 out of synchronism). When the synchronization signals of the decision making node 6 will change the phase of the initial installation of the driver 7 cyclic pulses, if the temporary position of a cyclical clock has changed or dot clocktimes distorted (more than k singlesymbol). Thus, the counter 14 out of synchronism counts the number of consecutive pulses of the failure of the synchronization signal generated by the element 2 of the ban. When you reach the state accountsthe output of the counter 14 and the output of the synchronism signal appears permits the formation of a critical node 6 of the synchronization signal. When the detection of the true clock (at any state of the counter 14 out of synchronism) or the formation of the output of the decision making node 6 of the synchronization signal, the counter 14 out of synchronism is reset to "zero". Blocks 18 and 21 comparison can be performed, for example, in the form of n-bit companyh operands, as well as the sign of their equality supplied to first and second inputs of the blocks. Thus the outputs of the first and second block are output P>Q comparator (for example, see Fig.2, the element DD7). Block 19 of the memory may be in the form of n-bit register with parallel input. When this data inputs, a control input, a reset input and output unit 19 memory is accordingly a data input, a clock input, a reset input and output data n-bit register. Block 20 subtraction can be performed in a full n-bit parallel adder. The bit width of the adder is provided a serial output connection of the transfer of the adder least significant bits with a carry-in input of adder senior ranks. To perform a full adder operation of subtracting a number from the memory block 20, arriving at the first input of the subtraction unit is subjected to inversion, and the number coming from the additional output unit 3 shift registers to the second input of the subtraction, inversion is not exposed. Shaper 7 cyclic pulses and the counter 22 comparison and can be made in the form of serially connected binary-synchronous decimal counter and decoder (see Fig.3, the elements DD1, DD2, DD.3.2). While the reset input and binary-decimal counter (DD1), connected through the element is NOT (DD 3.1). The clock inputs of the former (7 cyclic pulses and the counter 22 are clock input With a binary-decimal counter (DD1). The outputs of the counter 22 of the comparison is output element (DD.3.2). The output of the shaper 7 cyclic pulse is output element OR (DD4). During this phase counter 22 comparison is performed by setting to "zero" the meter, and the phasing of the shaper 7 cyclic pulses, in addition, be carried out by passage of the synchronization signal from the reset input of the driver 7 to the output element OR (Fig.3, the element DD4). Shaper 7 cyclic pulses can be implemented, for example, on the following chips: DD1 - KIE; DD2 - KID; DD3 - CLN; DD4 - K555l.

In Fig.4 shows a functional diagram of the counter 14 out of synchronism, which consists of a counting device (DD1), the comparison circuit (DD2) and storage devices (DD3.1-DD3.2, DD4). The counting device is intended for counting consecutive pulses of a failure of the synchronization signal, which are received from the output element 2 of the ban on the clock input CU meter. To the reset input of the counter with the output element 8 OR receives pulses identify the true clock the CTB state maximum account equal to the ratio of accountsthat from the output of block 13 of the choice of the coefficient of account is served in binary code input Q comparing device (DD2). The storage device is for storing a status signal of maximum accumulation counter 14 out of synchronism, which is determined by the comparing device. Reset storage device (DD4) in the "zero" state is received at a reset input of the counter 14 and the output of the synchronism signal "reset". The output of the storage device is the output of the counter 14 out of synchronism. The counter 14 out of synchronism can be implemented, for example, on the following chips: DD1 - KIE; DD2 - CSP; DD3 - CLN; DD4 - K555TM2.

The process of forming the threshold numbers d for the final node 6, the allowable number k undistorted singlesymbol for detector 1 clock and factor accountsfor counter 14 out of synchronism as follows. At the first input element 3 of the prohibition act, the pulse shaper 7 cyclic pulses, and the second input pulses (feedback) of detector 1 clock. As a result, the output element 2 zipsignals accept binary information sequence. Counting the number R of distorted signals during the time the account is quite a large number Q of such pulses, it is possible with some degree of accuracy periodically to determine the probability (castest) erroneous reception of the synchronization signal according to the formula PocR/Q, i.e., to produce a current assessment of the degree of distortion of the received signal. While the counter 10 distorted signals counts distorted signals, and the counter 9 cycles - the total number Q of signals transmitted over a given period of time. The capacity of the counter 9 cycles is equal to the value of Q. After counting each Q cycle pulses at its outputs a single pulse, which is supplied to the control input of the counter 10 distorted signals. In Fig.5, for example, presents a functional diagram of the counter 10 distorted signals intended for counting erroneously received signals. The counter 10 distorted signals consists of a counting device (DD1) and storage devices (DD2) and delay lines. At the counting input of the counter 10 distorted signals from the output element 2 of the prohibition of the signals of logical "unit" or "zero". When this signal is detected undistorted clock. Therefore, the counter 10 distorted signals provides counting only distorted signals corresponding to the true synchrogram. These signals are counted using a counting device (DD1). Storage device (DD2) is designed to capture and store the result (the number of distorted signals R) during the observation period (the number of cycles Q). The storage device provides storage number of distorted signals R before coming from the counter 9 cycles on the control input of the counter 10 distorted signals signal the end of the observation period. He served through the element is NOT DD3 to the reset input of the counter (DD1) and the input mode of the storage device (DD2). Then in the storage device is overwritten by the new value of R. the delay Line is designed to generate the recording signal at the time of admission to multibit input data storage device, the binary number R of distorted signals. The delay line can be constructed, for example, the elements are NOT. When this delay time is calculated as the delay time of signal propagation in the counter unit and is determined by the number of items included (see, for example, Venini

tLZ=qtZV.R. cf,

where q is an even number of elements NOT involved in the delay of the signal, tZV.R. withthe time delay distribution in the element is NOT equal to half the sum of the delay time distribution of the signal when switching on and off of the integrated circuit (for example, for a chip CLN tZV.p.cp=20 NS) (see, for example, Avanesyan, R., Levshin VP of Integrated circuits TTL, TTLS: a Handbook. - M.: Mashinostroenie, 1993. - S. 76). The counter 10 distorted signals can be implemented, for example, on the chip: DD1 - KIE; DD2 - CIR 13; DD3 - CLN. Element 2 of the prohibition may be made of serially connected elements of the EXCLUSIVE OR element And. at the first input of EXCLUSIVE OR serves cycle pulses. It is connected with the first input element I. the second input of the EXCLUSIVE OR pulses (feedback) from the detector 1 clock. The output of EXCLUSIVE OR connected to the second input of the element I. the Output element And an output element 2 of the ban.

In Fig.6 shows a functional diagram of the counter 9 cycles, which consists of a counting device (DD1), decoder (DD2) and element (DD3). The counting device is intended for calculation of Q cycles. The decoder prednaznachennogo device, the reset which is done synchronously (on the positive edge of a cyclical pulse at the input of the counting device). The output of the counter 9 cycles is output element (DD3). The counter 9 cycles can be implemented, for example, on the chip: DD1 - KIE; DD2 - KID; DD3 - CLN.

Unit 11 select a valid number undistorted signals, block 12 of the choice of the threshold and the block 13 ratio selection account depending on the value of the number R, is recorded in the counter 10 distorted signals, make the selection, respectively, of a certain number k undistorted signals, the threshold number d and coefficientcounter out of synchronism. The selected number k, d, andoutputs of blocks 11, 12 and 13 in parallel code served, respectively, to the control input of the detector 1 clock to the control input of the decision making node 6 and the input of the counter 14 out of synchronism. Unit 11 select a valid number undistorted signals, block 12 of the choice of the threshold and the block 13 ratio selection accounts can be made in the form of permanent storage devices (for example, on the chip CRF), memory elements which are recorded the results rscd> counter out of synchronism, depending on the probability of erroneous reception of the synchronization signal (see Kalinnikov centuries, tashlinskii A., methods of finding the internal parameters of the system frame synchronization in parallel and recircularii search. -Ulyanovsk: UFWOC, 2002. 35 S. - Dept. in ZUNI the defense Ministry 23.09.02. No. b, publ. SNR, ser. B., vol. 61, 2002). The value of the measured probability of erroneous reception of the synchronization signal ROSfrom the output of the counter 10 distorted signals is fed to the address inputs of permanent storage devices units 11, 12 and 13, the outputs of which are the output numbers k, d, and. Thus, during the time of account Q in the detector 1 clock served a certain acceptable number k undistorted singlesymbol, at the crucial site 6 - threshold number d, and the counter 14 and the output from the synchronism factor accountsthat can take in each case one of the h discrete values (gradation) depending on signal quality. The required number of gradations h numbers k, d, andis determined on the basis of maintaining the probability of false detection of the synchronization signal within the required limits at various and skazanych of singlesymbol unit 11, threshold numbers drunit 12 and the coefficientsrthe counter output of the matching unit 13 can be written in the form:

kr=F1(ArPoc< Br),

dr=F2(ArPoc< Br),

r=F3(ArPoc<B),

where F1F2F3- pre-selected rules, respectively, for block 11 select a valid number undistorted singlesymbol, block 12 of the choice of the threshold and the block 13 selection factor accounts for which value of Poctaking a value within the r-th period (r varies from 1 to h) dimensions, given in compliance with the valid values of krundistorted singlesymbol, the threshold number of drand coefficientrcounter out of synchronism; Andrand Inrrespectively the lower and upper bound values of ROSfor the r-th interval.

The required noise immunity of the device, which is determined by the probability of false detection of the synchronization signal, is ensured by the choice of the law of formation of the numbers krrfor block 13 selection coefficient accounts for the respective measured values of Rocwithin any r-th interval with boundaries Andrand Inraccording to the principle: the higher the value of POS, the greater must be the number of krdrandr. At the same time achieved by reducing recovery time simultaneity, since the time interval of observation of the response of the detector 1 clock at the end of which the decision on the phase of the clock cycle, adaptive changes depending on the magnitude of ROSand in each specific case (at a certain value of POSis approaching the minimum possible, which will ensure the required immunity. The Q-value, which determines the ratio of the account of the counter 9 cycles, must be chosen, on the one hand, large enough to provide the desired precision of the estimate of the error probability POSa single character, on the other hand is sufficiently low to ensure that the measurement of POSbetween two failures of synchronism in cycles and tracking of changes to the conditions of communication. If we assume that failures sinhronizovan signals, in practice, the value of Q can be chosen as:

where1- the upper boundary value of POSwithin the first measurement interval, which corresponds to the lowest values of the numbers k1d1and1; [] means rounding to an integer.

For determining the quality characteristics of the device to synchronize the cycles were built his analytical (Kalinnikov centuries, tashlinskii A., an Analytical model of the system frame synchronization in parallel and recircularii search clock. - Ulyanovsk: UFWOC, 2002. 28 S. - Dept. in ZUNI the defense Ministry 02.10.02. No. b, publ. SNR, ser. B., vol. 61, 2002) and simulation model (Kalinnikov centuries, tashlinskii A., a Simulation model of the system frame synchronization in parallel and recircularii search clock. - Ulyanovsk: UFWOC, 2002. 32 S. - Dept. in ZUNI the defense Ministry 02.10.02. No. b, publ. SNR, ser. B., vol. 61, 2002), on the basis of which the technique of finding the numbers k, d, anddepending on the probability of erroneous reception of the synchronization signal (see, Kalinnikov centuries, tashlinskii A., methods of finding the internal parameters of the system frame synchronization in parallel and recircularii popozudas under the following initial data:

- the length of the transmission cycle N=1200;

- length singlegroup m=9 (000111011);

the repetition period of the transmission cycle TC=2.5 MS.

- the probability of erroneous reception of a single character ROsh=510-2.

The result of simulation of the device showed the following characteristics (in parentheses are the characteristics of the prototype):

- average time to restore the synchronism of 14.7 MS (25 MS);

- the probability of false detection of synchronism 2,510-3(610-3).

The simulation confirmed the achievement of the technical result is to increase speed and noise immunity - during implementation of the invention.

The above data confirm that the implementation of the use of the claimed device the following cumulative conditions:

the tool embodying the claimed device in its implementation, is intended for use in the receiving device sync cycles of transmission of discrete messages;

for the claimed device, as it is characterized in the claims, confirmed the possibility of its implementation using the steps described in the application or known prior to the date of prior is to provide for the achievement perceived by the applicant of the technical result.

Thus, the claimed invention meets the criterion of "industrial applicability".

Claims

Device for synchronizing the cycles containing Recognizer clock element of the ban, the adder, the unit shift registers, a crucial node, the driver of such pulses, the cycle counter, the counter distorted signals and the block selection threshold, and the output of the detector clock jointly connected to the second input element of the ban and the first input of the adder, the output of which is connected to the signal input of the shift registers, the main output of which is connected to the second input of the adder, and an additional output unit shift registers connected to the signal input of the decision making unit, which consists of the first block compare block of memory block subtraction, the second unit of comparison and counter comparison with the first unit of comparison is connected to the control input of the memory block, the output of which is jointly connected to the second input of the first unit of comparison and the first input of the subtraction unit, the second input is combined with the first input of the first unit of comparison, and also to the input of the data memory block and the signal is input re the Deposit and the first input of the second Comparer, a second input connected to the output of the subtraction unit, and the output of the second unit of comparison is connected to the reset input of the counter comparison with the final node is connected to the reset inputs of the former (cyclic pulses and block shift registers, a clock input which is combined with the clock inputs of the detector clock, a casting site and shaper of such pulses, the output of which is jointly connected to the first input element of the ban and to the input of the cycle counter, the output of which is connected to the control input of the counter distorted signals, and to the counting input of the counter distorted signals connected to the output element of the ban, moreover, the output of the counter distorted signals are connected to the address input of the block selection threshold, the output of which is connected with the control input of the decision making node and the signal input of the detector of the clock, the clock input of the shaper cyclic pulses and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output device, characterized in that it introduced the unit of choice for a valid number undistorted singlesymbol, the block selection coefficient accounts, the counter output from the synchronism is inen with the output of the counter distorted signals, the output of which is also connected to the address input of the block selecting valid number undistorted singlesymbol, the output of which is connected to the control input of the Recognizer clock, and the output of the block selection factor accounts connected to the data input of the counter out of synchronism, a counting input connected to the output element of the ban, and the reset input of the counter output from the synchronism is connected to the output element OR the first input connected to the output of the first element And the first input connected to the output of the shaper cyclic pulses, and the second input of the first element And is connected to the output of the detector clock the second input element OR is connected to the output of the decision making node, and the output of the decision making node is the output of the second element And, optionally entered at a crucial node, the second input of the second element And is connected to the output of the meter comparison, and the first input of the second element And connected to the output of the counter out of synchronism, and the output of the second element And is connected to the reset input of the memory block and the first input of the second element And is managing additional entry of the decision making node.

 

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SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

FIELD: communications.

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1 dwg

FIELD: digital communications;

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1 cl, 2 dwg

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1 cl, 1 dwg

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1 dwg

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2 cl, 3 dwg

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2 cl

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2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

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1 cl, 9 dwg

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