A method of manufacturing somestrange field-effect transistor structure supercarsoflondon bipolar transistor

 

Usage: microelectronics, technology of manufacturing field-effect transistors with the structure of a metal-oxide-semiconductor. The essence of the invention: method of manufacturing a transistor to create the first dielectric etched window in the first dielectric vertical etching separately for the area of the drain and source with overlapping Windows “beak” of the first dielectric in the direction of the dielectric obtained by local oxidation, and etching depth, providing playmost dielectric in the Windows with the silicon surface, and the distance between the Windows for the area of the drain and source greater than the width of the gate field-effect transistor, produce etching of horizontal and inclined above the “beak” areas of the second dielectric to the first layer of polycrystalline silicon, and after etching the first layer of polycrystalline silicon to produce the deposition of the second layer of polycrystalline silicon alloyed to create a weakly doped regions of the drain and source of the field-effect transistor, harass horizontal and slanted, above the regions of the “beak”, the areas of the second layer of polycrystalline silicon to silicon and the first dielectric oxidize the silicon surface and the support the third layer of polycrystalline silicon, form the shutter, form a highly doped region of the drain and source diffusion from the first polycrystalline silicon and low-alloy region of the drain and source diffusion from the second polycrystalline silicon. The technical result of the invention is a full samoobladanie at the same time all major elements of the field-effect transistor relative to each other with the possibility of somestringvalue the length of the shutter to values significantly lower values of the minimum size of the lithograph. 1 S. and 2 C.p. f-crystals, 8 ill.

The scope of the invention is microelectronics, namely the manufacturing technology of the mass field-effect transistors with the structure of a metal-oxide-semiconductor (MOS transistors).

The technology of manufacturing the field-effect transistor is continuously being improved, primarily due to the success of modern lithography, providing the possibility of gradual decrease of the minimum size of an essential element of the transistor is the length of the shutter (in serial products to 0.25 microns and below).

Increasingly, the technology of manufacturing the field-effect transistor used methods samoobladanie elements travesing metal contacts to the areas of sinks and sources of the transistor [1], polycrystalline silicon electrodes with runoff and stokovoj areas of the field-effect transistor [2, 3].

However, in the known methods there are no methods full (or adopted an alternative term in the technical literature for bipolar technology “supersposobnosti”) at the same time all major elements of the field-effect transistor - a “window under the transistor dielectric”. “polycrystalline silicon electrodes to the areas of the drain and source”, “side of the dielectric gate spacer”, “metallic coatings on the polycrystalline silicon electrodes and gate” that allows you to get the maximum gain reduction of the area of the transistor, to minimize the individual elements of the structure of the field-effect transistor, and means to improve the quality and the percentage of output transistors and, in General, circuits for field-effect transistors.

Closest to the invention is a method of manufacturing supercarsoflondon bipolar transistor [4], including the formation on the surface of the silicon wafer, the first dielectric layer, etching it Windows with vertical walls below the base of the transistor, the deposition of the first layer of polycrystalline silicon and doping it mixed tsinia on lithography, the formation of the photoresist mask, the emitter window so that the boundaries of the emitter window in the photoresist pass over the vertical sections of the second dielectric layer formed on the steps of the window in the first dielectric layer, and are located no closer than one error of alignment in lithography from each side wall of the vertical sections of the second dielectric, etching horizontal surfaces of the second dielectric to the first layer of polycrystalline silicon, the etching of the first layer of polycrystalline silicon, silicon doping to create an active base region, forming in the Windows parietal insulator (spacer), the deposition of the second layer of polycrystalline silicon, doping it with impurities of the emitter, the formation of annealing the base and emitter regions by diffusion of an impurity from the polycrystalline silicon, create contacts to them and metallization.

In Fig.1.1-1.4 presents the main stages of manufacture supercarsoflondon bipolar transistor in accordance with a prototype [4].

In Fig.1.1 shows a section of the structure after forming on the surface of the plate (1) of the first dielectric layer (2), etching it under Windows base (3), the deposition of the first layer of police the two errors of alignment in lithography, the formation of the mask of photoresist (6) in such a way that the boundaries of the emitter window in the photoresist pass over the vertical sections of the second dielectric layer.

In Fig.1.2 shows operations: vertical plasma-chemical etching of the horizontal sections of the second dielectric (7) to the first layer of polycrystalline silicon, etching the first layer of polycrystalline silicon to silicon (8), silicon doping (9).

In Fig.1.3 shows operations of: forming a wall surface of the insulator (spacer) (11) plasma-chemical etching horizontal sections (10) of deposited dielectric for forming the spacer.

In Fig.1.4. shows operations: the deposition and doping of the second layer of polycrystalline silicon (12), the formation of annealing emitter (14) and base (15, 16) regions by diffusion of impurities from the polycrystalline silicon, create contacts to them and metallization (13).

As follows from the consideration of the technical solutions of the prototype in the method of manufacturing a bipolar transistor uses superomedia all the basic elements of a bipolar transistor between themselves, starting with “box under base dielectric, forming the base of the polycrystalline silicon electrodes”, misscrystaleyes silicon emitter electrode”, formation of diffusion regions of the base and the emitter”.

The main advantage of the technical solution of the method that is specified in the prototype, is scaling (reducing) the size of the emitter to values smaller than the minimum size of the lithograph, which creates the opportunity for significant improvement in quality and reduction in size of the transistor and in General improve the integration and percent yield of chips that use this type of transistor.

The problem to which the invention is directed, is the achievement of the technical result consists in the use of methods samoobladanie (supersposobnosti) major elements of the field-effect transistor and somestringvalue shutter in the process of manufacturing the field-effect transistor to a value less than the minimum size of the lithograph.

To achieve the mentioned technical result in the method of manufacturing a transistor, comprising forming on the surface of the silicon wafer, the first dielectric layer, etching it Windows with vertical walls under the field-effect transistor, the deposition of the first layer of polycrystalline silicon, doping his admixture of the desired type provia alignment in lithography, forming a photoresist mask so that the boundaries of the Windows in the photoresist pass over the vertical sections of the second dielectric layer formed on the steps of the window in the first dielectric layer, and are located no closer than one error of alignment in lithography from each side wall of the vertical sections of the second dielectric, etching horizontal surfaces of the second dielectric to the first layer of polycrystalline silicon, the etching of the first layer of polycrystalline silicon, forming the side walls of the first layer of polycrystalline silicon wall surface of the dielectric, the deposition of the second layer of polycrystalline silicon, doping his admixture of the desired conductivity type with the desired concentration, thermal annealing for the formation of regions of the transistor by diffusion from polycrystalline silicon, the formation of contacts to the electrodes of polycrystalline silicon and metallization, the first dielectric layer to create a method of local oxidation of silicon through a mask of silicon nitride around the area of the field-effect transistor, produce etching Windows in the first dielectric vertical etching separately for the area of the drain and source with perekriti the management of the Windows in the dielectric, providing playmost dielectric in the Windows with the silicon surface, and the distance between the Windows for the area of the drain and source greater than the width of the gate field-effect transistor, produce etching of horizontal and inclined above the “beak” areas of the second dielectric to the first layer of polycrystalline silicon, and after etching the first layer of polycrystalline silicon to produce the deposition of the second layer of polycrystalline silicon, alloyed type impurity with the end of the grace necessary to create a weakly doped regions of the drain and source of the field-effect transistor, harass horizontal and inclined above the “beak” areas of the second layer of polycrystalline silicon to silicon and the first dielectric, is formed on the silicon surface and the sidewalls of the second polysilicon dielectric layer is not less than the thickness of the required gate dielectric, precipitated the third layer polycrystalline silicon alloyed type impurities with a concentration required for the formation of the gate polysilicon of this type FET, thermal annealing to form a heavily doped region of the drain and source of diffuse polycrystalline silicon.

Thus, the important features of the present invention is that the first dielectric layer to create a method of local oxidation of silicon through a mask of silicon nitride around the area of the field-effect transistor, produce etching Windows in the first dielectric vertical etching separately for the area of the drain and source with overlapping Windows “beak” of the first dielectric in the direction of the dielectric obtained by local oxidation, and the depth of etching Windows in the dielectric, providing playmost dielectric in the Windows with the silicon surface, and the distance between the Windows for the area of the drain and source greater than the width of the gate field-effect transistor, produce etching of horizontal and inclined, above the regions of the “beak”, areas of the second dielectric to the first layer of polycrystalline silicon, and after etching the first layer of polycrystalline silicon to produce the deposition of the second layer of polycrystalline silicon, alloyed type impurities with a concentration required to create a weakly doped regions of the drain and source of the field-effect transistor, harass horizontal and slanted, above the regions of the “beak”, the areas of the second layer polikristallichyeskogo silicon dielectric layer is not less than the thickness of the required gate dielectric, precipitated third layer of polycrystalline silicon, alloyed type impurities with a concentration required for the formation of the gate polysilicon of this type FET, thermal annealing to form a heavily doped region of the drain and source diffusion from the first polycrystalline silicon and a weakly doped region of the drain and source diffusion from the second polycrystalline silicon.

This set of distinctive features allows to solve the problem - full samoobladanie (or supersposobnosti) at the same time all major elements of the field-effect transistor relative to each other. The main advantage of this method is the possibility of somestringvalue the length of the shutter to values significantly lower values of the minimum size of the lithograph.

In Fig.2.1-2.4 presents the main stages of manufacture somestrange field-effect transistor.

In Fig.2.1 shows a section structure of the transistor after forming on the surface of the plate (1) of the local oxidation of the first dielectric layer (17), etching it Windows with vertical walls (18) under the area of the drain and source of the field-effect transistor (dotted line show the Oia (4), alloying of its impurity, the deposition of the second dielectric layer (5) with a thickness of not less than two errors of alignment in lithography, forming a mask of photoresist (6) so that the boundaries of the Windows in the photoresist pass over the vertical sections of the second dielectric layer.

In Fig.2.2 shows operations: etching horizontal and inclined - not shown) plots of the second dielectric (7) to the first layer of polycrystalline silicon, etching the first layer of polycrystalline silicon to silicon (8) and to the first dielectric in the region of the beak (not shown in the figure).

In Fig.2.3 shows operations: the deposition of the second layer of polycrystalline silicon on the horizontal (19 - shown in the drawing by the dotted line) and vertical (20) surfaces, doping type impurities with a concentration required for the subsequent formation of the low-alloy diffusion regions of the drain and the source, etching horizontal and inclined - not shown) plots of the second layer of polycrystalline silicon to silicon (21) and to the first dielectric in the region of the beak (not shown), the oxidation of the silicon surface and the second polycrystalline silicon on the thickness of the gate diastolicheskoe silicon (22), doping type impurities with a concentration required for the formation of the gate polysilicon thermal annealing for the formation of weakly and heavily doped regions of sinks and sources (22 and 23) of the transistors, the diffusion of the first and second layers of polycrystalline silicon contacts to the electrodes of polycrystalline silicon and metallization (13).

As follows from the consideration of the proposed technical solutions in the method of manufacturing samosochranienija field-effect transistor applied methods full samoobladanie (or supersposobnosti) at the same time all major elements of the field-effect transistor - “window in the dielectric under the region of the field-effect transistor”, “polycrystalline silicon electrodes to the areas of the drain and source”, “side of the insulator (spacer) and polycrystalline silicon gate”, “metallic coatings on the polycrystalline silicon electrodes and the gate - to each other, so as to maximize the gain on the lower area of the transistor, and thus by its parameters, and the percentage of output transistors, means and circuits based on them.

The main advantage of technical solutions predloga topological dimension (or the minimum size of the lithograph), that creates the possibility to create a way camomilabarbieri field-effect transistor with a significant improvement in the key parameters of the transistor is determined by the length of the shutter determining the performance of the transistor and increase the degree of integration in the production of chips on this type transistors.

In the proposed method fundamentally change the order of the manufacturing regions of the FET.

Instead of the traditional sequence in the known methods:

- the formation of the transistor gate length determined by the minimum size of the lithograph,

- creation side of the gate dielectric - spacer,

- formation regions of the drain and source electrode and plating, when samosbernymi elements of the transistor were “the gate of the transistor” and “spacer under the bolt, and the sizes of sinks and sources and contacts to them was determined by the magnitude of the errors of alignment and minimum size of the lithograph in the proposed method, the following sequence:

- formation regions of the drain and source electrodes to them,

- formation side of the insulator (spacer) at the electrodes to the drain and the source,

- the formation of the window under the gate length, suspectsmore lithography to obtain the minimum sizes in submicron.

In addition, to reduce the capacitance of the gate-source and gate-drain field-effect transistor, the proposed method is proposed to increase the thickness of the dielectric between the gate of the third layer of polycrystalline silicon and electrodes to the drain and the source (formed from the first layer of polycrystalline silicon). To this end, the oxidation of silicon and the second layer of polycrystalline silicon is carried out after forming the side portions of the second layer of polycrystalline silicon and thermal annealing, forming low-alloy region of the drain and source diffusion from the ends of the second layer of polycrystalline silicon, lying on silicon, and the oxidation is carried out until complete processline side portions of the second layer of polycrystalline silicon.

Then the vertical plasma-chemical etching to remove the oxide only with silicon (prokalennye side areas of the second layer of polycrystalline silicon is not etched) to form on the surface of the silicon necessary for the thickness and quality of the gate dielectric.

A possible way to reduce the resistance of the electrodes to the drain regions and source and polycrystalline silicon gate can be a way of drawing on p layers.

Conducted patent studies have shown that the set of features of the present invention is a novel that proves the novelty of the proposed method.

In addition, patent research showed that in the literature there are no data showing the effect of the distinguishing features of the claimed invention to achieve a technical result, which confirms the inventive step of the proposed method.

Example. On the surface of the monocrystalline wafer EFC 4, 9 (100) form a standard nitride mask sublayer of silicon dioxide to create a field-effect transistor, is formed using local oxidation of the first dielectric thickness of 0.6 μm, through a mask of photoresist is formed in the first dielectric window under the drain region and the region of origin, precipitated the first layer of polycrystalline silicon of a thickness of 0.25 μm by pyrolysis of monosilane at a temperature of 640With, are implanted into the layer of polycrystalline silicon boron with a dose of 600 mkcol/cm2and energy of 30 KEV, precipitated layer of the second dielectric by pyrolysis TEOS at 715With a thickness of 0.4 μm, through a mask of photoresist conduct etching of the second dielectric layer to the imported from Germany who Rennie thickness of 0.15 μm at a temperature of 640C decomposition of monosilane, implanted him with boron with a dose of 5 mcal/cm2vertical plasma-chemical etching poison horizontal and inclined sections of polycrystalline silicon, is formed by oxidation of the gate dielectric on silicon and the side surface of the second layer of polycrystalline silicon is precipitated by the third layer of polycrystalline silicon 0.2 μm, implanted him with arsenic with a dose of 1000 mkcol/cm2, and then annealed structure at a temperature of 850C, plasma-chemical etching through a mask of photoresist to form a gate made of polycrystalline silicon using a mask of photoresist to expose the second dielectric contact window to the polycrystalline silicon electrode to the drain and the source and form a metal wiring made of aluminum.

The example described above, obtaining camomilabarbieri n-channel field-effect transistor with long shutter 0,35 µm with a minimum size of 0.8 μm lithography is a special case that uses the proposed method. The proposed method can be used to create also camomilabarbieri p-channel field-effect transistor complementary pair of field-effect transistors fever

1. The VLSI technology. Edited by S. ZEE. Book 2. P. 222 (Fig.11. 19a).

2. RF patent N2106719 priority from 10.03.98,

3. RF patent N2141148 priority from 10.11.99,

4. RF patent N2110868 priority from 09.11.95,

Claims

1. A method of manufacturing somestrange field-effect transistor structure supercarsoflondon bipolar transistor, comprising forming on the surface of the silicon wafer, the first dielectric layer, etching it Windows with vertical walls under the field-effect transistor, the deposition of the first layer of polycrystalline silicon, doping his admixture of the desired conductivity type with the required concentration, the deposition of the second dielectric layer with a thickness of not less than two errors of alignment in lithography, forming a photoresist mask so that the boundaries of the Windows in the photoresist pass over the vertical sections of the second dielectric layer formed on the steps of the window in the first dielectric layer, and are located no closer than one error of alignment in lithography from each side wall of the vertical sections of the second dielectric, etching horizontal surfaces of the second dielectric to the first layer polinkah first layer of polycrystalline silicon wall surface of the dielectric, deposition of the second layer of polycrystalline silicon, doping it with admixture of a desired type of conductivity required concentration, thermal annealing for the formation of regions of the transistor by diffusion from polycrystalline silicon, forming contacts to the electrodes of polycrystalline silicon and metallization, wherein the first dielectric layer to create a method of local oxidation of silicon through a mask of silicon nitride around the area of the field-effect transistor, produce etching Windows in the first dielectric vertical etching separately for the area of the drain and source with overlapping Windows “beak” of the first dielectric in the direction of the dielectric obtained by local oxidation, and the depth of etching Windows in the dielectric, providing playmost dielectric in the Windows with the silicon surface, and the distance between the Windows for the area of the drain and source greater than the width of the gate field-effect transistor, produce etching of horizontal and inclined above the “beak” areas of the second dielectric to the first layer of polycrystalline silicon, and after etching the first layer of polycrystalline silicon to produce the deposition of the second layer peyrovani areas of the drain and source of the field-effect transistor, poison horizontal and inclined above the regions of the “beak” area of the second layer of polycrystalline silicon to silicon and the first dielectric, is formed on the silicon surface and the sidewalls of the second polysilicon dielectric layer is not less than the thickness of the required gate dielectric, precipitated the third layer polycrystalline silicon alloyed type impurities with a concentration required for the formation of the gate polysilicon of this type FET, thermal annealing to form a heavily doped region of the drain and source diffusion from the first polycrystalline silicon and low-alloy region of the drain and source diffusion from the second polycrystalline silicon.

2. The method according to p. 1, in which the oxidation of the silicon surface and the second polycrystalline silicon is preceded by thermal annealing for the formation of low-alloy regions of the drain and source diffusion from the second polycrystalline silicon, and the oxidation of the silicon surface and the second polycrystalline silicon is made to the complete oxidation of the second layer of polycrystalline silicon, and then make a removal of the oxide grown on silicon, with pumps.1, in which immediately after doping impurities of the first and third layers of polycrystalline silicon layers on polycrystalline silicon are bonded and, together with them etched layers policydb metals.

 

Same patents:

The invention relates to methods of manufacturing field-effect transistors with the structure of a metal-oxide-semiconductor - MOSFETs
The invention relates to microelectronics, and is intended for the manufacture of p-channel MOS LSI with a high voltage level

The invention relates to semiconductor technology and can be used in the manufacture of Schottky field-effect transistors

The invention relates to microelectronics and can be used in various types of integrated circuits with a high degree of integration

FIELD: technologies for making transistors.

SUBSTANCE: method includes following stages: precipitation of electric-conductive material on substrate of semiconductor material, forming of shape of first parallel band electrodes with step, determined by appropriate construction rules, while areas of substrate in form of stripes between first electrodes are left open, precipitation of barrier layer, covering first electrodes down to substrate, alloying of substrate in open areas, precipitation of electric-conductive material above alloyed areas of substrate with forming of second parallel band electrodes, removal of barrier layer, near which vertical channels are left, passing downwards to non-alloyed areas of substrate between first and second electrodes, alloying of substrate in open areas of lower portion of channels, filling channels with barrier material, removal of first electrodes, during which gaps between second electrodes are left and substrate areas are opened between them, alloying of open areas of substrate in gaps, from which first electrodes were removed, removal of electric-conductive material in said gaps for restoration of first electrodes and thus making an electrode layer, containing first and second parallel band electrodes of practically even width, which are adjacent to alloyed substrate and separated from each other only by thin layer of barrier material, while, dependent on alloying admixtures, used during alloying stages, first electrodes form source or discharge electrodes, and second electrodes - respectively discharge or source electrodes of transistor structures, precipitation of insulating barrier layer above electrodes and separating barrier layers. Precipitation of electric-conductive material above barrier layer and forming in said electric-conductive material of shape of parallel band valve electrodes, directed transversely to source and discharge electrodes, thus receiving structures matrix for field transistors with very short channel length and arbitrarily large width of channel, determined by width of valve electrode.

EFFECT: ultra-short channel length of produced transistors.

11 cl, 17 dwg

FIELD: electronic engineering; high-power microwave transistors and small-scale integrated circuits built around them.

SUBSTANCE: proposed method for producing high-power microwave transistors includes formation of transistor-layout semiconductor wafer on face side, evaporation of metals, application and etching of insulators, electrolytic deposition of gold, formation of grooves on wafer face side beyond transistor layout for specifying transistor chip dimensions, thinning of semiconductor wafer, formation of grooves on wafer underside just under those on face side, formation of through holes for grounding transistor leads, formation of integrated heat sinks for transistor chips around integrated heat sink followed by dividing semiconductor wafer into transistor chips by chemical etching using integrated heat sinks of transistor chips as mask.

EFFECT: enhanced power output due to reduced thermal resistance, enhanced yield, and facilitated manufacture.

2 cl, 1 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: manufacturing method of microwave transistor with control electrode of T-shaped configuration of submicron length involves formation on the front side of semi-insulating semi-conductor plate with active layer of the specified structure of a pair of electrodes of transistor, which form ohmic contacts by means of lithographic, etching method and method of sputtering of metal or system of metals, formation of transistor channel by means of electronic lithography and etching, application of masking dielectric layer, formation in masking dielectric layer of submicron slot by means of electronic lithography and etching; at that, submicron slot is formed with variable cross section decreasing as to height from wide upper part adjacent to the head of the above control electrode to narrow lower part adjacent to transistor channel, formation of topology of the above control electrode by means of electronic lithography method, formation of the above control electrode in submicron slot by means of sputtering of metal or system of metals; at that, configuration of its base repeats configuration of submicron slot. During formation of submicron slot with variable cross section in masking dielectric layer, which decreases throughout its height, by means of electronic lithography and etching, the latter of masking dielectric layer is performed in one common production process in high-frequency plasma of hexafluoride of sulphur, oxygen and helium and discharge power of 8-10 W.

EFFECT: increasing output power and amplification factor, increasing reproducibility of the above output parametres and therefore yield ratio, simplifying and decreasing labour input for manufacturing process.

2 cl, 1 dwg, 1 tbl, 5 ex

FIELD: electricity.

SUBSTANCE: field transistor manufacturing method includes creation of source and drain contacts, active area identification, application of a dielectric film onto the contact layer surface, formation of a submicron chink in the dielectric film for the needs of subsequent operations of contact layer etching and application of gate metal through the resistance mask; immediately after the dielectric film application one performs lithography for opening windows in the dielectric at least one edge whereof coincides with the Schottky gates location in the transistor being manufactured; after the window opening a second dielectric layer is applied onto the whole of the surface with the resistance removed; then, by way of repeated lithography, windows in the resistance are created, surrounding the chinks formed between the two dielectrics; selective etching of the contact layer is performed with metal films sprayed on to form the gates.

EFFECT: simplification of formation of under-gate chinks sized below 100 nm in the dielectric.

6 dwg

FIELD: electricity.

SUBSTANCE: method for UHF high-power transistors manufacturing includes formation of transistor topology semiconductor substratum on the face side by electronic lithography and photolithography methods, metals spraying on, dielectrics application and etching, cathodic electrodeposition of gold, formation of preset size grooves on the face side outside the transistor topology, substrate thinning, formation of grounding through holes for the transistors source electrodes, formation of a common integrated heat sink, formation of a integrated heat sink for each transistor crystal, semiconductor substrate division into transistor crystals; one uses a semiconductor substrate with the preset structure of active layers having two stop layers with the preset distance between them, the stop layers ensuring minimum thermal resistance; the semiconductor substrate reverse side thinning is performed down to the stop-layer located close to such side; grounding through holes are formed immediately on the source electrodes with the common integrated heat sink thickness is set by the type of the transistor crystal subsequent mounting.

EFFECT: enhanced output capacity through reduction of thermal resistance, parasitic of the electric resistance in series and source electrodes grounding inductance; increased yield ratio, repeatability and functionalities extension.

4 cl, 1 dwg, 1 tbl

FIELD: electrical engineering.

SUBSTANCE: method for manufacture of a powerful UHF transistor includes formation of the topology of at least one transistor crystal on the semiconductor substrate face side, formation of the transistor electrodes, formation of at least one protective dielectric layer along the whole of the transistor crystal topology by way of plasma chemical application, the layer total length being 0.15-0.25 mcm, formation of the transistor crystal size by way of lithography and chemical etching processes. Prior to formation of the transistor crystal size, within the choke electrode area one performs local plasma chemical etching of the protective dielectric layer to a depth equal to the layer thickness; immediately after that one performs formation of protectively passivating dielectric layers of silicon nitride and diozide with thickness equal to 0.045-0.050 mm; plasma chemical application of the latter layers and the protective dielectric layer is performed in the same technological modes with plasma power equal to 300-350 W, during 30-35 sec and at a temperature of 150-250°C; during formation of the transistor crystal size ne performs chemical etching of the protectively passivating dielectric layers and the protective dielectric layer within the same technological cycle.

EFFECT: increased power output and augmentation ratio or powerful transistors with their long-term stability preservation.

4 cl, 1 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: semiconductor device comprises a thinned substrate of single-crystal silicon of p-type conductivity, oriented according to the plane (111), with a buffer layer from AlN on it, above which there is a heat conducting substrate in the form of a deposited layer of polycrystalline diamond with thickness equal to at least 0.1 mm, on the other side of the substrate there is an epitaxial structure of the semiconducting device on the basis of wide-zone III-nitrides, a source from AlGaN, a gate, a drain from AlGaN, ohmic contacts to the source and drain, a solder in the form of a layer including AuSn, a copper pedestal and a flange. At the same time between the source, gate and drain there is a layer of an insulating polycrystalline diamond.

EFFECT: higher reliability of a semiconducting device and increased service life, makes it possible to simplify manufacturing of a device with high value of heat release from an active part.

3 cl, 7 dwg

FIELD: physics.

SUBSTANCE: invention relates to semiconductor technology. Proposed method comprises removal of photoresist from at least one surface of conducting layer with the help of the mix of chemical including first material of self-optimising monolayer and chemical to remove said photoresist. Thus self-optimising monolayer is deposited on at least one surface of said conducting ply. Semiconductor material is deposited on self-optimising monolayer applied on conducting layer without ozone cleaning of conducting layer.

EFFECT: simplified method.

15 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: method for manufacture of powerful SHF transistor includes application of a solder layer to the flange, shaping of pedestal, application of a sublayer fixing the transistor crystal to the pedestal, formation of p-type conductivity oriented at the plane (111) at the base substrate of single-crystalline silicon and auxiliary epitaxial layers, application of the basic layer and buffer layer for growing of epitaxial structure of a semiconductor device based on wide-gap III-nitrides, application of heat conductive layer of CVD polycrystalline diamond to the basic layer, removal of the basic substrate with auxiliary epitaxial layers up to the basic layer, growing of heteroepitaxial structure based on wide-gap III-nitrides on the basic layer and formation of the source, gate and drain. The heat conductive layer of CVD polycrystalline diamond is used as a pedestal; nickel is implanted to its surficial region and annealed. Before formation of the source, gate and drain an additional layer of insulating polycrystalline diamond and additional layers of hafnium dioxide and aluminium oxide are deposited on top of the transistor crystal; the total thickness of the above layers is 1.0-4.0 nm.

EFFECT: invention allows increased heat removal from the active part of SHF-transistor and minimisation of gate current losses.

6 cl, 4 dwg

FIELD: electronic equipment.

SUBSTANCE: invention is intended to create discrete devices and microwave integrated circuits with the help of field-effect transistors. Method of making field-effect transistor, including creation of drain and source contacts on the contact layer of semiconductor structure and extraction of active region, metal or metal and dielectric mask is applied directly on the surface of contact layer, formation of submicron slot in the mask for further etching operations of contact layer etching and application of T-shaped gate metal through resist mask, after application of the first metal mask lithography for opening windows is carried out when one of the edges coincides with location of Schottky gates in manufactured transistor, and after opening windows the second metal or dielectric mask is applied on the whole surface, remove resist and by lithography create window in resist surrounding slits formed between two metals or between metal and dielectric, perform selective etching of contact layer, after which spray metal films to form T-shaped gates. As a result, edges of T-shaped gate heads on both sides resting on metal or metal and dielectric masks. Then, via selective etching the mask is removed from under the "wings" of T-shaped gate and from the surface of transistor active area. After that, the surface of transistor active area, containing drain, source contacts and Schottky gates, is coated with a passivating layer of dielectric so that under "wings" of T-shaped gate cavities are formed filled with vacuum or gas medium.

EFFECT: technical result is production of gated with length less than 100 nm, as well as reduced thickness of the metal mask and elimination of intermediate layer of dielectric placed between the active region surface and mask.

1 cl, 1 dwg

Up!