A method of manufacturing samosobrannoy built-in copper metallization of integrated circuits

 

Usage: the technology for multilevel wiring of integrated circuits. The essence of the invention: method of manufacturing samosobrannoy built-in copper metallization of integrated circuits on a substrate applied dielectric film and formed in the dielectric film grooves of different shapes, put a conductive barrier film composed of multiple conductive layers, put planarize layer from the liquid phase, release planarize layer so that it remains only in the grooves, release the top layer of the barrier film in the open from planarizing layer areas are removed planarize layer of the grooves selectively precipitated copper on the surface of the upper layer of the barrier film to fill the copper volume inside the grooves, selectively precipitated on the surface of the grown film of copper protective conductive layer, selectively removing the barrier film in the open from layers of copper areas, put the second dielectric film and repeat the above steps to create the next level of connecting wires. The technical result of the invention is to reduce the range of operations, reduction of defects obtained structed technology for producing multi-level wiring of integrated circuits. This method can be used to obtain multi-level copper metallization.

At the present time to form conductors and contact vias in multi-tiered systems of interconnections of the integrated circuits are widely used methods of filling the grooves and contact Windows in the dielectric layers of aluminium and copper.

The disadvantages of aluminum metallization are lower than the copper conductors, the conductivity and the emergence of technological difficulties filling in narrow grooves.

Copper conductors have a number of advantages over aluminium conductors: a lower electrical resistance, a significant increase in resistance to electromigration failures that can improve the reliability of the chip, the simpler technology of forming conductors, more reliable technology fill in narrow grooves of a width of less than 1 micron.

Currently, there are various methods of obtaining copper wiring. In U.S. patent US 5747360A from 05.05.98 shows a method of forming a metal layer on the semiconductor wafer. The essential features of this method are applying on a substrate a dielectric film, forming contact Windows in the dielectric play to fill the copper volume inside the contact window, the formation of copper conductors on a surface of the dielectric layer. The disadvantage of this method is that this method inside the dielectric layer is formed only in the contact window is filled with copper, and is not formed inside the dielectric layer, the conductive paths.

Closest to the proposed invention is a method of creating a copper interconnect microwires on semiconductor substrates, shown in U.S. patent US 5723387A from 03.03.98. The essential features of this method are: applying to the substrate a dielectric film, forming grooves in the dielectric film, application of a conductive barrier film, drawing on its surface film of copper to fill the copper volume inside the grooves, forming inside the dielectric layer copper contact vias and conductive tracks. The disadvantage of this method is that this method requires the removal of deposited on the surface of the layer of copper. In this patent to remove a layer of copper from the surface using a process of chemical mechanical polishing. This is a costly and Defektoskopiya operation.

The task to be solved by the invention, is to achieve a t the I metal wiring, in the reduction of defects in structures with copper metallization, the reduction in consumption of copper in the formation of the copper conductors.

The problem is solved in the method of manufacturing embedded in grooves copper metallization, comprising: applying to the substrate a dielectric film; forming grooves of different shapes in the dielectric film; applying a conductive barrier film composed of multiple conductive layers (e.g., TA/N1, TA/TaN/Ni, TA/TaN/cu, Ti/TiSiN/Ni, Ti/TiSiN/C), selected so that during the process of deposition of the copper layer is formed only on the surface of the upper layer barrier film, and on the exposed areas of the underlying layer barrier film of copper is not deposited, coating the surface of the structure obtained planarizing layer from the liquid phase, the drain planarizing layer so that it remains only in the grooves to a level located below the surface of the substrate, the etching of the upper layer of the barrier film in the open from planarizing layer regions selective to the underlying layer of the barrier film and to planarize layer, removing planarizing layer of the grooves selectively to the upper and lower layers of the barrier film, with full filling copper volume inside the grooves, selective removal of the lower part of the barrier film in the open from layers of copper areas selectively to the dielectric film and the layer of copper, the deposition of the second dielectric film, the repetition of the above operations to create the next level of connecting wires.

Thus, the important features of the present invention is that the barrier film is formed from multiple conductive layers, selected so that during the process of deposition of copper copper is deposited only on the top layer of the barrier film and on the exposed areas of the underlying layer of copper is not deposited, then applied to the surface of the structure obtained planarize layer from the liquid phase, release planarize layer so that it remains only in the grooves to a level located below the surface of the substrate, release the top layer of the barrier film in the open from planarizing layer regions selective to the underlying layer of the barrier film and to planarize layer, remove planarize layer of the grooves selectively to the upper and lower layers of the barrier film, selectively precipitated by electrochemical or chemical means, a layer of copper on the top layer benki open from layers of copper areas selectively to the dielectric film and the layer of copper.

The use of the combination of these characteristics of the invention allows deposition on the surface structure of a copper layer, completely filling the space within the grooves and does not extend above the surface of the substrate, which eliminates the delete operation settled on the surface of the layer structure of copper, thereby decreasing defects of the obtained structures and decreases the consumption of copper in the formation of the copper conductors.

The copper layer does not go above the level of the surface of the substrate, due to the fact that when the etching planarizing layer remains only in the grooves to a level located below the surface of the substrate. As a result, after grazing the top layer of the barrier film from polling stations from planarizing layer, the upper layer barrier film remaining in the grooves located below the surface of the substrate at a depth that allows you to besiege him a copper layer, completely filling the space within the grooves and does not extend above the surface of the substrate.

After deposition of a copper layer on its surface can be selectively deposited by electrochemical or chemical method, the protective conductive film, as to the route of obtaining samosobrannoy built-in copper metallization of integrated circuits (Fig. 1-9), where the numbers denote the following structures: 1 - base; 2 - dielectric layer; 3 - the lower part of the barrier film; 4 - upper layer barrier film; 5 - planarize layer; 6 - copper layer.

In Fig.1-9 shows the stages of formation samosobrannoy built-in copper metallization of integrated circuits, as follows.

Fig.1. On a substrate applied dielectric layer.

Fig.2. In the dielectric layer by the methods of photolithography to form the structure of the grooves.

Fig.3. On the surface of the obtained structures sprayed a thin bottom layer of the barrier film, and then sprayed a thin top layer of the barrier film.

Fig.4. On the surface of the obtained structures put planarize layer.

Fig.5. When carrying out plasma-chemical etching planarize the release layer from the surface, leaving it inside the grooves.

Fig.6. The top layer of the barrier film is removed from the surface, open from planarizing layer.

Fig.7. Planarize layer is removed from the grooves.

Fig.8. On the surface of the upper layer barrier film inside the grooves, electrochemical or chemical method precipitated the copper layer.

Fig.9. The bottom layer of the barrier film is removed from the surface of the dielectric layer.

On the example of manufacturing samosobrannoy built-in copper metallization of integrated circuits it is possible to offer the following technology. On a substrate applied with a method of plasma-chemical deposition of a dielectric layer of SiO2thickness of 1.0 μm at a temperature of deposition 215-225C. In the dielectric layer of SiO2methods of projection photolithography to form the structure of grooves of different shapes projection sizes of 0.5-1.0 μm. On the surface of the obtained structures by magnetron sputtering sprayed layer of TA with a thickness of 0.05-0.1 μm as the lower part of the barrier film, and then by magnetron sputtering put a layer of Ni with a thickness of 0.05-0.1 μm as an upper layer barrier film. The sputtering is carried out at a temperature of 200-250C. On the surface of the obtained structures put planarize the photoresist layer. When carrying out plasma-chemical etching planarize the release layer from the surface, leaving it inside the grooves. The Ni layer is removed from the surface, open from planarizing layer by chemical etching. Planarize layer is removed from the grooves by the method of plasma-chemical etching. On the surface of the Nickel layer inside the grooves, the electrochemical method of the precipitated copper layer to fill the grooves. The deposition is carried out from a solution containing cernobil the displacement of the dielectric layer by the method of chemical etching. Next, repeat the above steps to create the next layer of the connecting conductors.

Claims

1. A method of manufacturing samosobrannoy built-in copper metallization of integrated circuits, comprising applying to the substrate a dielectric film, forming grooves of different shapes in the dielectric film, application of a conductive barrier film, the deposition on its surface film of copper to fill the copper volume inside the grooves, the selective removal of the exposed areas of the barrier film, application of a second dielectric film, wherein the barrier film is formed from multiple conductive layers, selected so that during the process of deposition of the copper layer is formed only on the surface of the upper layer of the barrier film and on the exposed areas of the underlying layer barrier film of copper is not deposited, then applied to the surface of the structure obtained planarize layer from the liquid phase, release planarize layer so that it remains only in the grooves to a level located below the surface of the substrate, release the top layer of the barrier film in the open about Aut planarize layer of the grooves selectively to the upper and lower layers of the barrier film, selectively precipitated by electrochemical or chemical means, a layer of copper on the top layer of the barrier film within the grooves until they are full, selectively release the lower part of the barrier film in the open from layers of copper areas selectively to the dielectric film and the layer of copper is applied, the second dielectric film.

2. The method according to p. 1, characterized in that as the layers of the multilayer barrier film can be used TA/Ni, or TA/TaN/Ni, or TA/TaN/Cu, or Ti/TiSiN/Ni or Ti/TiSiN/Cu.

3. The method according to p. 1, characterized in that after deposition of electrochemical or chemical means a copper layer on the surface layer of copper selective electrochemical or chemical means cause the protective conductive film of Nickel, or gold, or platinum.

 

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