The transmitter manchester multiplex communication line

 

The invention relates to automatic control systems for organizing links in the trunk interfaces for signaling code Manchester-2". The technical result is to reduce the power consumption of the transmitter, reducing the heating temperature of the output transistors, increasing the reliability, resilience spacestation, increasing the maximum permissible ambient temperature, increasing the reliability of the transmitted information, the elimination of the need for selection of external capacitors or resistors with the aim of balancing the output signal, eliminating the need for matching the output transistors for gain. The transmitter contains two identical channels, each of which is connected to the first and second power sources and contains two logical inverter, eight resistors, six capacitors, circuit matches, five diodes, four transistor, and the transmitter contains an element of bias, made in the form of a chain of series-connected diodes. 1 Il.

The invention relates to automatic control systems (ACS) and can be used for the linking device is hash with centralized management, used in electronic modules, in computing for the PC to communicate with other blocks, for transmitting signals code Manchester-2”, the Transmitter multiplex communication line is designed primarily for use in onboard equipment, which is part of electronic terrestrial, marine and aerospace.

Known transmitters multiplex communication line, described in the book “the Organization of sequential multiplex channels of automatic control systems”, published under the editorship of candidate of technical Sciences S. I. Horsetail. L., engineering, 1989, page 132, Fig. 4.4.

This device contains input logic performing the role of a pre-amplifier, a differential amplifier of the transmitter data output transistors, the circuit of the temperature control of the crystal.

A disadvantage of the known transmitter is a lack of reliability due to overheating of the output transistors in the transmission mode, which leads to the necessity to stop from time to time of the transmitter to reduce the temperature of the output transistors. In addition, the transmitter has a large power consumption in standby mode. All this leads to the necessity of introduction of the scheme to the present invention is to reduce power consumption of the transmitter in standby mode and in transmission mode, reducing the heating temperature of the output transistors and, consequently, increased reliability, increased resistance to speciespecten, increasing the maximum permissible ambient temperature, ensuring durations rise and fall of output pulses in line with the requirements for limiting the maximum and minimum of these parameters, improving the accuracy of the duration of the transmitted pulses, the decrease in the amplitude of the inductive discharge that occurs at the end of the transmitted word, the elimination of the need for selection of external capacitors or resistors with the aim of balancing the output signal, eliminating the need for matching the output transistors for gain.

The technical problem is solved due to the fact that each channel of the multiplex transmitter (Manchester) lines containing two identical channels, each of which is connected to the first and second power sources, each of which is arranged on a first logical inverter and the circuit matches the input of the first logical inverter connected to the input of a channel output transistor terminal of the cascade, between the collector and base of which are connected capacitor integrator Milled protection from saturation, the input of the first channel connected to the first input of the transmitter, and outputs the first and second channels respectively with the first and second outputs of the transmitter, input a second logical inverter, the first, second and third transistors, the first, second, third and fourth capacitors, the first, second, third, fourth and fifth diodes, eight resistors, and the output of the first logical inverter connected to the first input schema matches through the integrating link composed of the first resistor and the first capacitor, the second input of the logic inverter connected to the input of the first logical inverter, the output of the second logic inverter connected to the second input of the circuit matches the output of the latter through the second capacitor is connected to the base of the first transistor is connected to the anode of the first diode and the cathode, a second resistor connected to the output of the circuit matches the cathode of the first diode connected to the cathode of the second diode and the anode of the latter is connected to the collector of the first transistor and the bases of the second and third transistors and through a third resistor connected to the collector of the third transistor and the second power source, the emitters of the second and third transistors through a third condensate is about United of the fourth capacitor and the sixth resistor connected to the base of the output transistor terminal of the cascade, the second terminal of the fifth resistor through the seventh resistor is connected to the base of the output transistor terminal of the cascade, the protection diode from saturation anode connected between the fifth and the seventh resistor, and a cathode coupled to the output channel, the emitter of the output transistor terminal of the cascade is connected with the second power source, and a cathode of the fourth diode, parallel to the latter is connected to the eighth resistor, the base of the output transistor terminal cascade through the fifth diode is connected to the input offset of the channel between the collector of the output transistor terminal of the cascade and the anode of the fourth diode connected to the fifth capacitor between the second power bus and the input offset of channel 1, connected to the input offset of channel 2, included the newly introduced element offset is made in the form of a chain of series-connected diodes.

The drawing shows an electric diagram of the multiplex transmitter (Manchester) lines. The transmitter consists of two identical channels: channel 1 and channel 2. Therefore elaborated scheme only channel 1. The first input of the transmitter is connected to the input of logic inverter 1 and the input of logic inverter 3. The yield of the latter is connected with the second input and therefore the capacitor 5. Another implication of the latter is connected with a common bus. The output of the circuit matches 2 through the condenser 6 is connected to the base of transistor 7. Between the base and emitter of the transistor 7 is connected to the resistor 8. The anode of the diode 9 is connected to the base of transistor 7. The cathode of the diode 9 is connected to the cathode of the diode 10 and through a resistor 11 is connected to the output of the circuit matches 2. The collector of transistor 7 is connected to the anode of diode 10, with the bases of transistors 12 and 13 and through resistor 14 to the second power source. The emitter of transistor 7 is connected to the first power source and to the collector of transistor 12. The emitter of transistor 12 is connected to the emitter of transistor 13 and is connected to the capacitor 15. Another implication of the latter is connected with the cathode of the diode 16 and the first output resistor 17. The second output of the latter is connected through a resistor 18 to the base of transistor 19. Between the anode of diode 16 and the base of the transistor 19 is in parallel connected capacitor 20 and resistor 21. Between the base and collector of transistor 19 is connected to the capacitor of the Miller integrator 22. The capacitor 23 is connected to the collector of the transistor 19. The second lead of the capacitor 23 through a resistor 24 is connected to the emitter of the transistor 19. In parallel with the resistor 24 is connected diode 25. The cathode of diode 26 is connected to the collector transistoren between the second power source and the first input of the offset of the first channel, which through the diode 31 is connected to the base of transistor 19. The first input of the offset channel 1 is connected to the input offset of channel 2.

Logical circuits 1, 2 and 3 by a circuit connected between the common bus and the first power source. The external load of the transmitter output is a linear transformer. Extreme conclusions mentioned primary winding of the transformer is connected to the output 1 and output 2 of the transmitter. The midpoint of the primary winding of the transformer connected to a common bus. The secondary winding through a protective resistor loaded on line.

Consider the state of the transmitter in the absence of input signals applied voltages. The transistors 7, 12, 13 and 19 are closed and do not consume energy from power sources. If the logical circuits 1, 2 and 3 of the selected type CMOS, they are also in standby mode have zero consumption. In this case, the transmitter is in standby mode has zero energy consumption.

If the logical circuits 1, 2 and 3 of the selected type TTL, the power consumption of the transmitter in standby mode is determined by the consumption of these TTL chips.

For comparison, we note that in standby mode known to the transmitter consumes significantly Bo the m state.

Consider the operation of the device in the transmission mode information. In this case, input 1 and input 2 transmitter alternately receives a negative pulse. When input a negative pulse on input 1 on the logical outputs of the inverters 1 and 3 appear positive impulses, which in turn are received at the inputs of circuit 2 matches. The output of the last negative pulse whose duration is slightly less (10-15 NS) than the input pulse duration, due to the delay introduced with the integrator performed on the resistor 4 and the capacitor 5. This delay allows to exclude the situation when the output transistor of channel 1 and channel 2 would be open at the same time, because in this case there is a mode momentary short circuit, which leads to heating of the output transistors.

The appearance of a negative pulse at the output of the chip matches 2 leads to the opening of the transistors 7, 12 and 19 for the duration of this pulse. Mentioned transistors work in switching mode, and in the open state is on the brink of field saturation collector current in the linear region, in the active mode. This allows to meet the requirements of stannie relative to their nominal values (500 NS, 1000 NS 2000 NS) when measured between the points of intersection of the pulses of the zero level voltage should not exceed ±25 NS”.

Thanks to the condenser 15 in the opening moments of the transistor 19 on its base relative to the emitter is formed of positive pulses. In between the opening pulses through capacitor 15 are formed negative closing pulses with amplitude equal to the sum of the voltage of the direct drop on the diodes 27, 28, 29, 30 and 31. During the passage opening of the pulse current in the base of the transistor 7 is supplied through the resistor 11. The diodes 9 and 10 at a given moment of time are open and protect the transistor 7 from the saturation mode. The fronts of the pulses from the circuit 2 to the transistor 7 is passed through the condenser 6.

Opening the current in the base of the transistor 19 is supplied through the circuit: the first power - transistor 7 - transistor 12 and the capacitor 15 resistors 17, 18 to the base of transistor 19. The diode 16 is in the closed position. The diode 26 is open and protects the transistor 19 from the saturation mode. The elements 23, 24 and 25 allow the fronts of the pulses in the line within specified limits. According to the current standards, the length of the front and duration of the decline of the pulses in the line is limited by the minimum and maximum of the duration of the front and duration of the decline depends on the variation of the gain of the transistors in the manufacture, during aging, when the temperature of the environment, from the accumulated dose of radiation exposure. In the proposed device it does not, and this is its principal advantage.

Reducing power consumption in the proposed transmitter is provided due to the fact that all transistors in the standby mode are closed and do not consume energy from power sources. In transmit mode due to the presence of elements 1, 2, 4 and 5 eliminates the mode intermittent short circuit in the output transistors, thereby reducing power consumption in transmit mode.

Reducing the heating temperature of the output transistors and, hence, higher reliability is ensured by the fact that these transistors are turned off and included quite fast and smooth edges in line are formed due to the presence of elements 23, 24 and 25. At the same time, in the known devices smooth edges in the line formed by the smooth switching of the output transistors, which leads to additional warming up.

The resilience spacestation, despite the deterioration of the static and dynamic properties of the output transistor, in this uslovnyh opening pulses and negative closing pulse.

By reducing the temperature of the output transistors is provided enabling conditions increase the maximum ambient temperature.

The decrease in the amplitude of the inductive discharge voltage at the end of the last transmitted word is provided by the damping action of the elements 23, 24 and 25, which improves the reliability of the transmitted information.

No need for the selection of external capacitors or resistors with the aim of balancing the output signal due to the identity work of the two output transistors, primarily due to the excitation of different wave voltage for the output transistors, as well as due to the action of the elements 23, 24 and 25.

The need in the selection of the output transistors in the gain falls off in the first place, because the duration of the rise and fall wave voltage in the line is determined by the presence of elements 23, 24 and 25 and does not depend on the gain of the above-mentioned transistors.

The proposed analog transmitter to pair with multiplex channel according to GOST 26765.52-87 (MIL-STD-V) is implemented as an integrated circuit. In the same case except the transmitter is Tizite the temperature of the output transistor, to increase reliability, improve resistance to spacestation, to increase the maximum allowable ambient temperature, to increase the reliability of the transmitted information, to withdraw from the selection of the external (to the chip transmitter) capacitors and resistors, to withdraw from the selection of the output transistors for gain.

Of all domestic circuits of this type offer the chip now has the highest settings and highest reliability of information transmission.

Claims

The transmitter Manchester multiplex communication line that contains two identical channels, each of which is connected to the first and second power sources, each of the channels made in the first logical inverter and the circuit matches the input of the first logical inverter connected to the input of a channel output transistor terminal of the cascade, between the collector and base of which is connected a capacitor in the form of a Miller integrator, between the base and a second power supply connected resistor thermal leakage, and with a collector connected to the protection diode from saturation, the input of the first channel is connected to the first input of the respectively with the first and second outputs of the transmitter, characterized in that each channel input a second logical inverter, the first, second and third transistors, the first, second, third and fourth capacitors, the first, second, third, fourth and fifth diodes, eight resistors, and the output of the first logical inverter connected to the first input schema matching across the integrating link composed of the first resistor and the first capacitor, the second input of the logic inverter connected to the input of the first logical inverter, the output of the second logic inverter connected to the second input of the circuit matches the output of the latter through the second capacitor is connected to the base of the first transistor, connected to the anode of the first diode and the cathode, a second resistor connected to the output of the circuit matches between the base and emitter of the first transistor is connected to the fourth resistor, the emitter of the first transistor connected to the first power source and to the collector of the second transistor, the cathode of the first diode connected to the cathode of the second diode and the anode of the latter is connected to the collector of the first transistor and the bases of the second and third transistors and through a third resistor connected to the collector of the third transistor and the second power source, the ora and to the cathode of the third diode, and the anode of the latter through parallel connected to the fourth capacitor and the sixth resistor connected to the base of the output transistor terminal of the cascade, the second terminal of the fifth resistor through the seventh resistor is connected to the base of the output transistor terminal of the cascade, the protection diode from saturation anode connected to the connection point between the fifth and the seventh resistor, and a cathode coupled to the output channel, the emitter of the output transistor terminal of the cascade is connected with the second power source and the cathode of the fourth diode, parallel to the latter is connected to the eighth resistor, the base of the output transistor terminal cascade through the fifth diode is connected to the input offset of the channel, between the collector of the output transistor terminal of the cascade and the anode of the fourth diode connected to the fifth capacitor between the second power bus and the input offset of channel 1 is connected to the input offset of channel 2, included the newly introduced element offset is made in the form of a chain of series-connected diodes.

 

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