Planar power mos transistor with a blocking capacity of drain schottky barrier
Usage: in the semiconductor power electronics, when designing semiconductor devices unipolar transistors with field effect created by the insulated gate. The inventive planar power MOSFET in stock diffusion region and a region with a Schottky barrier with an area considerably smaller, at least 10-fold, relative to the square of the diffusion of stock area, so that a relatively large output capacity of the drain is blocked low capacitance Schottky barrier. The technical result of the invention is to reduce the output capacitance of the planar power MOS transistor. 4 Il.The invention relates to a semiconductor power electronics, semiconductor devices unipolar transistors with field effect created by the insulated gate.In some schemes, for example, multiplex, working on a long line, power switches connected in parallel and respectively parallel to the included output capacitance of the MOS transistors used as the key. The value of the output capacitance of the MOSFETs is determined mainly by the capacity of the pn junction of the drain otomicroscopy devices - planar MOSFET with a high breakdown voltage due to the introduction of additional low-alloy regions at the edges of the flow, as described in the patent /1/. These areas increase the area of the pn junction of the drain-substrate and respectively their area increases the capacitance of the drain of the transistor. For operation at high frequencies it is necessary to reduce the capacitance of the transistors.Reduction of the capacity of the MOS transistors is usually carried out by introducing different ways of dielectric layers in the structure of the MOS transistor. Thus, in the patent /2/ reduction of the capacity of the drain and source of the MOSFET was proposed to be implemented by introducing an insulating layer under a region of the source and drain, which separates the region of the flow from the substrate or as in the patent /3/ introducing dielectric substrate under the entire unit. In the patent /4/ reduction of the gate capacitance of the MOSFETs was suggested due to the different thickness of the dielectric under the gate over the active channel and over the sink. In the patent /5/ serves to reduce capacity by introducing additional areas of the drain and the source.Proposals for the introduction of Schottky diodes in the MOSFET is known from a number of sources /6-12/, but these proposals are not intended to reduce e the precise areas. In the patent /7/ are prompted to enter the Schottky diodes in power DMAP transistors option IGBT to limit the injection of contact to the substrate. There is information in the /8/ about reducing the off time power DMAP transistors option IGBT bulky design with the introduction of the Schottky diode in the drain (SINFET) due to the limitations of injection into the flow. In the works /9/, /10/ more detail the functioning of SINFET transistors. The /11/ is considered the mechanism of the MOS transistors with the introduction of the Schottky diode to the source of the transistor to increase the injection of hot electrons. In the patent /12/ serves to limit injection into power drop-transistor of the contact to the substrate during operation of a bipolar transistor with injection-driven insulated gate (IGBT), to produce fused contact to the substrate - drain or on top of the substrate or on the entire bottom side of the substrate.The closest analogue adopted us for the prototype is a MOS transistor on the insulating substrate /3/. As the dielectric used single crystals of sapphire or oxide layers on silicon single crystals. This device increases the cost of production of power MOSFETs and high-voltage integrated circuits for MOS tallageda on the contact to the drain to form a region, ensuring the formation of Schottky barrier with an area significantly smaller (<10 times) the area of the pn junction of the drain-substrate. Thus the capacity of the Schottky barrier is included in series with the capacitance of the drain-substrate, which reduces the output capacitance of the drain of the MOSFET.The essence of the invention is to create a region with a Schottky barrier contact to the stock diffusion area power planar MOSFET with an area significantly smaller (at least 10-fold) relative to the square of the diffusion of stock area, including the area of the pinch resistor part of the flow, so that a relatively large output capacity of the drain is blocked low capacitance Schottky barrier.In Fig.1 shows the structure of the planar power MOSFET area, creating a Schottky barrier contact to the drain sequence of manufacture of the device shown in Fig.2, the topology of the power MOSFET is given in Fig.3, the equivalent circuit of tanks planar power MOS transistor with a Schottky barrier between the drain contact to the drain shown in Fig.4.In Fig.1 shows a cross section of the planar power MOSFET with a Schottky barrier between the drain contact to the drain of the device, where the power playstationeu (3); a control electrode (4) is isolated from the surface (2) thin gate dielectric (5) and a thick dielectric (6); a first conductive electrode of the source (7) is located on the surface (2) and is in contact with stokovoj diffusion region (10) located in the substrate (1); a first conductive electrode of the source (7) generates stokovoj diffusion region (10) ohmic contact; a second conductive drain electrode (8) is also located on the surface (2) on stock diffusion region (12) located in the substrate; the second conductive electrode (8) forms with runoff diffusion region (12) a rectifying contact is a Schottky barrier; about stokovoj diffusion region (10) in the substrate (1) formed area (9) with high concentration impurities to prevent the clamping space charges from the pn junctions of the source and drain; between regions (9) and (12) is formed in the substrate region of the pinch resistor (11) with the same stock diffusion region (12) type of conductivity and due to the low level doping region of the pinch resistor (11) increases the breakdown voltage of the drain when closed, the transistor and provides the conductivity of the transistor is open.In Fig.2 presents a phased sequence operas, the substrate has p-type conductivity.a) Forming region of the pinch resistor (11) n-typeb) forming a region of thick dielectric (6) over the area of the pinch resistor (11). As the dielectric can be silicon oxide, which may be formed by LOCOS method. Also formed area of conservation (9) p-type.C) Formation of ion doping and diffusion of stock diffusion region (12).g) Forming region of the thin gate dielectric (5) and the control electrode (4)d) Forming signalisierung stokovoj diffusion region (10), the ohmic contact of the first conductive electrode (7) to stokovoj diffusion region (10) and contact the second conductive electrode (8) to the stock diffusion region (12) in the form of a Schottky barrier. The formation of the contact second conductive electrode (8) to the stock diffusion region (12) in the form of a Schottky barrier is provided either by using additional ponteginori stock diffusion region (12) the admixture of p-type to compensate for the impurity in a region on the surface near the contact due to the ion introduction of impurities; or one of the doping of the drain - the latter is carried out with the same doping level, when nanes aluminum with silicon is formed a Schottky barrier; either by drawing on the contact window to the stock areas of the layer of another metal, for example tin.In Fig.3 shows the topology of planar power MOS transistor with a Schottky barrier between the drain contact to the drain of the device.Planar power MOS transistor with a working voltage of 100 V is an annular structure with a control electrode (4) octagonal shape of the polycrystalline silicon. The total area of the stock diffusion region (12) and the region of the pinch resistor (11) (these areas are located within the ring of the steering transition (4)) equal to 50 μm2when the area of the second conductive electrode (8) (Schottky barrier) to the stock diffusion region (12) equal to 4 μm2. The region of the pinch resistor is located inside the ring of the control electrode (4) under a thick dielectric (6).Outside ring of the control electrode (4) is located Itokawa diffusion region (10) and the first conductive electrode (7) (ohmic contact).In Fig.4 shows the equivalent circuit of tanks planar power MOS transistor with a Schottky barrier between the stock diffusion region (12) (runoff) and the second conductive electrode (8) (contact to the drain).The input cap) - C4-1and between the control electrode (4) and stokovoj diffusion region (10) - C4-10-7. Output capacity swich=C12-11-1*C8-12/ C12-11-1+C8-12formed from containers between stock diffusion region (12), the region of the pinch resistor (11) and the substrate (1) - C12-11-1and connected in series the capacitance of the Schottky diode C8-12between the second conductive electrode (8) to the stock diffusion region (12) and directly stock diffusion region (12). Internal capacitance of C4-11-12is formed between the control electrode (4), the region of the pinch resistor (11) and a drain diffusion region (12).Powerful planar power MOS transistors with a working voltage of 100 V to ensure operation at high currents is composed of a large number included in the separate parallel transistors shown in Fig.3. So for the working current 2 a combined 2048 cells. The capacity of the p-n junction of the drain-substrate With12-11-1such transistors has a value of 90 pF, and the capacitance of the Schottky diodes C8-12equal to 5 pF, so that the output capacity of the powerful planar power MOSFET with Schottky diodes in stock area at a working voltage of 100 V and an operating current of 2 a is the magnitude of 4.7 pF.To open the current. Typically, the Schottky diode is a voltage drop of about 0.3 C. This voltage drop increases the resistance of the open device at low operating currents. High current dynamic resistance of the diode is small and has no significant effect on the operation of the transistor. In the closed state of the MOS transistor, the voltage at the drain close to the voltage source, so through the Schottky diode current does not leak.Work MOSFET switching depends on the capacities indicated on Fig. 4. Therefore, the reduction of the output capacitance of the planar power MOSFET with a Schottky barrier can improve the performance of the device. The introduction of the Schottky barrier in the flow of the planar power MOSFET allowed in the scheme of the multiplexer 32-channel performance from 500 kHz to 4 MHz. The design of planar power MOSFET with a Schottky barrier in the flow, having the technology is one difference from the accepted manufacturing techniques, namely the formation region of the Schottky contact to the drain is much easier than the well-known design of planar power MOSFET on the dielectric substrate.Manufactured samples of the planar power MOSFET with a Schottky barrier in conta/p>2. The European patent EP 0077773.3. U.S. patent US 4665416 prototype.4. U.S. patent US 5179032.5. The Japan patent JP 2000260980 20000922.6. SB-IGFET: An Insulated-Gate Field-Effect Transistor Using Schottky Barrier Contact as Source and Drain / M. P. Lepselter and S. M. Sze // Proc. IEEE, 58, p.1088, 1968.7. Sakurai et al., Power MOSFETs having Shottky Barrier Drain Contact, Int'1 Symposium on Power Semiconductor Devices & Ics, Tokyo 1990, pp.126-130.8. Sin et al., The SINFET: A New High Conductance, High Switching Speed MOS-Gated Transistor, Electronic Letters, Nov, 1985, p.1124.9. Sin et al., Analysis and Caracterization of the n-Canal Hybrid Shottky Injection Field Effect Transistor, IEDM 86-9.4, pp.222-225.10. Sin et al., Analysis and Caracterization of the Hybrid Shottky Injection Field Effect Transistor, IEEE Trans. Electron Devices, 1989, v.36, No. 5, pp.993-1000.11. The increase in the speed of generation of hot holes in Schottky - source MOSFETs. Appl. Phys. Lett., 2000, v.76, No. 26, pp.3992-3994.12. U.S. patent US 5589408.
ClaimsPlanar power MOS transistor with a blocking capacity of drain Schottky barrier containing monocrystalline substrate, a control electrode insulated from the substrate by a dielectric, the first conductive source electrode in contact with stokovoj diffusion region located in the substrate, the second conductive electrode of the drain above the stock diffusion region located in the substrate region with a high impurity concentration of about Itokawa is on, characterized in that between the second conductive drain electrode and a drain diffusion region formed region with a Schottky barrier with an area significantly smaller (at least 10-fold) relative to the square of the diffusion of stock area, creating a Schottky barrier at the contact with the tank, blocking the flow capacity.
FIELD: nanoelectronics and microelectronics.
SUBSTANCE: proposed nanotransistor that can be used in microelectronic and microelectromechanical systems as fast-response amplifier for broadband digital mobile communication means and also for building microprocessors, nanoprocessors, and nanocomputers has semiconductor layer incorporating conducting channel, thin insulator layer disposed on semiconductor surface, gate made on thin insulator surface, drain, and source contacts; semiconductor layer is disposed on bottom insulator layer that covers semiconductor substrate functioning as bottom gate; conducting channel is nano-structured in the form of periodic grid of quantum wires; thin insulator layer encloses each quantum wire of conducting channel on three sides; gate is made in the form of nanometric-width metal strip and encloses each quantum wire of conducting channel on three sides; thin insulator has windows holding drain and source metal contacts connected to channel. Silicon can be used as semiconducting material and thermal silicon dioxide, as insulator.
EFFECT: enhanced degree of integration, reduced size, eliminated short-channel effects, enhanced transconductance, radiation resistance, and environmental friendliness of device manufacture.
4 cl, 2 dwg
FIELD: electronic equipment.
SUBSTANCE: in SHF LDMOS - transistor, which contains semi-conductor substrate with high-resistance and high-alloyed layers of the first type of conductance, elementary transistor cells in high-resistance layer of substrate with channel field of the first type of conductivity, high-alloyed source, high-alloyed and low-alloyed drain regions of the second type of conductivity, gate dielectric from thermal silica dioxide and gate electrode above channel region of transistor cells, thermal silica dioxide and interlayer dielectric above low-alloyed drain region of transistor cells, source and drain electrodes of transistor cells on the face side of substrate, field screening electrodes in the gap between drain and gate electrodes, which are connected to one of transistor cells source electrode ends outside the limits of gate electrodes, common electrode of transistor structure drain on back side of substrate, field screening electrodes of transistor cells are made of gate electrode material and are installed at the interface of thermal silica dioxide - interlayer dielectric, at that width of thermal silica dioxide above low-alloyed drain region makes (1.0-3.5) of gate dielectric width, and border of gate dielectric coupling with layer of thermal silica dioxide above low-alloyed drain region is installed under gate electrode.
EFFECT: increase of permissible limit values of electric parameters and operation modes of SHF LDMOS - transistors and provision of conditions for organisation of profitable industrial production of these items.
1 dwg, 2 tbl
SUBSTANCE: in field MIS transistor drain and source regions each contain two serially connected sections, the main and the additional ones, at that the main sections of drain and source regions have high concentration of alloying admixture, and additional sections that are installed between channel and main sections have low concentration of alloying admixture. Abovementioned additional sections stretch into abovementioned semiconductor wafer deeper than the abovementioned main sections and enclose these main sections inside themselves, with their overlap in semiconductor wafer, and on the surface of semiconductor wafer border of this additional section on the one side is at least superposed with projection of one of gate sides on semiconductor wafer, and from the other sides it is distant from border of protective area at the value that is not less than sum of values of width of space charge areas formed in semiconductor wafer by drain, source regions and protective area, at that projection of end areas of gate ends onto surface of semiconductor wafer is superposed with border of protective area, and all surface of semiconductor wafer is coated with dielectric, the thickness of which does not exceed gate thickness.
EFFECT: increase of resistance to external actions, percentage of proper produce, fast-action.
FIELD: information technology.
SUBSTANCE: flash memory element for electrically programmable read-only memory is meant for data storage when power is off. On a semiconductor base with a source and drain between the latter, there is a tunnelling layer, an auxiliary tunnelling layer, a memory layer, blocking layer and a switch. The auxiliary tunnelling and blocking layers are made from material with high dielectric permeability, from 5 to 2000, exceeding the dielectric permeability of the material of the tunnelling layer made from SiO2.
EFFECT: as a result there is reduction of voltage (4 V) and time (10-7 s) for recording/erasing information and increase in data storage time (up to 12 years).
7 cl, 1 dwg
FIELD: physics, radio.
SUBSTANCE: invention is to find application in microelectronics. Concept of the invention is as follows: the proposed field transistor is composed of a source electrode, a drain electrode, a gate insulator, a gate electrode and an effective layer; the effective layer contains an amorphous oxide with an electronic media concentration less than 1018/cm3 and the electronic mobility increasing proportional to the electronic media concentration. Of the source, drain and gate electrodes at least one is visual light translucent with the current flowing between the source and the drain electrodes never exceeding 10 mA unless there is a voltage applied to the gate electrode.
EFFECT: development of a transistor enabling improvement of at least one of the following properties: translucency, thin film transistor electrical properties, gate insulation film properties, leakage current prevention and adhesiveness between the effective layer and the substrate.
21 cl, 12 dwg
SUBSTANCE: invention relates to an amorphous oxide, used in the active layer of a field-effect transistor. The amorphous oxide, which contains at least one microcrystal and has concentration of electron carriers from 1012/cm3 to 1018/cm3, contains at least one element, chosen from a group consisting of In, Zn and Sn, and the boundary surface of the grains of the said microcrystal is coated with an amorphous structure.
EFFECT: obtaining an amorphous oxide which functions as a semiconductor for use in the active layer of a thin-film transistor.
6 cl, 8 dwg
FIELD: electrical engineering.
SUBSTANCE: proposed invention relates to field transistor with oxide semiconductor material including In and Zn. Atomic composition ratio expressed as In/(In+Zn) makes at least 35 atomic percent and not over 55 atomic percent. With Ga introduced into material, aforesaid atomic composition ratio expressed as Ga/(In+Zn+Ga) makes 30 atomic percents or smaller.
EFFECT: improved S-characteristic and drift mobility.
9 cl, 25 dwg
SUBSTANCE: in field transistor, comprising active layer and gate-insulating film, active layer comprises a layer of oxide, comprising In, Zn and Ga, amorphous area and crystalline area. At the same time crystalline area is separated from the first surface of interface, which is surface of interface between a layer of oxide and gate-insulating film, distance of 1/2 of active layer thickness or less, and it within the limits of 300 nm from surface of interface between active layer and gate-insulating film or is in point condition in contact with this surface of interface.
EFFECT: production of field transistor with high drift mobility.
4 cl, 4 dwg, 2 ex
SUBSTANCE: amorphous oxide compound having a composition which, when said compound is in crystalline state, has formula In2-xM3xO3(Zn1-YM2YO)m, where M2 is Mg or Ca, M3 is B, Al, Ga or Y, 0 ≤ X ≤ 2, 0 ≤ Y ≤ 1, and m equals 0 or is a positive integer less than 6, or a mixture of such compounds, where the said amorphous oxide compound also contains one type of element or several elements selected from a group consisting of Li, Na, Mn, Ni, Pd, Cu, Cd, C, N, P, Ti, Zr, V, Ru, Ge, Sn and F, and the said amorphous oxide compound has concentration of electronic carriers between 1015/cm3 and 1018/cm3.
EFFECT: amorphous oxide which functions as a semiconductor for use in the active layer of a thin-film transistor.
6 cl, 8 dwg
SUBSTANCE: in a field-effect transistor which includes an oxide film as a semiconductor layer, the oxide film has a channel part, a source part and a drain part, and concentration of one of hydrogen or deuterium in the source part and in the drain part exceeds that in the channel part.
EFFECT: invention enables to establish connection between the conducting channel of a transistor and each of sources and drain electrodes, thereby reducing change in parameters of the transistor.
9 cl, 13 dwg, 6 ex