Correlation meter time shifts

 

The invention relates to the field of computer engineering and can be used to process a random process. The technical result is simplification. The meter contains an analog-to-digital Converter, a register, a multiplier, a group accumulative adders, multiplexer, demultiplexes, unit extremum seeking control unit. 1 C.p. f-crystals, 5 Il.

The invention relates to specialized devices to retrieve information and is used to measure phase shifts between random analog signals.

The known correlation meter time shifts, containing two correlator, the subtraction unit, the adjustable delay unit, the unit constant delay, amplifier and two controlled filter, and the outputs of the first and second correlators are connected to the corresponding inputs of the subtraction unit whose output via the amplifier is connected with the control input of the adjustable delay unit, the output of which is directly and through the block constant delay respectively connected with the first inputs of the first and second correlators, the second inputs of which are connected with the output of the first controlled filter, the output of the second uplo and second driven filters are respectively the first and the second input device, the control inputs of the first and second controlled filters combined and connected to the output of the amplifier [and.with. The USSR №1101837, publ. in BI 1984, No. 25].

The lack of correlation meter is a great instrument volume.

The closest in technical essence to the proposed correlation meter is a meter that contains two analog-to-digital Converter (ADC) register, a multiplier, a memory unit and group k accumulative adders, first and second information inputs of the meter are respectively informational inputs of the first and second ADCS, the meter output is the output of the group k accumulative adders, the entrance of which is connected to the output of the multiplier, a first input connected to the output register and the second input with the output of the memory block, the outputs of the first and second ADCS are connected respectively to the information inputs of the memory unit and the register [Kulikov E. I. Methods of measurement of random processes. - M.: Radio and communication, 1986, page 261, Fig.5.21].

Meter-the prototype can be used to determine the values of the relative time shifts by finding the coordinates of intercorrelation function with maximum value by comparing the results of nanoplate to store the array of multi-bit operands (samples of one of the signals). Moreover, these sites are among the most complex and expensive of used in digital electronics.

Technical result achieved when using the present invention is to simplify the correlation meter through the use of the structure is only one ADC and exceptions memory block. As a consequence, decreases the cost of the meter and increases its reliability.

The technical result is achieved by the fact that in the known correlation meter time shifts, containing analog-to-digital Converter, a register, a multiplier, and the group k accumulative adders, the output register connected to the first input of the multiplier, according to the invention introduced multiplexer, two demultiplexer, the unit extremum seeking control unit, the output of the multiplexer is connected to the information input of the analog-to-digital Converter, the output of which is connected to the information input of the first demultiplexer, the first output of which is connected with the information input register, a second input of the multiplier is connected to the second output of the first demultiplexer, the output of the multiplier is connected to the information input of the second demultiplexer, k outputs to the s with the corresponding k information input unit extremum, the output which is the output of the meter, the information inputs of the meter are respectively the first and second information inputs of the multiplexer, the address input is combined with the address input of the first demultiplexer and connected to the first address output control unit, the second address output of which is connected to the address input of the second demultiplexer, the first, second and third clock outputs of the control unit is connected to the clock inputs of analog-to-digital Converter, register and accumulative adders, respectively, inputs reset accumulative adders combined with boleushim input unit extremum seeking and connected to boleosoma output control unit, control output of which is connected to the triggering input unit extremum, inputs start and zero correlation meter are the corresponding inputs of the control unit.

In addition, the technical result is achieved by the fact that the unit extremum seeking control contains a group k of the comparator, encoder, counter, trigger, clock generator pulses, the And gate, an inverter, and the first inputs of the Comparators are information input unit extremum seeking, second input coleuses input trigger and represents Abdoulaye the input unit, trigger input which is the input set to the trigger unit, the output of which is connected to the first input element And a second input connected to the output of the inverter, whose input is connected to the output of the excitation encoder, the third input element And is connected to the generator output clock pulses, the output element And is connected to the subtractive output of the meter, the input data which is used for the initial download of the source code.

The invention is illustrated temporary diagrams and functional schemes.

In Fig.1 shows timing diagrams illustrating the measurement of the relative time shifts of the method pairwise uncorrelated samples; Fig.2 shows a functional diagram of the correlation meter the phase shifts of Fig.3 is a functional block circuit 8 extremum seeking (an example of execution) of Fig.4 is a functional block circuit 9 control (sample version); Fig.5 is a timing diagram illustrating the operation of the control unit 9.

The timing diagram in Fig.1 contains a sample of the signal x(t) and sampling the signal y(t), delayed relative to x(t).

Functional diagram of the correlation meter (Fig.2) contains 1 multiplexer, analog-to-digital Converter is s, unit 8 extremum and the control unit 9. The output of the multiplexer 1 is connected to the information input of the ADC 2, the output of which is connected to the information input of the demultiplexer 3, the first output of which is connected to the information input of the register 4, the output of which is connected to the first input of the multiplier 5, a second input connected to the second output of the demultiplexer 3, the output of multiplier 5 is connected to the information input of the demultiplexer 6, k outputs of which are connected to information inputs of the respective accumulative adders group 7, the outputs of which are connected with the corresponding information input unit 8 extremum, the output of which is the output of the meter, inputs X and Y of the meter are respectively the first and second information inputs of the multiplexer 1, the address input is combined with the address input of the demultiplexer 3 and is connected to the address output A1 of the control unit 9, the address output A2 is connected to the address input of the demultiplexer 6, the clock inputs CLK1, CLK2 and CLK3 of the control unit 9 is connected with a clock input ADC 2, case 4 and accumulative adders 7, respectively, the inputs are zeroed adders group 7 combined with boleushim entrance block the m input unit 8 extremum, control inputs and WITH zero RST correlation meter are the corresponding inputs of the control unit 9.

Unit 8 extremum (Fig.3) contains a group of 10 k Comparators, the encoder 11, a counter 12, a trigger 13, the generator 14 clock pulses, the And gate 15 and an inverter 16. The first inputs of the Comparators group 10 are information input unit 8, the second inputs of the Comparators group 10 United and connected to the information output DO of the counter 12, the input L boot which combined with boleushim input trigger 13 and represents Abdoulaye the RST input unit 8, the triggering input of DC1 which is the input set to the trigger unit 13, the output of which is connected to the first input element And 15, a second input connected to the output of the inverter 16, the inlet of which is connected to the output G of the excitation encoder 11, the third input element And 15 connected to the output of generator 14 clock pulses, the output element And 15 is connected to a subtractive input “-1” counter 12, the input data DI which is used for the initial download of the source code.

The control unit 9 in Fig.4 contains triggers 17 and 18, the divider 19 frequency counters 20 and 21, the generator 22 of clock pulses, the And gate 23, the element OR 24, the elements 25, 26, 27 and 28 of the delay. Su D-input of the trigger 18, the output of which is connected to the first input element And 23, the second input is combined with a clock input of the trigger 18 and is connected to the output of the generator 22, the inputs of the divider 19 and the element 25 delay combined with a summing input of the counter 20 and is connected to the output element And 23, a summing input of the counter 21 through the element 27 delay connected to the output element 25 delay, the output of which is the first clock CLK1 output of the control unit 9, the second clock CLK2 output which is the output element 26 delays the input connected to the output of the divider 19 frequency the output of which is the first address output A1 of the block 9, the third clock CLK3 output which is the output element 28 delays the input connected to the output element 27 delay, abdulaye inputs of the trigger 18, the counters 20, 21 are integrated with the first input element OR 24 and serve boleushim the RST input of the control unit 9, the output of the overflow of the counter 20 is connected to the second input of the OR element 24 and represents the triggering DC1 output unit 9, the second address output A2 which is an informational output of the counter 21, the output of the OR element 24 is connected with boleushim input trigger 17.

The timing diagram in Fig.5 contain the clock pulses CLK (what erom address output unit 9; the clock pulses CLK1 (Fig.5g) on the first clock output unit 9; the clock pulses CLK2 (Fig.5D) on the second clock output unit 9; heartbeats “+1” (Fig.5e) to the summing input of the counter 21; the clock pulses CLK3 (Fig.G) on the second clock output unit 9; the current address code A2 (Fig.S) on the second address output unit 9.

The claimed correlation meter delay time used for processing a centered, stationary and ergodic random processes x(t) y(t). The basis for operation of the meter lies in the method of measurement of the correlation function uncorrelated paired samples. Time shiftbetween the signals x(t) and y(t) is determined by the position of the peak mutual correlation function R(), the coordinates of which are calculated as follows.

The value of the process x(t) at time tii.e. x(ti) (Fig.1), which is leading sequentially To multiply the samples of the second signal y(ti+kt)(k=1,2...,K) appearing intervalt. After the first (or i-th cycle calculation To works of x(ti) y(ti+kt) to the resulting values are added the result is if">t). And so during the entire observation interval, the end of which will be accumulated To amounts

where (I+1) is the number of samples of the signal x(ti) during the observation interval. Kt specifies the value artificially made time shift necessary to calculate the ordinate mutual correlation function R(). The maximum value of the shift depends on the maximum possible relative delaymaxbetween the signals x(t) and y(t) and is selected from the condition

tmax

So the bottom border of the measurement range ist. Thus, at a constant sampling periodt is the required number of times the delayed signal y(t) during one cycle of computation. As for the signal x(t), it is sampled at a time depending on the value of k:

It is easy to see that when i=0 t0=0, if i=1 ti=(K+1)t, if i=2 t2=2(K+1)t etc. Then Edna dependence of the sampling period samples of the signal x(t) on the parameter K, specifies the length of the cycle, the sample size within a cycle and dependable, in turn, from the maximum possible delaymaxbeing measured. Physically reducing the sampling rate of the signal x(t) with increasing values of K due To the need for more long-term expectations of the “arrival” of strongly correlated counting process y(t), delayed relative to x(t). Therefore, when the designated number of samples i=i the observation time T will depend on the measuring range of the device and is determined by the formula

The launch of the correlation meter (Fig.2) is produced by feeding the input WITH trigger pulse, after which the control unit 9 starts the supply of clock pulses CLK 1, CLK 2 and CLK 3 clock inputs of the ADC 2, the buffer register 4 and accumulative adders 7, respectively. In the initial moment of time tifor example, at time t0on entry register 4 receives the reference signal x(t), i.e. x(t0). This is set by applying a logical unit to the address inputs of the multiplexer 1 and the demultiplexer 3, the first of which commutes on ADC input 2 signal x(t), and the second sends the reference x(t0) to the input buffer reg is sky logical level), switching these nodes in another possible mode switching, namely the ADC input 2 is switched already signal y(t), and ADC output 2 signal is routed through the demultiplexer 3 to the second input of the multiplier 5, the first entrance which is already present count x(t0). Since clocking of the ADC 2 is intervalt,, therefore, the output of the ADC 2 have a sample y(t0+t) Thus, the time t0+t corresponds to the appearance at the output of the multiplier 5 pieces x(t0)y(t0+t), which, through the demultiplexer 6 is directed to an information input of the accumulating adder 7-1. ADC 2 digitizes the signal values y(t) for cycle time and, therefore, at the output of the multiplier 5 for loop is formed It works

X(t0)y(t0+kt), k=1,2,...K.

Each of these works is sent to the appropriate channel accumulating adder group 7 according to the rule: k-e work in the k-th adder. Commutes results of multiplication of the samples demultiplexer 6, the managed address code received from the output A2 of the control unit 9. P is multiplexor 3 again set the level of logical units, as a result the ADC input 2 signal x(t), and ADC output 2 next value of x(ti+1), in our example, x(t1) to the input of the buffer register 4, where it is stored in the lifetime calculations. As in the previous cycle, this cycle is the formation of samples y(ti+kt), in our example, y(t1+kt), which, after multiplying by x(t1) are distributed over adders group 7, each of which is the summation is there previously obtained result.

After (I+1)-th cycle processing on the outputs of the adders group 7 will be formed of the amount of the form (1), which differ from the ordinate inter correlation function R() by a constant factor 1/(I+1), perform the function of averaging. Given that all sums of the form (1) differ by the same factor, to search for the greatest amount of k obtained to multiply them by a factor of 1/(I+1) is not necessary. Thus, block 8 extremum search for the greatest amount of the form (1), on which the decision on the position of the ordinate mutual correlation function R() with the highest value, i.e. defining tp://img.russianpatents.com/chr/964.gif">* calculated with discretet according to the formula:

*(k,t)=kt,

where k is the sequence number of the channel adder group 7, which received the greatest amount of the form (1).

In the base block 9 extremum (Fig.3) is a line of digital Comparators 10, connected to the encoder 11. At first United inputs (right scheme) of the comparator 10 receives the code threshold level set by the counter 12, and the second input of each of Comparators binary code k-th sum of the form (1).

Since before the beginning of the measurement device (Fig.2) zero and since the input load L of the counter 12 is combined with boleushim entrance, therefore, the counter 12 is written to the initial code - number 2m- 1, where m is the number of output bits of the adder group 7, which determines the maximum possible cumulative sum output of the adder. Pulse start DC1, which goes to the S-input of the trigger 13, the counter 12 is included in the subtraction mode - potatoo reduce the code number 2m- 1 unit LSB. Operands recorded on the channel outputs of the adders 7, are compared with the specified counter 12 level and at the onset of Ni, which, being transferred by the logical chain encoder 11 to the inverter 16 is an element ZI 15, stops the counter 12. At the output of the encoder 11 is fixed binary code is the sequence number of the channel in which accumulated the highest amount of the form (1).

Relative to the encoder 11 note that its quality can be used IC 555 IF (output excitation G - conclusion No. 14), which is included in this unit considering the fact that the inputs and outputs of the inverting it.

Consider the principle of generation of control signals for example, the execution control unit 9 according to Fig.4.

Before the launch of sequential logic block 9 zero translating it thus in the standby trigger pulse.

With occurrence of a triggering pulse FROM arriving at the S-input of the trigger 17, the output of the trigger 18 synchronously with the positive front of the next clock pulse (Fig.5A) is set to a high logic level, allowing the passage of clock pulses to the inputs of the divider 19 and frequency counters 20, 21. Because according to the measurement algorithm in the buffer register 4 at the beginning of the cycle is filled in with the reference signal x(t), for the formation of the address signal, sending the signal x(t), is the first impul demultiplexer 2 are under the influence of high logical level, providing switching at the input of the register 4 of the signal x(t1). Information in the register is recorded on the leading edge of the zero clock pulse CLK2 (Fig.5D). After the expiration of the address pulse 1 multiplexer and demultiplexer 2 pass mode switching signal y(t), discretizing in rhythm with the pulse sequence CLK1 (Fig.5g). In our example, suppose k=3, then each cycle will consist of four (k+1) clock pulses (Fig.5g), the last three of which are used for taking samples of the signal y(t). Simultaneously, clock pulses from the output of the element 2I 23 arrive at the counting input of the counter 21 (Fig.5e), which performs the functions of the address and controls the switching in the demultiplexer 6. In connection with the peculiarities of forming of the address code (Fig.S) when using demultiplexer with traditional sequential addressing you for the first channel (the adder 7-1) connect the output of the demultiplexer, activated at the address corresponding to the binary code number “2”, the second channel (the adder 7-2) is the output corresponding to the binary code number “3” and so on, in ascending order, and the last channel, in our case, the third must match address number zero. I eventually zero. Address, which is called the first output channel of the demultiplexer, is not used because according to the sequence of operations of multiplication counts in cycles of this clock interval (zero clock interval) occurs only preparation multiplier for calculations within the loop.

The countdown of the duration of the observation interval T with discretest is a counter 20, a conversion factor which is chosen so that with the end of the observation interval began to develop momentum overflow, which boleushim for the trigger 17 and runs for a block of 8 extremum seeking.

Time shifts introduced by the elements 25, 26, 27, 28 delay, provide sustainable unambiguous operation of the meter due to time-shift moments updating information and points of fixation. When implementing a meter in shemotehnicheskom basis TTLS time delay elements 25, 26, 27 and 28 are selected so that conditions were performed (Fig 5, d, e, f, g): delay time sequence CLK1 relatively A1 should be (40-50) na sequence CLK2 relative to CLK1 1.5 tnp(tCRthe conversion time of the ADC 2), the sequence “+relatively “+1” 1.5 tsum+40 NS (tsumthe time summation in the adder group 7).

The information in the meter can be presented in both serial and parallel codes. In this connection it should be noted that if the ADC output data 2 do in parallel code and then the code is converted to serial is not, shown in the diagram (Fig.2) signal links in the chain ADC 2 - demultiplexer 3 - case 4 - multiplier 5 - demultiplexer 6 is a group of adders 7 block 8 should be implemented as multi-bit buses (in the diagram according to Fig.2 links shown conventionally in the form of a single-chain without specifying bit). Likewise, when the representation of the data in blocks 8 and 9 in a parallel connection of the counter 12 with the Comparators 10 and the counter 21 with demultiplexer 6 must also be made in the form of multi-bit buses.

Claims

1. Correlation meter time shifts, containing analog-to-digital Converter, a register, a multiplier, and the group k accumulative adders, the output register connected to the first input of the multiplier, characterized in that it introduced the multiplexer, two demultiplexer, the unit extremum seeking control unit, the output of the yen to the information input of the first demultiplexer, the first output of which is connected with the information input register, a second input of the multiplier is connected to the second output of the first demultiplexer, the output of the multiplier is connected to the information input of the second demultiplexer, k outputs of which are connected to information inputs of the respective k accumulative adders whose outputs are connected to respective k information input unit extremum, the output of which is the output of the meter and is designed for fixation of the binary code sequence number of the channel in which accumulated the greatest amount of information inputs of the meter are respectively the first and second information inputs of the multiplexer, the address input is combined with the address input of the first demultiplexer and connected to the first address output control unit, the second address output of which is connected to the address input of the second demultiplexer, the first, second and third clock outputs of the control unit is connected to the clock inputs of analog-to-digital Converter, register and accumulative adders, respectively, inputs reset accumulative adders combined with boleushim input unit extremum seeking and the connection is ska extremum, inputs start and zero correlation meter are the corresponding inputs of the control unit.

2. Correlation meter time shifts under item 1, characterized in that the block extremum contains a group k of the comparator, encoder, counter, trigger, clock generator pulses, the And gate, an inverter, and the first inputs of the Comparators are information input unit extremum, the second inputs of the Comparators are combined and connected to the information output of the counter, the input load which combined with boleushim input trigger and represents Abdoulaye the input unit, trigger input which is the input set to the trigger unit, the output of which is connected to the first input element And a second input connected to the output of the inverter, the inlet of which is connected to the output of the excitation encoder, the third input element And is connected to the generator output clock pulses, the output element And is connected to the subtractive output of the meter, the input data which is used for the initial download of the source code, the Comparators are connected to the encoder, the output of which is fixed binary code is the sequence number of the channel in which accumulated the highest amount.

 

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