Correlation analyzer

 

The invention relates to the field of computer engineering and can be used for analysis of random processes. The technical result is to increase functionality. The analyzer contains a correlator, a subtraction unit, a memory block, the block averaging and the control unit. 3 Il.

The invention relates to specialized computing means and is used for comparative analysis of random processes, spaced in time.

The known correlation analyzer, built according to the classical scheme of parallel correlation analysis and containing the first and second input blocks, a delay line, n multiplier products, n equalization tank and the display, and the first n inputs of multiplier products combined and connected to the output of the first input unit and the second inputs of the n multiplier products connected to the corresponding n taps of the delay line including exhaust with zero delay, the input of which is connected to the output of the second input unit, the device inputs are inputs of the input blocks, the n outputs of the multiplier products are connected to respective inputs of the display through n equalization tank [Mirsky, I. E measurement. - M.: Radio and communication, 1986, S. 291, Fig.8.12].

The closest in technical essence to the proposed analyzer is a correlation analyzer contains two correlator block subtraction, the adjustable delay unit, the unit constant delay, amplifier and two controlled filter, and the outputs of the first and second correlators are connected to the corresponding inputs of the subtraction unit whose output via the amplifier is connected with the control input of the adjustable delay unit, the output of which is directly and through the block constant delay respectively connected with the first inputs of the first and second correlators, the second inputs of which are connected with the output of the first controlled filter, the output of the second controlled filter is connected to the information input of the adjustable delay unit, the information inputs of the first and second driven filters are respectively the first and second inputs of the device control inputs of the first and second controlled filters combined and connected to the output of the amplifier [A. S. of the USSR №1101837. Publ is BSA structure analyzer does not allow a comparative analysis of signals, acting is not at the same time, so as not provided by the possibility of storing information about the current signal.

The lack of correlation analyzer prototype is the lack of functionality of joint processing of signals operating at different points in time to determine the extent of their similarity.

Technical result achieved when using the present invention, consists in the possibility of quantitative determination of the degree of similarity of signals operating at different points in time.

The technical result is achieved by the fact that in the known correlation analyzer containing the correlator and the subtraction unit, the first input connected to the output of the correlator according to the invention introduced the memory block, the block averaging and the control unit, and the second input of the subtraction unit is connected to the output of the memory unit, the information input of which is connected to the output of the correlator, the address input is combined with the address input of the memory block and is connected to the address output control unit, the gate output of which is connected to the gate input of the correlator, the information input by the information input analyzer, Tania, and the clock input is connected with the corresponding output of the control unit, Abdoulaye input is combined with alnoaimi inputs of the correlator and block averaging and is boleushim the analyzer input, first and second control inputs of which are the corresponding inputs of the control unit, the control inputs of the memory block connected to respective outputs of the control unit.

The invention is illustrated by the functional circuits and timing diagrams.

In Fig.1 shows a functional diagram of the correlation analyzer of Fig.2 is a timing diagram illustrating the operation of the analyzer of Fig.3 is a block diagram of the control unit (an example of execution).

Correlation analyzer of Fig.1 contains the correlator 1, block 2 subtraction, block 3 of memory presented in the form of a RAM, the block averaging 4 and unit 5 controls. The first and second inputs of block 2 subtraction are connected respectively with the information outputs of the correlator 1 and RAM 3, respectively, the information input RAM 3 is connected to the output of correlator 1, the address input is combined with the address input of the RAM 3 and is connected to the address output control unit 5, the gate output of which is connected to the strobe input E to which is the output of block 4 averaging, an information input connected to the output of block 2 of the subtraction, and the clock input CLK is connected with the corresponding output of the control unit 5, Abdoulaye the RST input of which is connected alnoaimi inputs RST correlator 1 and block 4 and is averaging boleushim the RST input of the analyzer, the first C01 C02 and second control inputs of which are the corresponding inputs of the control unit 5, the control inputs CS andRAM 3 are connected with the corresponding outputs of the control unit 5.

The timing diagram (Fig.2) contain the RST pulse of the reset analyzer (Fig.2A); the first C01 C02 and second control pulses analyzer (respectively Fig.2B and Fig.2B); the gate pulse E at the input of the correlator 1 (Fig.2G); current address code Andithe address inputs DA correlator 1 and RAM 3 (Fig.2D); the pulses CS select RAM 3 (Fig.2E); the clock pulses CLK to the clock input unit 4 averaging (Fig.2ZH); pulseread RAM 3 (Fig.2H).

The control unit 3 (Fig.3) contains the counters 6 and 7, the trigger 8, 9 and 10, items 2, 11, 12 and 13, the elements ILI 14, 15, 16, 17, 18, 19 and 20, the delay element 21 and the generator 22 of clock pulses. The first and second inputs of the element ILI 14 are respectively first C01 and the second And 15, 16, 17, 18 and 19, the outputs of which are connected to boleushim inputs of the trigger 8, the counter 6, the trigger 10, the trigger 9, the counter 7, respectively, the second inputs of elements ILI 15 and 16 are combined and connected to the output of the overflow of the counter 6, the second inputs of elements ILI 17, 18 and 19 are United and connected to the output of the overflow of the counter 7, the bit outputs of which are targeted output And the control unit 5, the gate output E, which is the trigger output 8 connected to the first input element 2I 11, the second input is combined with the first input element 2I 12 and is connected to the output of the generator 22 of clock pulses, the outputs of the elements 2I 11 and 12 are connected to a summing inputs, respectively, of the counters 6 and 7, the output of the overflow of the counter 6 is connected with the input set to the trigger unit 9, the output of which is connected with the second input element ILI 12, the output of which is connected to the input of the delay element 21, the output of which is connected with United first inputs of elements ILI 20 and 2 And 13, the second inputs of which are also combined and connected to the output of the trigger 10, the input set to the unit which is combined with the second input element ILI 14, the output of which is connected with the input set to the trigger unit 8, the output of the trigger 10 and the output Alameda CLK which is the output element 2I 13. The principle of correlation analyzer is based on the alternate calculation of the autocorrelation functions RXX(iand RYY(irespectively the signals X(t) and Y(t) is stationary and ergodic, operating at different points in time, remembering and then comparing the obtained values. The first of the calculated features is stored in a specially allocated under her memory and can be stored for quite a long time (real limits) prior to a second signal. Therefore, temporary restrictions on the relative shift of the processes X(t) and Y(t) in practical tasks can generally be absent, and theoretically determined maximum possible storage time information without destruction specifically used storage structures. Second autocorrelation function, the analysis process is retrieved directly from the memory cells (accumulative adders, for example) of the correlator.

The beginning of the computing operations in the analyzer (Fig.1) is preceded by zeroing all sequential logic correlator 1, block 4 of averaging and control unit 5, which on input RST served Abdoulaye pulse (Fig.2A). With the beginning of the action is in store entrance C01 serves triggering pulse (Fig.2B). In response, the control unit 5 generates a strobe pulse (Fig.2B), the duration of which determines the duration of the observation interval, during which the correlator 1 carries out the averaging necessary to calculate the autocorrelation function RXX. At the end of the observation interval on the shared address bus, the device begins a sequential scan addresses (Fig.2D) that is required to write into the RAM 3 the calculated values of the ordinates of the autocorrelation function RXX(i), (i - ordinates, i=0,1,...NI=i,the discrete delay). Thus, putting on call address code to output the data bus correlator calculated values of RXX(i) alternately act on the information input RAM 3, and stored in the memory of the latter under the action of the specially formed permitting pulses CS (Fig.2E), the time of formation are somewhat shifted in time towards lag relative to the point of change of address. Control mode in which the RAM 3, is input

When the input X, Y signal Y(t) on the second control input C02 serves the starting pulse, and therefore the correlator 1 begins the process of computing the autocorrelation function RYY(i). Simultaneously with the second run of the analyzer control unit 5 generates a pulseread RAM 3 (Fig.2H), which translates RAM 3 mode, read the rest of this cycle of analysis.

At the end of the second gate pulse E (Fig.2G), when the correlator 1 prepared ordinate values of the autocorrelation function RYY(i), on the address bus again begins the formation of the address code Andi. When this RAM 3 by a combination of pulses CS and(Fig.2E, h) is translated into a read mode and transmit the information to the output, i.e. to the input of block 2 of the subtraction, to the other input of which simultaneously receives information directly from the output of the correlator 1. Thus, each i-th cycle in accordance with a destination address at the inputs of block 2 of the subtraction will be the values of the ordinates RXX(i) - RYY(i)| sent in block 4 of averaging, where the calculation of the mean deviation M[RXY]:

From the last expression it is easy to see that the degree of similarity of the processes X(t) and Y(t) in the inventive device is determined by determining how little the average value M[RXY] the difference of their autocorrelation functions. Of course, in the ideal case, the absolute equality of the calculated valuesXX(iand RYY(iwill match equal to zero and their standard deviation: M[RXY]=0.

Relative implemented in the analyzer method note that since the autocorrelation function of the signals are closely related to their energy spectra using Fourier transforms, the degree of equality is possible to judge the degree of similarity of the energy spectra, i.e. the value of M[RXY]. Let us also add that ifi=0 tp://img.russianpatents.com/chr/963.gif">2in turn, equal to the average power of the process, in this case the process X(t). Consequently, the structure of the analyzer 1 according to Fig.1 allows us to calculate the difference of average power processes X(t) and Y(t). It is enough to fix the output of block 2 subtracting the value of the difference between |RXX(iand RYY(i) | (I=0.

Let us further consider some of the specific features of the individual blocks declared analyzer (Fig.1).

The structure analyzer developed in the assumption that the correlator 1 is a multichannel device for parallel computation of the correlation function R(i), where i is the number of channels is determined by the number calculated ordinate, and the resulting values of y can be stored in accumulating the adders-equalization tank or meter sticks. The output of the correlator selected values of R(i) is accomplished by multiplexing the data contained in the adders of the device. Controlling transfer of said data output is performed in the address bus And the correlator 1 by setting code, snaco should be a mandatory requirement for structural diagram of the correlator 1: the device must contain the (N+1)-channel multiplexer, channel inputs of which are connected with the information output channel accumulative adders-equalization tank, and the address multiplexer input is an address input of the correlator.

Unit 4 averaging in the claimed correlation analyzer can be made in the form of cascaded accumulating adder and devices division by a constant factor N+1. As the last device can be applied to an EPROM with a pre-recorded values of the possible outcomes of the division, i.e implemented hardware-tabular method of performing arithmetic operations. Input CLK provides clocking internal registers accumulating adder.

An example of a specific implementation of the control unit 5 shown in Fig.3.

The control unit 5 operates as follows.

After resetting all flip-flops and counters unit 5 to the input C01 served first trigger pulse (Fig.2B) is indicative of the first signal X(t). On the front of the specified pulse trigger 8 state is a high logic level at the output, passing the appropriate level (Fig.2G) to the gate output E of the block 5 and, in addition, gives a command to the count of the counter 6. The last counts in the deposits is determined by the moment of occurrence of the pulse overflow at the output P of the specified counter. Therefore the trigger 8 is transferred to the initial state, the account stops, and the trigger 9 is transferred into the state high logic level at summing input of the counter 7 is allowed to pass clock pulses and begins the process of forming the current address Andi(Fig.2D) that is used at this stage for podlesney recording information in the RAM 3. With some delay in time change the address code is accompanied by the appearance of pulses CS, permitting the work RAM 3. These pulses pass through the element 21 of the exit delay element ILI 20. The delay time is selected based on the requirements for temporary allocation of specific signals in the RAM chips. After forming the code of the last address counter 7 is reset, the trigger 9 is transferred to the initial state and the control unit 5 ends the cycle of generation of control actions.

The next cycle begins with the receipt of the second trigger pulse to the input C01 (Fig.2B). In this case the algorithm unit 5 control remains the same as described above, except that the trigger 10 passes in a single state and, consequently, is set to a high logic level outputsand served the clock pulses to the control unit 4 averaging.

From the description of the operating principle of the analyzer and circuit performance can be seen that for mutual signal processing, each separated by wide intervals of time and not overlapping with each other, not necessarily to apply complex compensating delay line. Theoretically, the delay line can eliminate any temporary mismatch and, therefore, allows the use of the correlators of classical type. However, this significantly increases both the cost of the whole device and its hardware volume. Hardware volume stated analyzer invariant with respect to time shifts of the investigated signal.

Claims

Correlation analyzer containing the correlator and the subtraction unit, the first input connected to the output of the correlator, characterized in that it introduced the memory block, the block averaging and the control unit, and the second input of the subtraction unit is connected to the output of the memory unit, the information input of which is connected to the output of the correlator, the address input is combined with the address input of the memory block and is connected to the address output control unit, the gate output cohadon analyzer, the output which is the output of block averaging, an information input connected to the output of the subtraction unit, and a clock input connected with the corresponding output of the control unit, Abdoulaye input is combined with alnoaimi inputs of the correlator and block averaging and is boleushim the analyzer input, first and second control inputs of which are the corresponding inputs of the control unit, the control inputs of the memory block connected to respective outputs of the control unit.

 

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