Recirculating register file
The invention relates to data processing systems having a rated Bank and supporting vector operations. The technical result consists in increasing the efficiency and performance of data processing. A device for processing data register contains a Bank with multiple addressable registers and a command decoder, responsive to at least one command data defining a vector operation that repeatedly executes the processing operation of the data using the data values from a sequence of registers in the register Bank, starting from the source register specified in the above command, the data in this register Bank includes at least one subset of registers, and a command decoder configured to control the sequence of registers for its “loop” within the mentioned subset of registers. Data processing method describes the operation of the device. 2 C. and 13 C.p. f-crystals, 17 tab., 33 table. Description text in facsimile form (see graphic part).
Claims1. A device for processing data containing the register babochki data determining a vector operation that repeatedly executes the processing operation of the data using the data values from a sequence of registers in said register Bank, starting from the source register specified in the above command, data processing, these register Bank includes at least one subset of registers, and the above sequence of registers is in said subset and said command decoder is configured to control the said sequence registers for its "loop" within the mentioned subset of registers.2. The device under item 1, in which the mentioned vector operation performs the operation of processing data using a number of corresponding data values from the corresponding set of sequences of registers; the register Bank contains many subsets of registers, and referred to the set of all sequences of registers is displayed in the corresponding subsets; the command decoder control the said sequence of registers to perform a "loop" within their respective Podmore eusto according to any one of paragraphs.1-3, in which the said subset contains the sampling interval following each other numbers of registers.5. The device according to p. 2, in which each of the said multiple subsets contains a sampling interval of consecutive numbers of registers.6. The device under item 5, in which the said multiple subsets contains the appropriate adjacent sampling intervals following each other numbers of registers.7. The device according to p. 6, which contains 4 adjacent sampling interval.8. Device according to any one of the preceding paragraphs which includes the additional memory and the controller of the transmission to control the transmission of data values between the memory and registers in said register Bank, and the said controller drives are designed with the ability to respond to many commands to send to send a sequence of data values between the memory and the sequence of registers in said register Bank.9. The device according to p. 6, in which each sampling interval is addressed through incrementor that "looped" between the end points of the sampling interval.10. Device according to any one of the preceding paragraphs, in which the mentioned n the WMD from the preceding paragraphs, which referred to the register Bank and said command decoder are part of the block floating-point number.12. A method of processing data according to which to store data values in the set of addressable registers of the register Bank in response to at least one command data defining a vector operation, perform the operation processing data iteratively, using the data values from a sequence of registers in said register Bank, starting from the source register specified in the above command, data processing, these register Bank includes at least one subset of registers, moreover, the above-mentioned sequence of registers is mentioned in the subset and in the execution of data processing operations mentioned sequence registers sealcoat" within the mentioned subset of registers.13. The method according to p. 12, in which when performing the said vector operation for these data processing operations use many times the corresponding data values from the corresponding set of sequences of registers, and referred to the register Bank stereotactic subsets and during the said operation processing data mentioned many sequences registers sealcoat" within the respective subsets of registers.14. The method according to p. 13, in which the data values in one sequence are coefficients of taps of the filter, and the data values in the other sequence are the values of the signals for filtering the said filter.15. The method according to p. 12, wherein a set of vector operations performed on the data values in the above-mentioned set of all sequences starting point, at least one sequence change with each vector operation.
SUBSTANCE: configurable basic electrical element for forming outputs signals of electrical equipment includes processor means for performing a configurable function to generate outputs of the object of electrical equipment. Processor means contain a fast CPU and a slow processor segment segment in which functional blocks are implemented. Units operate relatively fast operations and a relatively slow operations. These units are independent and parameterized. Processor segments are configured to selectively connect and parameterize these functional blocks to perform a configured specified function.
EFFECT: increased reliability.
10 cl, 5 dwg
FIELD: engineering of data processing systems, which realize operations of type "one command stream and multiple data streams".
SUBSTANCE: system is disclosed with command (ADD8TO16), which decompresses non-adjacent parts of data word with utilization of signed or zero expansion and combines them by means of arithmetic operation "one command stream, multiple data streams", such as adding, performed in response to one and the same command. Command is especially useful for utilization in systems having a data channel, containing a shifting circuit before the arithmetic circuit.
EFFECT: possible use for existing processing resources in data processing system in a more efficient way.
3 cl, 5 dwg
FIELD: computing devices with configurable number length for long numbers.
SUBSTANCE: device consists of two computing device units, each of them divided into at least four subunits, which consist of a quantity of unit cells. Named units are spatially located so that the distance between unit cell of first unit and equal unit cell in the second unit is minimal. Computing device configuration can be changed using configurational switches, which are installed between device subunits.
EFFECT: increased performance of computing device, reduced time of data processing.
12 cl, 6 dwg
FIELD: network communications, in particular, control means built into applications for conduction of network exchange.
SUBSTANCE: expandable communication control means is used for maintaining communication between computing device and remote communication device. In a computer program adapted for using expandable communication control means, information about contacting side is found, and on basis of found contact information it is determined which types of transactions may be used for communication with contacting side at remote communication device. As soon as communication setup function is determined using contacting side information, communication setup request, associated with such a function, is dispatched to communication address. After receipt, expandable communication control means begins conduction of communication with remote communication device.
EFFECT: creation of more flexible and adaptable software communication control means (program components) for processing communications (connections, exchange) between devices.
3 cl, 11 dwg
FIELD: engineering of microprocessors and computer systems.
SUBSTANCE: in accordance to shuffling instruction, first operand is received, which contains a set of L data elements, and second operand, which contains a set of L shuffling masks, where each shuffling mask includes a "reset to zero" field and selection field, for each shuffling mask, if the "reset to zero" field of shuffling mask is not set, then data indicated by shuffling mask selection field are moved, from data element of first operand, into associated data element of result, and if "reset to zero" field of shuffling mask is set, then zero is placed in associated data element of result.
EFFECT: improved characteristics of processor and increased productivity thereof.
8 cl, 43 dwg
SUBSTANCE: invention pertains to the means of providing for computer architecture. Description is given of the method, system and the computer program for computing the data authentication code. The data are stored in the memory of the computing medium. The memory unit required for computing the authentication code is given through commands. During the computing operation the processor defines one of the encoding methods, which is subject to implementation during computation of the authentication code.
EFFECT: wider functional capabilities of the computing system with provision for new extra commands or instructions with possibility of emulating other architectures.
10 cl, 15 dwg
FIELD: physics; computer technology.
SUBSTANCE: present invention pertains to digital signal processors with configurable multiplier-accumulation units and arithmetic-logical units. The device has a first multiplier-accumulation unit for receiving and multiplying the first and second operands, storage of the obtained result in the first intermediate register, adding it to the third operand, a second multiplier-accumulation unit, for receiving and multiplying the fourth and fifth operands, storage of the obtained result in the second intermediate register, adding the sixth operand or with the stored second intermediate result, or with the sum of the stored first and second intermediate results. Multiplier-accumulation units react on the processor instructions for dynamic reconfiguration between the first configuration, in which the first and second multiplier-accumulation units operate independently, and the second configuration, in which the first and second multiplier-accumulation units are connected and operate together.
EFFECT: faster operation of the device and flexible simultaneous carrying out of different types of operations.
21 cl, 9 dwg
FIELD: information technologies.
SUBSTANCE: command of message digest generation is selected from memory, in response to selection of message digest generation command from memory on the basis of previously specified code of function, operation of message digest generation, which is subject to execution, is determined, at that previously specified code of function defines operation of message digest calculation or operation of function request, if determined operation of message digest generation subject to execution is operation of message digest calculation, in respect to operand, operation of message digest calculation is executed, which contains algorithm of hash coding, if determined operation of message digest generation subject to execution is operation of function request, bits of condition word are stored in block of parameters that correspond to one or several codes of function installed in processor.
EFFECT: expansion of computer field by addition of new commands or instructions.
14 cl, 18 dwg
FIELD: information technology.
SUBSTANCE: present invention relates to computer engineering and can be used in signal processing systems. The device contains an instruction buffer, memory control unit, second level cache memory, integral arithmetic-logic unit (ALU), floating point arithmetic unit and a system controller.
EFFECT: more functional capabilities of the device due to processing signals and images when working with floating point arithmetic.
4 cl, 4 dwg
FIELD: physics; computer engineering.
SUBSTANCE: invention relates to processors with pipeline architecture. The method of correcting an incorrectly early decoded instruction comprises stages on which: the early decoding error is detected and a procedure is called for correcting branching with a destination address for the incorrectly early decoded instruction in response to detection of the said error. The early decoded instruction is evaluated as an instruction, which corresponds to incorrectly predicted branching.
EFFECT: improved processor efficiency.
22 cl, 3 dwg, 1 tbl
FIELD: information technology.
SUBSTANCE: method involves defining a granule which is equal to the smallest length instruction in the instruction set and defining the number of granules making up the longest length instruction in the instruction denoted MAX. The method also involves determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length MAX-1 into the instruction string to the end of the embedded data. Upon pre-decoding of the padded instruction string, a pre-decoder maintains synchronisation with the instructions in the padded instruction string even if embedded data are randomly encoded to resemble an existing instruction in the variable length instruction set.
EFFECT: ensuring reconstruction during repeated synchronisation owing to reduced errors of synchronising the mechanism for pre-decoding the instruction string.
20 cl, 11 dwg