A method of manufacturing a non-volatile semiconductor memory cell with a separate tunnel window
The invention relates to a method of manufacturing a nonvolatile semiconductor memory cell (SZ) with a single cell (TF) with the tunnel window, and the tunneling region (TG) using cells (TF) with the tunnel window as a mask to perform at a late stage of tunnel implantation (IT). The technical result of memory cells with little need for the area and a large number of cycles programming/erasing. 2 C.p. f-crystals, 6 ill. The invention relates to a method of manufacturing a non-volatile semiconductor memory cell with a separate tunnel window and, in particular, to a method of manufacturing the EEPROM cell with a small need for the area and a large number of cycles programming/erasing.Non-volatile semiconductor memory cell with the ability to re-record gain in circuits with a high degree of integration all the more important because they are, for example, smart cards can store variable data for a long period of time and without the use of power.Depending on the type of nonvolatile semiconductor memory cells Prince who is basically, from cell TF with the tunnel window and transistor memory cell TZ. According Fig.5, transistor memory cell TZ consists of a relatively thick and impervious to the leakage currents of the layer 3 shutter, located on top of it a layer 5 floating gate, a dielectric layer 6 and layer 7 of the control electrode. Put in layer 5 floating gate charge determines the behavior of the corresponding field-effect transistor in the switching mode, which occurs through the field 1 of the source and drain and layer 7 of the control electrode. To enter charges in layer 5 floating gate memory cell contains the cell TF with the tunnel window, which basically has the same sequence of layers as the transistor memory cell TZ, moreover, however, the insulating layer between the semiconductor substrate 100 and the layer 5 of the floating gate consists of a very thin tunnel layer 4.When producing normal cells TZ EEPROM first carry out ion implantation in the area of the cell TF with the tunnel window for the formation of homogeneous tunneling region 2'. Then put the tunnel insulating layer 4 or layer 3 of the shutter and the layer 5 floating gate, a dielectric layer 6 and layer 7 driving the kăđẫa cell SZ as a mask, the semiconductor substrate 100 is performed by samoobladanie region 1 of the source and drain. Thus receive only high-quality non-volatile semiconductor memory cell with the possibility of re-recording, which has a very long service life. The lifetime indicates the number of cycles programming/erasing and the conventional EEPROM is typically about 106the loops.The disadvantage of these conventional EEPROM, however, is a high need in the area for the memory cell SZ, so it finds application in circuits with a high degree of integration only conditionally.In contrast, memory cells "fast" EPROM have very small need of space. In Fig.6 shows a section normal memory cells "fast" EPROM, and on the semiconductor substrate 100 is applied, the tunneling oxide layer 4, layer 5 floating gate, a dielectric layer 6 and layer 7 of the control electrode. To perform the tunneling region in the area of TF' tunnel window memory cells "fast" EPROM using stablehouse memory cells in the semiconductor substrate 100 is performed by samoobladanie the area of implantation. Then, using a memory cell and an additional auxiliary materials the Noah memory cells "fast" EPROM similarly, as described above EEPROM memory cells in layer 5 of the floating gate in area TF' tunnel window through the tunnel layer 4 is injected charge through, for example, injection of hot charge carriers and/or tunneling through the Fowler-Nordheim. Put this way, the charge carriers then determine the behavior of the zone TZ' transistor cell in the switching mode.Despite the significantly less need to square this normal memory cells "fast" EPROM, this type of non-volatile memory cells has one major disadvantage in that their service life, i.e. the number of cycles programming/erasing, significantly lower than that of the conventional memory cell EEPROM of Fig.4. As a rule, the life of these storage cells "fast" EPROM is about 103the loops.Another disadvantage of these conventional non-volatile memory cells with the possibility of re-recordings is that they can be combined in a common integrated circuit only conditionally. The reason for this is, in particular, the fact that pre-made according to Fig.5 implantation tunnel region 2' affects the thickness of the executed then the tunneling layer 4. More specifically, when primeape thickness, than in the storage cell "fast" EPROM of Fig.6. Next region 2' of the implant of Fig.5 very susceptible to subsequent heat treatment, whereas region 2 of the implant of Fig.6 perform only at a relatively late point in time in the manufacturing process. Due to this, executed in the same integrated circuit memory cell of Fig.4 and 5 having different voltage programming/erasing.Forth from US 5565371 known method of manufacturing a non-volatile semiconductor memory cell with a separate tunnel window, wherein the programming transistor memory cells is implemented by injection of hot charge carriers, and the erasing transistor memory cells through tunneling, Fowler-Nordheim. The disadvantage, however, is the high demand in the area, as well as many non-standard technological processes. The combination of this method with conventional methods, therefore, impossible.The basis of the invention lies in the task of creating a method of manufacturing a non-volatile semiconductor memory cell with a separate tunnel window when using standard processes would omens through events p. 1 formula.In particular, by performing tunneling regions in the active area of the cells with the tunnel window after performing the tunneling layer, you can create a non-volatile semiconductor memory cell, which in respect of its lifetime, i.e., cycles programming/erasing equivalent of a conventional EEPROM cell, however, significantly improved in respect of their needs in the area. In addition, manufactured thus memory cell can easily implement in a common integrated circuit with the normal memory cells "fast" EPROM using standard processes. Working voltage (voltage of the programming, erasing and reading) can be the same as for various forms of non-volatile semiconductor memory cells.Mostly tunneling region perform with samoobladanie using at least one layer of a cell with a tunnel window through implantation. In particular, schemes with a high degree of integration with structure sizes

Claims
1. A method of manufacturing a non-volatile semiconductor memory cell with a separate tunnel window consisting of the following steps: performing cell (TF) with the tunnel window with the tunnel region (TG), the tunneling layer (4), a storage layer (T5) of the tunneling window, a dielectric layer (T6) tunnel window and the layer (T7) of the control electrode of the tunneling window; follow-transistor memory cell TZ) with a channel region (KG), layer (3) of the shutter, the storage layer (5), dielectric layer (6) and a layer (7) the control electrode with run separately from one another transistor memory cell TZ) and cells (TF) with the tunnel window in active regions of a semiconductor substrate (100), and a connecting zone (VB) for connection of the cell (TF) with the tunnel window transistor memory cell (TZ) in the inactive region of a semiconductor substrate (100), while the tunnel doping region (TG) in the active region of the cell (TF) with the tunnel window is carried out after the execution of the tunneling layer (4), if the color under the tunnel layer (4), and when the application voltage zone (RLZ) space charge regions 2 implantation extend completely under the tunneling layer, wherein the tunneling region is performed through a relatively late process of manufacturing the tunneling implant IT, mainly corresponding tunnel implantation for simultaneously fabricated memory cells "fast" EPROM, which can be performed as cell TF with the tunnel window of the storage cells SZ, and areas with the tunnel window is made in the same process memory cells "fast" EPROM, both memory cells have the same properties of programming/erasing.2. The method according to p. 1, wherein performing the tunneling region (TG) is performed with MD-implantation.3. The method according to p. 1, wherein performing the tunneling region (TG) is performed with LDD-implantation.
FIELD: electronic engineering.
SUBSTANCE: device provided with short channel for controlling electric current has semiconductor substrate to form channel. Doping level of channel changes extensively in vertical direction and keeps to constant values at longitudinal direction. Electrodes of gate, source and discharge channels are made onto semiconductor substrate in such a manner that length is equal or less than 100 nm. At least one of source and discharge electrodes form contact in shape of Schottky barrier. Method of producing MOS-transistor is described. Proposed device shows higher characteristics at lower cost. Reduction in parasitic bipolar influences results to lower chance of "latching" as well as to improved radiation resistance.
EFFECT: improved working parameters.
24 cl, 11 dwg
FIELD: microelectronics; integrated circuits built around silicon-on-sapphire structures.
SUBSTANCE: proposed method for manufacturing silicon-on-sapphire MIS transistor includes arrangement of silicon layer island on sapphire substrate, formation of transistor channel therein by doping silicon island with material corresponding to channel type, followed by production of gate insulator and gate, as well as source and drain regions; prior to doping silicon island with material corresponding to channel type part of silicon island is masked; mask is removed from part of silicon island of inherent polarity of conductivity upon doping its unmasked portion and producing gate insulator; in addition, part of gate is produced above part of silicon island of inherent polarity of conductivity; source region is produced in part of silicon island of inherent polarity of conductivity and drain region is produced in part of silicon island doped with material corresponding to channel type.
EFFECT: improved output characteristics of short-channel transistor at relatively great size of gate.
1 cl, 7 dwg
FIELD: integrated-circuit manufacture on silicon-on-insulator substrate; transistor structures of extremely minimized size for ultra-high-speed integrated circuits.
SUBSTANCE: proposed method for manufacturing self-aligning planar two-gate MOS transistor on SOI substrate includes production of work and insulator regions of two-gate transistor on wafer surface, modification of hidden oxide, formation of tunnel in hidden oxide, formation of polysilicon gate and drain-source regions; upon formation of insulator and work regions; supporting mask layer is deposited onto substrate surface and ports are opened to gate regions to conduct ionic doping of hidden oxide with fluorine through them; then doped part of oxide under silicon is removed by selective etching to form tunnel in hidden oxide whereupon silicon surface is oxidized in open regions above tunnel and gate is formed; port in supporting layer and tunnel are filled with conductive material, and gate-source regions are produced upon etching supporting layer using gate as mask. Transistor structure channel length is up to 10 nm.
EFFECT: reduced length of transistor structure channel.
2 cl, 1 dwg
FIELD: physics.
SUBSTANCE: invention relates to semiconductor technology. The method of making power insulated-gate field-effect transistors involves making a protective coating with a top layer of silicon nitride on the face of the initial silicon nn+ or pp+ - substrate, opening windows in the protective coating, making channel regions of transistor cells in the high-resistivity layer of the substrate and heavily-doped by-pass layers and source regions inside the channel regions using ion implantation of doping impurities into the substrate through windows in the protective coating and subsequent diffusion distribution of implanted impurities. When making by-pass layers, the doping mixture is implanted into the substrate through windows in the protective coating without using additional masking layers. After diffusion redistribution of implanted impurities in by-pass layers on the entire perimetre of windows in the protective coating, selective underetching of lateral ends of the protective coating under silicon nitride is done. The silicon nitride layer is then removed from the entire face of the substrate and source regions of the transistor cells are formed through implantation of doping impurities into the substrate through windows in the protective coating.
EFFECT: invention is aimed at increasing avalanche break down energy, resistance to effect of ionising radiation and functional capabilities of silicon power transistors.
5 dwg, 1 tbl
FIELD: physics; semiconductors.
SUBSTANCE: invention concerns electronic semiconductor engineering. Essence of the invention consists in the manufacturing method of SHF powerful field LDMOS-transistors, including forming of a primary sheeting on a face sheet of an initial silicon body with top high-resistance and bottom high-alloy layers of the first type of conductance, opening of windows in a primary sheeting, sub-alloying of the revealed portions of silicon an impurity of the first type of conductance, cultivation of a thick field dielectric material on the sub-alloying silicon sites in windows of a primary sheeting thermal oxidising of silicon, creation in a high-resistance layer of a substrate in intervals between a thick field dielectric material of elementary transistor meshes with through diffused gate-source junctions generated by means of introduction of a dopant impurity of the first type of conductance in a substrate through windows preliminary opened in a sheeting and its subsequent diffused redistribution, forming of connecting busbars and contact islands of a drain and shutter of transistor structure on a thick field dielectric material on a face sheet of a substrate and the general source terminal of transistor structure on its back side, before silicon sub-alloying and cultivation of a thick field dielectric material in windows of a primary sheeting a high-resistance layer of a substrate is underetched on the depth equal 0.48 - 0.56 of thickness of a field dielectric material, and before dopant impurity introduction in the formed source crosspieces of transistor meshes in a high-resistance layer of a substrate in sheeting windows etch a channel with inclined lateral walls and a flat bottom depth of 1.5 - 2.6 microns.
EFFECT: improvement of electric parametres of SHF powerful silicon LDMOS transistors and increase of percentage output of the given products.
5 dwg, 2 tbl
FIELD: physics.
SUBSTANCE: in a field-effect transistor which includes an oxide film as a semiconductor layer, the oxide film has a channel part, a source part and a drain part, and concentration of one of hydrogen or deuterium in the source part and in the drain part exceeds that in the channel part.
EFFECT: invention enables to establish connection between the conducting channel of a transistor and each of sources and drain electrodes, thereby reducing change in parameters of the transistor.
9 cl, 13 dwg, 6 ex
FIELD: electricity.
SUBSTANCE: in manufacturing method of semiconductor device, which involves processes of ion implantation and formation of active areas of instrument on silicon substrate, after formation of active areas there created is hidden p-layer under channel of instrument by alloying of substrate with Be ions with energy of 125-175 keV, dose of (2-5)·1012 cm-2 and with further annealing at 650-750°C during 20-30 minutes and H2 atmosphere.
EFFECT: reducing leakage current values in semiconductor devices, providing processibility, improving parameters, reliability and increasing percentage yield.
FIELD: electricity.
SUBSTANCE: in the method for manufacturing of a semiconductor device including formation of a semiconductor substrate of the first type of conductivity, a gate electrode formed above a subgate dielectric and separated with interlayer and side insulation from a metal source electrode (emitter), a channel area of the second conductivity type and a source area of the first conductivity type, formed by serial ion alloying of admixtures into windows of the specified shape in the gate electrode, and the metal source electrode, a subgate dielectric is developed, as well as a gate electrode and interlayer insulation above the gate electrode in a single photplithographic process by plasma-chemical feeble anisotropic etching with ratio of vertical and horizontal components of etching speed making (3÷5)/1.
EFFECT: reduced resistance in open condition without increasing dimensions of a crystal and improved efficiency without deterioration of other characteristics.
11 cl, 4 dwg
FIELD: electricity.
SUBSTANCE: manufacturing method of SHF LDMOS transistors includes growth of thick field dielectric at surface of high-ohmic epitaxial p- -layer of source silicone p-p+-substrate at periphery of transistor configurations, formation of source p+-junctions and p-wells of transistor cells in epitaxial p- -layer of substrate not covered with field dielectric, growth of gate dielectric and formation of polysilicone electrodes of transistor cells gate in the form of narrow lengthwise teeth of rectangular section with close adjoining tapped contact pads from source side over p-wells, creation of high-alloy n+-areas of sink, source and low-alloy n-area of transistor cells by introduction and further diffusion redistribution of donor dopant using gate electrodes as protective mask, formation of metal electrodes of sinking, source, screens and buses shunting gate electrodes of transistor cells through tapped contact pads at substrate face and common metal source electrode of transistor configuration at backside, the first degree of low-alloy multistage n-area of transistor cell source is formed after formation of source p+-junctions by introduction of donor dopant to epitaxial p--layer of substrate without usage of protective masks, p-wells, sink and source areas of transistor cells are created with use of additional dielectric protective mask identical in configuration and location of lengthwise teeth of polysilicone gate electrode without tapped contact pads adjoining to them, simultaneously with p-wells similar areas are formed at edges of low-alloy n-area of transistor cells sink and gate electrodes with tapped contact pads adjoining to teeth are formed after removal of additional dielectric protective mask and subsequent growth of gate dielectric, at that width of polysilicone gate electrode teeth are selected so that it exceeds length of transistor cell induced channel per overlay error value.
EFFECT: improvement in electric parameters of powerful silicone generating SHF LDMOS transistors, increase of their resistance to ionising radiation exposure and increase of production output in percents.
7 dwg
FIELD: electricity.
SUBSTANCE: transistor based on a semiconductor compound comprises a semiconductor plate, a channel and a contact layers, ohmic contacts of a source and a drain, made on the basis of a thin-film compound of Ge and Cu, and a gate, where thin films of barrier-forming metal, a diffusion barrier and a conductor are installed in layers on a semiconductor plate. The gate conductor material is a thin-film compound of Ge and Cu with thickness of 10-1,000 nm, with mass content of Ge in the range of 20-45%.
EFFECT: higher thermal stability of gate parameters, lower value of reduced contact resistance of ohmic contacts of a source and a drain.
6 cl, 6 dwg, 1 tbl