Device for frame synchronization

 

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal. The technical result - synchronization of a class of transmission of information with asynchronous merging of digital streams with changing in the process, the length of the multiframe. For this purpose, in the device for frame synchronization, containing the first random access memory, a shift register, a decoder of synchronously, environment unit, generating equipment, device settings, entered the second memory device, the decoder control, trigger, divider, six inverters, seven elements And four elements OR. 3 Il.

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal.

The known device for frame synchronization [1-3], which contains the shift register, the detector clock cycle, the analyzer matches the clock (blocks retention and retrieval of synchronism), generating equipment, elements, AND, OR, the inputs and outputs of the device, soy is Euston to synchronize the various digital transmission with asynchronous merging of digital streams; the inability to synchronize the digital transmission, the length of the multiframe which is changed in the process; - significant hardware costs.

The closest to the technical nature of the claimed invention is selected as a prototype device for frame synchronization [4] , containing random access memory device, the device configuration and diagnostics, storage criteria of entry and exit out of synchronism, the decoder synchronously, environment unit, generating equipment, inputs and outputs of the devices that are connected in a certain way.

This device for frame synchronization allows you to synchronize the various transmission information Association with asynchronous digital stream having a constant length of the multiframe.

The disadvantage of this device is the inability to synchronize the class of digital transmission of information with a temporary seal, the structure of which consists of a cycle whose length (in bits) depends on the transmission speed, and super-frame, the length of which is changed in the process. Analysis of the structure of this class shows that the loop contains the service group of bits, in which n is their channels).

The cycle length of this class of digital transmission of information equal to VN, where V is the transmission rate (Kbit/s); N is a constant number for a specific group of transmission.

An object of the invention is enhanced functionality, allowing synchronization of the various transmission information is changing the process, the length of the multiframe.

This task is solved in that the device for frame synchronization (CA), containing the first random access memory (RAM), a shift register (PC), the decoder synchronously (DS), environment unit (FU), generating equipment (TH), device settings (UN), and the clock input devices for frame synchronization (CA) is connected to the corresponding inputs PC and TH, an information input device for the CA is connected with the respective input PC, 0-N, the outputs of which are connected with information 0-N inputs DC the output response which is connected with the respective input FU, the first 0-N and the second 0-N specifies the inputs of which are connected respectively with the fifths 0-N and sixth 0-N specifies the outputs of the UNIVERSITY, the output of the availability of synchronization FU is the corresponding output device for the CA, the first 0-N address vijayta for CA second 0-N address outputs TH are second 0-N address outputs of the device for the CA, the input/output end of the cycle of the first RAM is connected with the corresponding input/output of the UNIVERSITY, with the appropriate input and an output end of the cycle the device for the CA inputs write, read and select the first RAM connected to respective outputs of the UNIVERSITY, the input mode selection, new address, set to zero, write, read, set the RAM or register memory selecting a custom RAM and information 0-N inputs/outputs which are the corresponding inputs of the device for the CA, the input mode selection the UNIVERSITY also connected with the respective input, input cycles settings and the first input set to the initial state of which is connected with the corresponding outputs of the UNIVERSITY, according to the invention introduced the second RAM, the decoder control (RMC), trigger factor, from first to sixth inverters, with the first seven elements And first to fourth elements OR, and inputs the read, write, and selecting the second RAM connected to respective outputs of the UNIVERSITY, 0-N address inputs of the second RAM is connected with the second address outputs, the input/output end of the multiframe of the second RAM is connected with the corresponding input/output of the UNIVERSITY and/outlet UNIVERSITY and third inputs of the first and second elements, And the outputs of which are connected respectively with the first and second inputs of the first element OR the third input connected to the output of the third element, And output to the clock input FU, the zero output state of which is connected to the input of the third inverter, the third input of the third element And to the first input of the sixth element And a second input of the third element OR the output of which is connected to the first input of the fifth element And the second input and the third input of the sixth element And is connected to the input of the mode selection device for the CA, the maximum output state FU is connected to the input of the fourth inverter, the output of which is connected to the fifth input of the second element And the exit criteria exit synchronism FU connected with the allow logon trigger, the output of which is connected with the allow input of the divider, the input of the sixth inverter, a first input of the third element OR and M entrance FU, the output of the availability of synchronization FU connected to the first input of the fourth element And a second input connected to the output of the first element, And its output to the input of the fifth inverter, the output of which is connected to a clock input of the trigger information input trigger is connected to the power bus, and the input set to zero - the output of vtoro the ol FU - with the release of the seventh element And the first input connected to the output of the divider and the second input and the first inputs of the first, second and third elements And is connected to the output of the first inverter, an input connected to a clock input of the device for the CA, the input set to zero divider connected to the output of the second element OR the first 0-N and the second 0-N specifies the outputs of the UNIVERSITY are connected respectively with the first 0-N and the second 0-N specifies inputs DC output response which is connected to the fourth input of the second element, And with a second input of the third element And to the input of the second inverter, the output of which is connected to the fourth input of the first element And 0 third-and fourth N 0-N specifies the outputs of the UNIVERSITY are connected respectively with the first 0-N and the second 0-N specifies the control inputs, the output response which is connected with the corresponding input is ON, seventh 0-N specifies the outputs of the UNIVERSITY are connected respectively with 0-N specifies the inputs of the divider, a clock input, and the second inputs of the first and second elements And is connected to the output end of the cycle of the first RAM, the output of the fifth element And connected to the first input of the fourth element OR a second input connected to the output setting in the initial state UNIVERSITY, and the output from the second input usta element And, a second input connected to the output of the sixth inverter, the output of the third inverter is connected to the fifth input of the first element And 0-N outputs PC connected to respective information input control.

The novelty of technical solutions is available in the claimed device new circuit elements: a second memory device, the decoder control, trigger, divider, from first to sixth inverters from the first to the seventh element, And first to fourth elements OR.

Thus, the invention meets the criterion of "novelty."

Analysis of the known technical solutions in the study and related fields allows us to conclude that the introduced functional units known. However, their introduction into the device for frame synchronization with the above links gives it new properties. Introduced functional units interact in such a way that allow you to extend its functionality, providing synchronization of a wide class of gear changing in the process, the length of the multiframe.

Thus, the invention meets the criterion of "Inventive step", as it is for the expert is not obvious from the prior art is the application of digital streams.

Thus, the invention meets the criterion of "Industrial applicability".

In Fig.1 shows a structural electrical diagram of the device for frame synchronization, Fig.2 is an electrical diagram of the generating equipment of Fig.3 - structure of digital transmission.

Device for frame synchronization (Fig.1) contains the first random access memory (RAM) 1, the shift register (PC) 2, the decoder synchronously (DS) 3, environment unit (FU) 4, generating equipment (TH) 5, device settings (UN) 6, the second RAM 7, the decoder control (RMC) 8, the trigger 9, the divider 10, from first to sixth inverters 11, 12, 13, 14, 15, 16, from first to seventh elements 17, 18, 19, 20, 21, 22, 23 and first to fourth elements ILI, 25, 26, 27, and clock input (input T) devices for the CA is connected to the corresponding inputs of the PC 2 and 5, data input (input) device for the CA is connected with the corresponding input of the PC 2, 0-N, the outputs of which are connected with information 0-N inputs DC 3, the output response which is connected with the respective input FU 4, the first 0-N and the second 0-N specifies the inputs of which are connected respectively with the fifths 0-N and sixth 0-N specifies the outputs of SCIENCES 6, the presence of synchronization FU 4 t the address inputs of the first RAM 1 and are the first address output unit for CA second 0-N address outputs TH 5 are second 0-N address outputs of the device for the CA, the input/output end of the first cycle of the RAM 1 is connected with the corresponding input/output of SCIENCES 6, with the respective input TH 5 and an output end of the cycle the device for the CA inputs write, read and select the first RAM 1 is connected with the corresponding outputs of SCIENCES 6, the input mode selection, new address, set to zero, write, read, set the RAM or register memory selecting a custom RAM and information 0-N inputs/outputs which are the corresponding inputs of the device for the CA, the input mode selection UNIVERSITY 6 is connected with the respective input TH 5 input clock cycles settings and the first input set to the initial state of which is connected with the corresponding outputs of SCIENCES 6, the inputs are read, write, and selecting the second RAM 7 is connected with the corresponding outputs of SCIENCES 6, 0-N address inputs of the second RAM 7 is connected with the second address outputs TH 5, the input/output end of the second multiframe RAM 7 is connected with the corresponding input/output UN 6 and the respective input TH 5, the input/output end of synchronously second RAM 7 is connected with the corresponding input/ output UN 6 and third inputs of the first and second elements 17, 18, is connected to the output of the third element 19, and the output with a clock input FU 4, the zero output state of which is connected to the input of the third inverter 13, with the third input of the third element 19, to the first input of the sixth element I and a second input of the third element ILI, the output of which is connected to the first input of the fifth element I, the second input and the third input of the sixth element E connected to the input of the mode selection device for the CA, the maximum output state FU 4 is connected to the input of the fourth inverter 14, the output of which is connected to the fifth input of the second element I, exit criteria exit synchronism FU 4 is connected with the allow logon trigger 9, the output of which is connected with the allow input of the divider 10, the input of the sixth inverter 16, the first input of the third element ILY and M entrance FU 4, the output of the availability of synchronization FU 4 connected to the first input of the fourth element I, a second input connected to the output of the first element 17 and its output to the input of the fifth inverter 15, the output of which is connected to a clock input of the trigger 9, the information input of the trigger 9 is connected to the power bus, and the input set to zero with the output of the second element ILI, the first input connected to the output of the second element I, and the second input and the input set to zero FU 4 - with the e inputs of the first, the second and third elements 17, 18 and 19 connected to the output of the first inverter 11, an input connected to a clock input T of the device for the CA, the input set to zero divider 10 is connected to the output of the second element ILI, the first 0-N and the second 0-N specifies the outputs of SCIENCES 6 are connected respectively with the first 0-N and the second 0-N specifies inputs DC 3, the output response of which is connected to the fourth input of the second element I, with a second input of the third element 19 and to the input of the second inverter 12, the output of which is connected to the fourth input of the first element 17, 0 third-and fourth N 0-N specifies the outputs of SCIENCES 6 are connected respectively with the first 0-N and the second 0-N specifies the inputs DN 8, the output response which is connected with the respective input TH 5, seventh 0-N specifies the outputs of SCIENCES 6 are connected respectively with 0-N specifies the inputs of the divider 10, a clock input, and the second inputs of the first and second elements 17 and 18 are connected with the output end of the first cycle of the RAM 1, the output of the fifth element I connected to the first input of the fourth element ILI, a second input connected to the output setting in the initial state UNIVERSITY 6, and the output from the second input set to the initial state RD 5, the third input set to the initial state which seedio inverter 13 is connected to the fifth input of the first element 17, 0-N outputs of the PC 2 are connected to the appropriate information inputs DN 8.

Generating equipment 5 (Fig. 2) contains the count cycle length is 28, the counter length of the multiframe 29, remover signals 30, inverters 31, 32 and 33, the elements I, 35, 36, 37, 38, 39 and 40, the elements ILI and 42, and a clock input (input T) TH 5 connected to the first input element I, with a clock input (input T) remover signals 30 and the input of the inverter 32, the output of which is connected to the first input element I, a second input which is the input of the response (input) TH 5, input clock cycles settings (log T) TH 5 is connected with the first inputs of the elements I and 39, the inlet end of the cycle (log CS) TH 5 is connected with the second input element I, the third input element I and the input end of cycles (log CP) remover signals 30, the control input (gate) of which is connected with the output element I, and the output of the CC of the remover signals 30 connected to the first input element I, select input mode (input MODE) TH 5 connected to the inputs of the inverters 31 and 33, the second inputs of the elements I, 38 and to the first inputs of the elements I, 40, the inlet end of the multiframe (input KSC) TH 5 is connected with the second input element I, the output of which is connected to the input of synchronous setup to zero (sign-R1) meter length of the multiframe 29, asynchronous input ustanovka T - with the output element ILI, address 0-N outputs of the counter length of the multiframe 29 is connected with the second address 0-N outputs TH 5, the output of the inverter 31 is connected with the second input element I, the output of which is connected with the second input element ILI, the first input connected to the output element I and the output with a clock input (input T) counter cycle lengths 28, the input asynchronously set to zero (sign-R1) which is connected to the first input set to the initial state (input RES1) TH 5, the synchronous input setup to zero (log R2) - output element I, and the input set to the maximum condition (input R3) - with the third input set to the initial state (input RES3) TH 5, address 0-N outputs of the counter length of the loop 28 is connected with the first 0-N address outputs TH 5, the output element E connected to the first input element ILI, a second input connected to the output element I, a second input connected to the output of the inverter 33.

Device for frame synchronization works as follows. Device for the CA has two modes of operation. The first mode of operation and diagnosis, the second mode of operation. In the first mode, the input device for the CA and then to the inputs of SCIENCES 6 with a controller that works in conjunction with the personal electronic count is ON), installation to zero (input RES), write (log CE), read (input OE), set the RAM or register recall (input RAM/RG), non configurable RAM (input RAM), information (inputs/outputs 0-N). The select signal also is fed to the input DIR TH 5, to the second input of the fifth element I and to the third input of the sixth element I.

When setting the RAM to the input RAM/RG UNIVERSITY 6 signal "Log.1".

Used in the device for the CA RAM have 0-N address inputs, a selection input (CE input), input recording (input WE, input read (input OE) and information inputs/outputs. Allow the RAM is carried out in the presence of the signal Log. 0" on its CE input. Recording information on the information inputs/outputs of RAM, is if WE can control the input Log.0", and the SECOND input signal Log. 1". Reading the information stored in RAM is carried out in the presence of the SECOND input signal Log.0", and the WE input signal Log.1".

In the first RAM 1 is memorized position of the end of the cycle (input/output CC).

In the second RAM 7 remember the following parameters digital transmission: - the end of the multiframe (input/output KSC); - end synchronously (input/output CSC). The end of synchronously - cycle number in the multiframe, where is singlecompany.

Before the crust is the setting signal to zero, received from the output of SCIENCES 6 (output RES) on the input set to zero (input RES1) TH 5, counter end loop 28 and the counter end of the multiframe 29 TH 5 are set in the zero state.

On the setup time of the first RAM 1 input select custom RAM (input RAM) UNIVERSITY 6 signal Log.0". When this signal is "Log.0", coming from SE exit UNIVERSITY 6 input selection SE first RAM 1, allowed the use of the latter, and the signal Log.1" coming from SE exit UNIVERSITY 6 CE input selecting the second RAM 7, prohibited his work. Information 0-N input/output device for the CA and then to the respective inputs/outputs of the UNIVERSITY 6 receives information signals settings. When this signal the end of the cycle with entry/exit CC UNIVERSITY 6 is supplied to the corresponding input/output of the first RAM 1.

Further according to the recording signal, WE arrived at the entrance of the University of 6 and then WE exit UNIVERSITY 6 WE input the first RAM 1, the last address corresponding to the zero state of the counter cycle length 28 TH 5, memorize the information received on the input/output of the first RAM 1. Then, on the information 0-N I/o UNIVERSITY 6 receives new configuration data, and the input ON UNIVERSITY 6 - the signal new address, which is the quantum setting. This tact settings received from the output of SCIENCES 6 (you>/p>Further, as described above, in the first RAM 1 is memorized information at the address corresponding to the counter state cycle lengths 28 TH 5.

After setting up the first RAM 1 setting set the parameters of the second RAM 7. At this, all the setup time of the second RAM 7 to the input of non configurable RAM (input RAM) UNIVERSITY 6 signal Log.1". When this signal is "Log. 0", coming from SE exit UNIVERSITY 6 input selection SE second RAM 7 is allowed the use of the latter, and the signal Log.1" coming from SE exit UNIVERSITY 6 SE the selection input of the first RAM 1, prohibited his work. Address 0-N inputs of the second RAM 7 is connected with the second address 0-N outputs TH 5. The second address 0-N outputs TH 5 are connected to the address outputs of the counter length of the multiframe 29. As described above, before setting up the second RAM 7 meter length of the multiframe 29 TH 5 set to the zero state. When configuring a clock signal for counter multiframe 29 TH 5 are signals coming from the output VT of the University of 6 on the appropriate input TH 5. The setup procedure of the second RAM 7 is the same as the first RAM 1. In the second RAM 7 memorized signals the end of the multiframe and the end of synchronously coming respectively from the input/output KSC and input/output stewards of the University of the Oia UNIVERSITY 6 (input OE) signal "Log.1". When this signal is "Log.1" from the output reading UNIVERSITY 6 (output OE) arrives at the inputs of TH first 1 and second RAM 7.

To determine the correct configuration of RAM on the WE input recording UNIV 6 and next to the appropriate input of the first 1 and the second RAM 7 is supplied to the signal Log. 1". Then, as described above, select the number of configurable RAM, a setting signal to zero the counters of the end of the loop 28 and the end of the multiframe 29 TH 5 are set in the zero state, the signal Log.0", piped reading TH UN 6 and then with the corresponding output of the UNIVERSITY 6 the inputs of the SECOND reading of RAM, the information recorded in the RAM, with its inputs/outputs are fed to respective inputs/outputs of the University of 6 further information 0-N/o UNIVERSITY 6 through 0-N input/output device for the CA - PC. Then signal a new address, which counters the end of the loop 28 and the end of the multiframe 29 TH 5 are installed in the next state, and information is again read from the RAM and comes into the PC, as described above.

In the PC the information read from the RAM is compared with the original and the result of the comparison is displayed on the display.

After setting the RAM is set up the registers of the memory located at the UNIVERSITY 6. At this, all the time settings Regis is determining the correct configuration registers storing the UNIVERSITY 6 the same, when configuring RAM.

When applying for UNIVERSITY entrance 6 setting signal to zero RES selects the first register storing the UNIVERSITY 6. Change custom register memory by a signal of a new address received at the corresponding input of the UNIVERSITY 6.

In the registers of the memory stores the following parameters: - position synchronously in the service group specified by the signals coming from the first 0-N specifies the outputs of SCIENCES 6 on the first 0-N specifies the inputs DS 3, and if the position refers to the position of synchronously, it is set by the signal Log.1";
values of the positions of synchronously specified by the signals coming from the second 0-N specifies the outputs of SCIENCES 6 on the second specifies 0-N inputs DS 3;
position signals to control the length of the multiframe in the service group specified by the signals coming from the third 0-N specifies the outputs of SCIENCES 6 on the first 0-N specifies the inputs DN 8;
values of positions to control the length of the multiframe defined by the signals from the fourth 0-N specifies the outputs of SCIENCES 6 second 0-N specifies the inputs DN 8;
- entrance criteria in synchronism set by signals from the fifth 0-N specifies the outputs of SCIENCES 6 on the first 0-N specifies the inputs FU 4;
- exit criteria from synchronism, set the division factor, asked by signals from the seventh 0-N specifies the outputs of SCIENCES 6 0-N specifies the inputs of the divider 10.

After the implementation of the device for the CA mode. The translation mode is performed when a signal "Log. 1" from the controller PC to the input DIR devices for CA.

When this is done the following:
the first 1 and the second RAM 7 are set in the read mode, since the respective outputs of the UNIVERSITY on 6 selects SE and SE, to the inputs of the read SECOND RAM signal Log.0", and the inputs WE write signal "Log.4";
- inputs/outputs CC, CSC, CSC UNIVERSITY 6 are set to the third state;
- prohibited the formation of the signals at the outputs T and RES UNIV 6;
- allowed the fifth element I and the sixth element I.

When the data and clock signals, respectively, with inputs And T device for the CA act to corresponding inputs of a PC 2. Signals with 0-N outputs PC 2 receives on the corresponding 0-N informational inputs DC 3 0 N informational inputs DN 8.

When deciphering synchronously output response DS 3, you may receive the signal Log.1". Each occurrence of a positive response to the output control 8 indicates the change in the length of the multiframe on one cycle. The signal response from filament 17, the fourth input of the second element I and to the second input of the third element 19. Until the DC output 3 of the first signal positive response FU 4 is in the zero state. When this signal is "Log. 1" at the output of the zero state (output DC "0") performs the following:
through the third inverter 13 prohibits the fifth input of the first element 17, thereby prohibited from forming at the output of the clock signal passing through the first element ILI on the clock input (input T) FU 4, and thus forbidden transition FU 4 from the zero state to the maximum;
- opens on to a third input of the third element 19, thereby allowing the formation of its output clock signal through the first element ILI on the clock input FU 4;
- proceeding through the third element ILI, then through the open second input of the fifth element I and then through the fourth element ILI to the second input set to the initial state (input RES2) TH 5, holds the multiframe counter 29 in the zero state;
- doing an open on the second and third inputs of the sixth element I to the third input set to the initial state (input RES3) TH 5, holds the loop counter 28 last in the maximum condition on the Signals from the address outputs of the counter cycle length 28 through the first 0-N address outputs TH 5 arrive at the corresponding address inputs of the first RAM 1.

The signals from the address outputs of the counter length of the multiframe 29 through the second 0-N address outputs TH 5 arrive at the corresponding address inputs of the second RAM 7.

The first signal of a positive response to the output DC 3 sets FU 4 in the positive mode account and enables the second input of the third element 19. Now the signal from the clock input devices for CA, proceeding through the first inverter 11, the third element 19 and the first element ILI on the clock input FU 4, increases its status on the unit. Then on the DC output "0" FU 4, you may receive the signal Log.0", which enables the first element 17, prohibits the third element 19, the fifth element I and the sixth element I. When this signal is "Log.0", coming from the output of the fifth element I through the fourth element ILI input RES2 TH 5 meter length of the multiframe 29 the latter starts counting mode, and the signal Log.0", coming from the output of the sixth element I input RES3 TH 5, mode account means the length counter loop end 28 TH 5.

When a signal of the end loop from the output CP of the first RAM 1 on the appropriate input TH 5 meter length of cycle 28 last on the next clock signal from clock input devices for the CA to the zero state after receiving a signal of the end of the multiframe output KSC second RAM 7 to the appropriate input TH 5. The clock frequency of the counter length of the multiframe 29 is formed when a signal of the end of the cycle to the input of TH 5. Upon receipt of a positive signal response output DN 8 to the corresponding input of the TH 5 and further to the entrance of his remover signal 30 last prohibits the passage of the next signal the end of the cycle to the clock input of the counter length of the multiframe 29 TH 5. Thus, each occurrence of a positive response to the output control 8 leads to an increase in the length of the multiframe on one cycle. After you receive the first signal response at the output of the DS-3 the formation of the clock signals at the clock input FU 4, by using the first and second elements 17, I. The output of the first element 17 is formed by a clock signal at a negative signal response at the output of the DS-3, and the output of the second element I - if a positive signal response. The formation of the clock signals at the outputs of the first and second elements 17, I is the coincidence in time of the signal of the end of the cycle, coming from the output of the CC of the first RAM 1 at a second input elements 17, I, and signal the end of synchronously coming from the CSC output of the second RAM 7 to the third inputs of the elements 17, I. In this case, the signal from the clock input devices DL the entrance FU 4, increases or decreases its state unit. The increase in state per unit is performed when the signal of the positive feedback input FU 4, and the reduction state of the unit when the signal of the negative response to his input.

When the difference in the number of signals of positive and negative response to the output DC 3 reaches the criterion value input in synchronism specified by signals from the fifth 0-N specifies the outputs of SCIENCES 6 on the first 0-N specifies the inputs FU 4, the latter is set in the maximum condition and device for the CA enters the hold of synchronism, as evidenced by the signal Log.1" at the output of the availability of synchronization (exit f) FU 4. When FU 4 in maximum condition signal maximum state FU 4, coming from the DC output "1" FU 4 via the fourth inverter 14 to the fifth input of the second element I, is prohibited. Thus it is prohibited to transfer FU 4 from the maximum condition in the minimum.

In the result of interference you may encounter the following situation:
the emergence of inserts and deposition, i.e., the appearance of false clock signals or their disappearance. In this case, the device for the CA out of synchronism and again it starts the Ko.

- distortion of synchronously;
the distortion of the information on the positions to control the length of the multiframe.

Depending on the noise immunity of the communication line is selected criteria of entry and exit of synchronism, which reduces the probability of matching devices for the CA when the distortion of synchronously.

Falsification of information on the positions to control the length of the multiframe can lead to a false change in the length of the multiframe or to maintain the same length if necessary changes.

In these situations, when the interference device for the CA works as follows. When the difference in the number of signals of negative and positive output DC 3 reaches the criterion value output from the synchronism specified by the signals from the sixth 0-N specifies the outputs of SCIENCES 6 second 0-N specifies the inputs FU 4, the output KB last receive a signal Log. 1, which, on entering EU input trigger 9, allows his work. Signal the presence of synchronism with output f FU permit the first input of the fourth element I. Now, when a negative signal response at the output of the DS-3 clock signal output from the first element 17 is supplied through the open fourth e is the output signal, coming to EU input of the divider 10, allowing his work. The output signal of the trigger 9 through the third element ILI through the fifth element I and the fourth element ILI is fed to the input RES2 TH 5, holding the counter length of the multiframe 29 last in the zero state. A clock signal divider 10 are signals the end of the cycle, coming from the output of the CC of the first RAM 1 at the input To the divider 10. The divider 10 is set by signals from the seventh 0-N outputs of the University of 6 to corresponding inputs of a divider 10. The divider 10 is selected depending on the length of the multiframe transmission and noise immunity of the communication line. If during operation of the divider 10 is not formed any positive signal response at the output of the DC 3, the output signal of the divider 10 allows the first input of the seventh element I. Then, when receiving the clock signal output from the first inverter 11 to the second input of the seventh element I, the output signal from the last received on the input set to zero FU 4 and through the second element ILI on the input set to zero divider 10 and the input set to zero trigger 9, FU 4, the divider 10 and the trigger 9 is set in the zero state. Device for the CA when it again moves in the positive response to the output DC 3, the signal generated at the output of the second element I received through the second element ILI on the inputs installed in the zero trigger 9 and divider 10, last set to the zero state. Also the signal received from the output of the second element I through the first element ILI on the clock input FU 4, the latter is set in the maximum state, because the input M FU with 4 trigger 9 received signal Log.1". Device for the CA, in walked the signal Log.1". Device for the CA, in this case, will continue to hold synchronism.

Generating equipment operates as follows. In the mode setting device for the CA to the input DIR generating equipment 5 (TH) on all the time setting signal "Log.0", prohibiting the operation of the elements I, I, I, I and through inverters 31, 33 allowing the work items I, I. That would allow the passage of signals from input clock cycles settings T TH 5 at the clock inputs of the counter cycle lengths 28 and the counter length of the multiframe 29 and prohibits the passage:
- clock signals from the clock input T TH 5 at the clock input T of the counter cycle lengths 28;
signals from the input end of the cycle (log CS) TH 5 on the input set to zero (log R2) of the counter cycle lengths 28;
signals the end of the cycle (output CC) with you is a (log KSC) TH 5 to the input of synchronous setup to zero (sign-R1) meter length of the multiframe 29.

Then at the signal input asynchronously set to zero RES1 TH 5 meter length of the loop 28 is set in the zero state, and the signal input asynchronously set to zero RES2 TH 5 in the zero state is set, the counter length of the multiframe 29. Then the ticks setting input T TH 5 are received at the clock inputs of the counter cycle lengths 28 and the counter length of the multiframe 29, changing their addresses.

In the operation mode input DIR TH 5 signal Log.0" is changed to the signal Log. 1", thereby allowing the operation of the elements I, I, I, I, and, through the inverters 31, 33, prohibiting the operation of the elements I, I. It is prohibited the passage of signals from input clock cycles settings T TH 5 at the clock inputs of the counter cycle lengths 28 and the counter length of the multiframe 29 and permitted the passage:
- clock signals from the clock input T TH 5 at the clock input T of the counter cycle lengths 28;
signals from input CC TH 5 input R2 of the counter cycle lengths 28;
signals from the output of the remover signals 30 to the clock input of the counter length of the multiframe 29;
signals from input KSC TH 5 to the input of synchronous setup to zero R1 counter the length of the multiframe 29.

When working, while FU 4 is in the zero state, the input set to the maximum condition (input R3) meter length.1". While the counter length of the loop 28 is held in the maximum condition, and the counter length of the multiframe 29 is held in the zero state. In the process of finding synchronism with the transition FU 4 from zero in any other state at the inputs of R1, R3 counter cycle length 28 TH 5 and to the input of R2 counter the length of the multiframe 29 TH 5 receives signals "Log.0", allowing their work. When the counter reaches the length of the loop 28 position corresponding to the length of a given cycle length, according to the signal received from input CC TH 5 through the open element I input R2 of the counter cycle lengths 28, the latter following a clock pulse received at its input T, set to the zero state. In the process, a clock signal of the counter length of the multiframe 29 signals the end of the cycle, coming from the output of CC of remover signal 30 through the element I and element ILI to the input T of the counter length of the multiframe 29. When the counter reaches the length of the multiframe 29 location corresponding to a given length of the multiframe signal received from input KSC TH 5 through the open element I input R1 of the counter length of the multiframe 29, the latter as a clock signal set to the zero state. Remover signals 30 performs the prohibition of passing sigilla, coming respectively with inputs and CC TH 5 through the element I to the input of the remover signals 30.

For the technical realization of the device for frame synchronization used static random access memory (RAM) imported type KM68257CJ-15 - company SEC and user-programmable logical integrated circuit (PPLIS) HSA - by XILINX.

The present invention enables synchronization of a class of transmission of information with asynchronous merging of digital streams with changing the length of the multiframe.

Sources of information
1. RF patent 2019046, CL H 04 L 7/08, 30.08.1994.

2. RF patent 2136111, CL H 04 L 7/08, 27.08.1999.

3. Levin, L. S., Plotkin, M. A. Digital communication system. M.: Radio and communication, 1982, S. 102, 103, Fig. 4.4.

4. Application EN 2000105720, CL H 04 L 7/08, publ. 27.01.2002.


Claims

Device for frame synchronization, containing the first random access memory (RAM), a shift register (RS) decoder of synchronously (DS), environment unit (FU), generating equipment (TH), device settings (UN), and the clock input devices for frame synchronization (CA) is connected to the corresponding inputs of the RS & E information 0-N inputs DC the output response which is connected with the respective input FU, the first 0-N and the second 0-N specifies the inputs of which are connected respectively with the fifths 0-N and sixth 0-N specifies the outputs of the UNIVERSITY, the output of the availability of synchronization FU is the corresponding output device for the CA, the first 0-N address outputs TH connected to respective address inputs of the first RAM and are the first address output device for the CA, the second 0-N address outputs TH are second 0-N address outputs of the device for the CA, the input/output end of the cycle of the first RAM is connected with the corresponding input/output of the UNIVERSITY, with the appropriate input and an output end of the cycle the device for the CA inputs write, read and select the first RAM connected to respective outputs of the UNIVERSITY, the input mode selection, new address, set to zero, write, read, set the RAM or register remember, selecting a custom RAM and information 0-N inputs/outputs which are the corresponding inputs of the device for the CA, the input mode selection the UNIVERSITY also connected with the respective input, input clock cycles settings and the first input set to the initial state of which is connected with the corresponding outputs of the UNIVERSITY, characterized in that it introduced the ways And and first to fourth elements OR moreover, the inputs are read, write, and selecting the second RAM connected to respective outputs of the UN, 0-N address inputs of the second RAM is connected with the second address outputs, the input/output end of the multiframe of the second RAM is connected with the corresponding input/output of the UNIVERSITY and the respective input, the input/output end of synchronously second RAM is connected with the corresponding input/output of the UNIVERSITY and third inputs of the first and second elements And the outputs of which are connected respectively with the first and second inputs of the first element OR the third input connected to the output of the third element And and the output clock input HOLD, the zero output state of which is connected to the input of the third inverter, the third input of the third element And to the first input of the sixth element And a second input of the third element OR the output of which is connected to the first input of the fifth element And the second input and the third input of the sixth element And is connected to the input of the mode selection device for the CA, the maximum output state FU is connected to the input of the fourth inverter, the output of which is connected to the fifth input of the second element And the exit criteria exit synchronism FU connected with the allow logon trigger the output of which is connected to allow the I sync FU connected to the first input of the fourth element, And a second input connected to the output of the first element, And its output to the input of the fifth inverter, the output of which is connected to a clock input of the trigger information input trigger is connected to the power bus, and the input set to zero with the output of the second element OR the first input connected to the output of the second element, And the second input and the input set to zero FU - with the release of the seventh element And the first input connected to the output of the divider and the second input and the first inputs of the first, the second and third elements And is connected to the output of the first inverter, an input connected to a clock input of the device for the CA, the input set to zero divider connected to the output of the second element OR the first 0-N and the second 0-N specifies the outputs of the UNIVERSITY are connected respectively with the first 0-N and the second 0-N specifies inputs DC output response which is connected to the fourth input of the second element And with a second input of the third element And to the input of the second inverter, the output of which is connected to the fourth input of the first element And third 0-and fourth N 0-N specifies the outputs of the UNIVERSITY are connected respectively with the first 0-N and the second 0-N specifies the control inputs, the output response which is connected with the corresponding input is ON, seventh 0-N specifies Wii first and second elements And is connected to the output end of the cycle of the first RAM, the output of the fifth element And connected to the first input of the fourth element OR a second input connected to the output setting in the initial state UNIVERSITY, and the output from the second input set to the initial state, the third input set to the initial state of which is connected to the output of the sixth element And a second input connected to the output of the sixth inverter, the output of the third inverter is connected to the fifth input of the first element And 0-N outputs the PC connected to the appropriate information inputs do.

 

Same patents:

The invention relates to a method of transmitting digital data and can be used for frame synchronization in systems robust data protection with application of the adjustment, in particular, concatenated codes

The invention relates to the transmission of discrete information and can be used for frame synchronization in systems robust protection using corrective, in particular concatenated codes

The invention relates to systems for the transmission of discrete data and can be used for frame synchronization in systems robust data protection that apply corrective, in particular concatenated codes

Device sync cycles // 2192711
The invention relates to communication technology and can be used for receiving data from a downhole telemetry system using looped packets of digital data

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal

The invention relates to techniques for digital communication, namely, devices frame synchronization in digital transmission systems with a temporary seal

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital transmission systems with a temporary seal

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

1 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg

Up!