The erase mode page in the matrix flash memory

 

The invention relates to the erase mode in the matrix of flash memory. The technical result is a significant decrease in excitation is not selected for erasing memory cells in erasing the selected memory cells. The device matrix flash memory contains many transistors of the memory cells, means for supplying a first voltage to a control gate of at least one transistor in the erased cells of said memory, means for supplying a second voltage, more positive than the first voltage, to the control gates of all the transistors of the cells mentioned memory, other than those referred to at least one transistor in the erased cells of said memory, means for supplying a third voltage that is more positive than said second voltage, a drain mentioned at least one transistor in the erased cells referred to memory and to the drains of the mentioned transistors is not erasable memory cells. Methods describe the operation of the specified device. 3 S. and 11 C.p. f-crystals, 4 Il.

The technical field to which the invention relates the Present invention relates to the erase mode in the matrix of flash memory. More specifically, the present isoretinoin techniques In traditional matrix flash memory matrix flash memory is typically arranged as a matrix of lines, words and bit lines to form intersections with elements of flash memory, located at the intersection method, well known to specialists in this field of technology. Operations that can be performed on the memory cells in a matrix of flash memory are reading, programming and erasing.

Program operation is often performed by excitation of the selected bit lines connected to the drain region in the cells of a flash memory, to the first voltage and the excitation of the closures of the cells of a flash memory connected to the selected lines of words, to a higher voltage to run the injection of hot electrons by the way, is well known to specialists in this field of technology.

The erase operation is performed by the excitation shutter cell flash memory to a voltage that is substantially less than the voltage established on the bit line. When doing this, the electrons tunnel from the free shutter cell flash memory method, well known to specialists in this field of technology. For traditional matrices flash memory is known that either the whole matrix of flash memory can be erased at a time when the so-called total erase or sector in a matrix of flash memory can be erased at a time when the so-called erasing sector. An example of Thoth who ence on solid state circuits Institute of electrical and electronics engineers, pages 140 and 141, February 1989, an Example of the erase sector are presented in the article "A 55ns 0,35 m 5V Only 16M Flash Memory with Deep-Power-Down", 1996 international conference on solid-state circuits Institute of electrical and electronics engineers, pages 44 and 45, February 1996,

The limitation of the operation of erasing or erase sector or total Erasure is performed in consideration of the fact that, when separate line number are selected for erase, there is a possibility that the value stored in the floating gate cell flash memory for non-selected rows will be affected due to the presence of unintentional tunneling. Thus, the aim of the present invention is the provision of the erase mode, in which only one row in the sector or multiple rows in the sector can be erased at the same time, reducing the phenomenon of excitation of the cells of the flash memory sector that is not selected.

Summary of the invention In accordance with the first aspect of the present invention, the operation mode erase page is provided for the sector in a matrix of flash memory. In the operation mode erase page preferred voltage tunneling approximately -10 V is applied to the gates of the cells of the flash memory in a row, liberibacter voltage approximately 6.5 volts (V). To reduce unintentional erasing of the memory cells in the rows other than the selected row, the preferred bias voltage of approximately 1 to 2 V is applied to the gates of all cells in the flash memory in the rows other than the selected row.

In accordance with the second aspect of the present invention is provided an erasing mode multiple pages. In erase mode multiple pages ranks in the sector are divided into groups, and more than one row in the group is selected for erase or corresponding rows in different groups are selected for Erasure. In erase mode multiple pages preferred voltage tunneling approximately -10 V is applied to the gates of the cells of the flash memory in the rows selected for erase, and bit lines connected to drains of the cells in the flash memory, are excited to a preferred voltage of approximately 6.5 Century To reduce the presence of unintentional erasing of the cells of the flash memory in rows that are not selected, the preferred bias voltage of approximately 1 to 2 V is applied to the gates of the cells of the flash memory in rows that are not selected for Erasure.

A brief description of the accompanying drawings Fig. 1 illustrates a block diagram of the matrix PL is in the matrix flash memory of Fig. 1 in accordance with the present invention.

Fig. 3 illustrates a table of the signals supplied to the elements in the sector illustrated in Fig. 2, for reading, programming and erasing of the page matrix of flash memory, in accordance with the present invention.

Fig. 4 illustrates a schematic diagram of the alternating reference signal, suitable for use in accordance with the present invention.

A detailed description of the preferred variant embodiment of the invention, the Specialists in the art will understand that the following description of the present invention is only illustrative and in no way limiting of the scope of patent protection. Other variants of embodiment of the invention will be easily understood by professionals.

In Fig. 1 illustrates the matrix 10 flash memory in accordance with the present invention. Matrix 10 flash memory has M rows, where each row has N bytes. Each of the M rows in the matrix 10 flash memory is usually called the page memory. In the matrix 10 flash memory data M rows are grouped into sectors or blocks the way, well known to specialists in this field of technology. It will be clear that the number of rows to be included in the sector of the matrix 10 is considered as one sector. In a preferred variant embodiment of the matrix-in flash memory 4 MB 2048 rows (or pages) of 264 bytes each are grouped into 4 sectors, each of which contains 512 rows.

As discussed above, typically there are three operations that can be performed in the memory cells in a matrix of flash memory. These three operations are reading, programming and erasing. In the art knows how to perform an erase of the entire matrix of flash memory, i.e., total erase, and execute erase the entire sector, called Erasure of the sector. In accordance with the present invention, the erasing can be performed in the same row in the sector, known as the Erasure of a page or multiple pages in the sector, known as the erasing multiple pages.

In Fig. 2 illustrates part 14 sector 12 in accordance with the present invention. In part 14 sector 12 rows of 20 are divided into K groups, where each of the K groups has J rows. In a preferred variant embodiment of the matrix-in flash memory 4 MB, described above, 512 rows in the sector are divided into 64 groups, where each of the 64 groups includes 8 rows. In part 14 sector 12 the first group of rows 20-1 through 20-J is shown as group 1, and aetsa line of words, as is well known to specialists in this field of technology. Each of the lines of words of rows 20-1 through 20-J forms an intersection with the bit lines. Usually the number of bit lines in a matrix of flash memory is equal to the number of words in the range of 20 multiplied by the number of bits in each word. For example, in a preferred variant embodiment of a matrix of flash memory 4 M described above, there are 264 words in each row and 8 bits in each word. The result will be 2112 bit lines in a matrix of flash memory. In part 14 sector 12 one bit line 22 is depicted for illustrative purposes.

In the intersections between lines 20 words and bit lines 22 are cell 24 flash memory. A specific embodiment of a matrix of flash memory will not be described here to avoid complicating the description of the essence of the present invention. Cell flash memory suitable for use in accordance with the present invention, is described in U.S. patent 4783766, issued for the corresponding application filed may 30, 1986, the rights to which are owned by the present applicant.

To one end of each line 20 words connected pair of N-channel MOS transistors 26-1 and 26-2. In each pair of N-channel MOS transistors 26-1 and 26-2 drain of the first N-channel MOS transistor 26-1 p is s shift valve Vwg, a source and a drain of the first N-channel MOS transistor 26-1 and the second N-channel MOS transistor 28-2, respectively connected to the lines 20 words.

The gate of each N-channel MOS transistor 26-1 is connected to the select signal group Xs, and the gate of each N-channel MOS transistor 26-2 is connected to the complementsignal select group Xs, provided by inverter 28. It should be understood that the inverter 28 provides a voltage potential onthat is either above the desired value or lower than the voltage at Xs. The select signal group Xs and its Supplementprovided by the decoder, the implementation of which is within the competence of specialists in this field, which has not been disclosed here for exceptions complexity of describing the essence of the present invention.

For each element in flash memory located at the intersection of line 20 words and bit line 22, the drain element of flash memory is connected with the bit line 22, the source element 24 flash memory is connected to the voltage source matrix line 30 of the source matrix, and the shutter element 24 flash memory connects to the line 20 words. For each channel transistors 26-1 and 26-2 and the first element 24 flash memory, located at the intersection of line 20 words and bit line 22. United with a part of each line is 20 words, which is located between the P-channel MOS razvedochny transitional transistor 32 and the gate of the first element 24 flash memory located at the intersection of line 20 words and bit line 22 is the generator 34 of the pumping line of words, connected to a source of negative voltage is from approximately-15V to approximately -4 V, preferably -10 V, line 36 generator pumping line of words.

In Fig. 3 shows a table indicating the signals in the various elements in the circuit illustrated in Fig. 2, to implement the modes of reading, programming and erasing of the matrix flash memory, in accordance with the present invention. In accordance with the present invention, only the signals that are performed during the erase operation will be described here.

To select a specific number to erase the page, the voltage Vcc is supplied via the signal line group selection Xs to the gates of N-channel MOS transistors 26-1 group containing a number 20-1 through 20-J, choose to erase the page, and the voltage ground (0 V) is supplied via line complement signal group selection Xs to the gates of N-channel MOS transistors of the t group, having a number 20-1 through 20-J, choose to erase the page, voltage ground (0 V) is supplied via the signal line group selection Xs to the gates of N-channel MOS transistors 26-1, and the voltage Vcc is supplied via line complement signal group selection the XS on the gates of N-channel MOS transistor 26-2.

When the voltage on the signal lines of the group selection the XS andserved voltage ground (0 V) is supplied to the gate of the N-th canaliega MOS transistor 26-1 row 20-1 through 20-J, which is selected to erase the page, and the bias voltage in the range of from about 1 to about 5 and preferably from about 1 to about 2 is supplied to the drains of the rows 20-1 through 20-J which are not selected for erase page select signal row Xd and who are not in the same group as the row 20-1 through 20-J to be selected for erase page.

Voltage ground (0 V) will also be connected to the drains of N-channel MOS transistors 26-1 row 20-1 through 20-J unselectable in groups that correspond to the selected row 20-1 through 20-J and the bias voltage in the range of from about 1 to about 5 and preferably from about 1 to about 2 In will also be podavati selected rows 20-1 through 20-J in the selected group.

For example, when we select the next 20-1 through 20-J is the number 20-2 in group 1, the voltage ground (0 V) is supplied to the drain of N-channel MOS transistor 26-1 range of 20-2, and the drains of N-channel MOS transistors 26-1 number 20-2 in groups of 2 K. in Addition, the bias voltage will be supplied to the drains of N-channel MOS transistors 26-1 all rows 20-1 and 20-3 20-J in group 1, and to the drains of N-channel MOS transistors 26-1 all rows 20-1 and 20-3 20-J in groups of 2 To inclusive.

In addition to the signals at the drains of N-channel MOS transistors 26-1, when served voltage on the signal lines of the group selection Xs andthe bias voltage in the range of from about 1 to about 5 and preferably from about 1 to about 2 served on the sources of N-channel MOS transistor 26-2 line signal Vwg.

When these voltages are fed to the gates of N-channel MOS transistors 26-1 and 26-2 are included drain of N-channel MOS transistor 26-1 and the source of N-channel MOS transistor 26-2, the P-channel razvedochnye transitional transistors 32-1 to 32-j

As a result, the voltage ground (0 V) is supplied to the gates of the elements 24 flash memory in the selected row 20-1 through 20-J, and strain the above discussion, for the selected group of 1 To containing the selected row 20-1 through 20-J, the bias voltage applied to the gates of the elements 24 flash memory is not selected rows 20-1 through 20-J in the selected group, served by lines of the signal Xd, which is connected to the drains of N-channel MOS transistors 26-1, and that for all other rows 20-1 through 20-J in unselected groups 1 according To the bias voltage applied to the gates of the elements 24 flash memory, is provided by voltage, supplied through the signal line Vwg on the sources of N-channel MOS transistor 26-2.

When the voltage ground (0 V) is fed to the gates of the cells 24 flash memory in the selected row 20-1 through 20-J and the bias voltage in the range of from about 1 to about 5 and preferably from about 1 to about 2 submitted to the gates of all the other cells in 24 flash memory, the voltage applied to the gates of the P-channel MOS razvedochnyh transient transistors 32-1 to 32-J so that P-channel MOS razvedochny transitional transistor 32-1 to 32-J, connected with the selected next 20-1 through 20-J is turned off due to voltage gate-source. The negative voltage in the range from approximately-15V to approximately -4 V and preferably about -10 V is supplied to the selected row 20-1 through 20-J in squeeze complexity of describing the essence of the present invention, implementation of the generator 34 of the pumping line of words or other means for supplying a negative voltage to the selected row line 20-1 through 20-J, well known to experts in the art, will not be described here. Implementation of the generator 34 of the pumping line of words, suitable for use in accordance with the present invention, is disclosed in U.S. patent 4511811, issued for the corresponding application filed February 8, 1982, and 4673829 issued on an application filed February 8, 1985, the rights to which are owned by the present applicant.

Since the P-channel MOS razvedochny transitional transistor 32-1 to 32-J, connected with the selected next 20-1 through 20-J is turned off, a negative voltage applied to the gates of the cells 24 flash memory in the selected row 20-1 through 20-J, will not affect a pair of N-channel MOS transistors 26-1 and 26-2 for negative voltage. In addition, when the first supply voltage ground at the gates of the cells 24 flash memory in the selected row 20-1 through 20-J and not bias voltage less energy and time is spent by the generator 34 of the pump when applying a negative voltage to the gates of the cells 24 flash memory in the selected row 20-1 through 20-j

To complete the operation erase all pages bit lio approximately 6.5 Century As a result, the tunneling will occur between the floating gate and the source of the cells 24 flash memory on the selected row 20-1 through 20-J method, well known to experts in the art, to erase the cells 24 flash memory on the selected row 20-1 through 20-J, since the potential difference of from about 12 to about 20 and preferably about 16.5 V is established between the drain and the free shutter cells 24 flash memory on the selected row 20-1 through 20-j

In accordance with the present invention, when a positive voltage is from about 5 to about 10 and preferably about 6.5 is available on bit line 22, the cell 24 flash memory on all the selected rows 20-1 through 20-J will be less sensitive to the tunneling, since the bias voltage from about 1 to about 5 and preferably from about 1 to about 2 submitted to the gates of the cells 24 flash memory on all of the not selected row 20-1 through 20-j

It should be understood from the above discussion that the erasing multiple pages can be executed on multiple pages in the selected group a supply voltage ground (0 V) at the effluent of each of the N-channel MOS transitor cells 24 flash memory on all of the multiple selected rows 20-1 through 20-J. Generators 34 pumping line of words connected to multiple selected rows 20-1 through 20-J, and then select to establish a negative voltage is from approximately-15V to approximately -4 V and preferably about -10 V gate cells 24 flash memory on all of the multiple selected rows 20-1 through 20-J, inclusive.

When a positive voltage is from about 5 to about 10 and preferably about 6.5 V is supplied to bit line 22, tunneling will occur between the floating gates and the drains of the cells 24 flash memory on multiple selected rows 20-1 through 20-J method, well known to experts in the art, to erase the cells 24 flash memory on multiple selected rows 20-1 through 20-J, since the potential difference of from about 12 to about 20 and preferably about 16.5 V between the drain and floating gate of the cells 24 flash memory on multiple selected rows 20-1 through 20-J, inclusive.

In Fig. 4 illustrates a circuit 40 AC reference oscillator to provide the reference voltage selection series Xd for reading, programming and erasing. In the circuit 40 of the alternating oportunity row 20-1 through 20-J in the group. The output of the logic element 42 is NOT-AND is connected to the first input of logic element 44 OR NOT, the first input of logic element 46 OR-NOT through the inverter 48 and the first input of logic element 50 OR NOT.

The second input of logic element 44 OR NOT connected with a resolution of the offset line, which becomes high when the matrix flash memory is in erase mode. The second inputs of the logic elements 46 and 50, OR IS NOT connected with an addition enabling signal offset. The output of logic element 44 OR IS NOT connected with the first input of the logic element 52 OR NOT, and the second input of logic element 53 OR IS NOT connected with the allow signal offset. The output of logic element 44 OR NOT also connects to the source of N-channel MOS transition of the transistor 54 and the gate of N-channel weakening of the transistor 56.

The gate of N-channel MOS razvedochnogo transition of the transistor 54 is connected with razvedochny control signal, which is preferably Vcc. The reference potential of the AC voltage Vmp is connected to the sources of P-channel MOS transistors 58, 60 and 62. The source of N-channel MOS transistor 56 is connected to the ground. The gates of the P-channel MOS transistors 58 and 62 are connected to Go MOS razvedochnogo transition of the transistor 54 together with the drain of the P-channel MOS transistor 58. The drain of the P-channel MOS transistor 60 is also connected to the drain of N-channel MOS transistor 56. N-channel MOS transistor 64 has its gate connected to the output of the logic element 52 OR NOT, a source connected to ground, and a drain connected to the drain of the P-channel MOS transistor 62 to form output Xd circuit 40 of the generator of the reference voltage.

The outputs of logic elements 46 and 50, OR IS NOT connected to the gates of N-channel MOS transistors 66 and 68. The drain of N-channel MOS transistor 66 is connected with a bias voltage, and the source of N-channel MOS transistor 68 is connected to the ground. The source of N-channel MOS transistor 66 is connected to the drain of N-channel MOS transistor 68 to form a node, which is connected to the output Xd circuit 40 of the generator of the reference voltage.

When the operation of the circuit 40 of the alternating reference signal, when the erase mode of the page, allowing the signal bias is set high so that the output of logic elements 44 and 52 OR will NOT be low. Low signal passing through the N-channel MOS transistor 54 to the gate of the P-channel MOS transistor 60, set the AC voltage Vmp gate of the P-channel MOS transistor 62. Voltage Vmp modes midrange is, the-channel MOS transistor 62 turns off. Low signal logic element 52 OR-NOT gate N-channel MOS transistor 64 also turns off N-channel MOS transistor 64.

In erase mode page, when enabling the signal bias is set high, the addition enabling signal offset, United with logical elements 46 and 50 OR NOT, is low. Also with the logical elements 46 and 50, OR is NOT inverted output of the logic element 42 is NOT-AND the output of the logic element 42 is NOT-AND, respectively. The low output signal from the logic element 42 is NOT-AND indicates that selects a specific row 20-1 through 20-J. Thus, when a low output signal of the logic element 42 is NOT-AND is served in the logical element 50 OR NOT, Xd earthed through the N-channel MOS transistor 68, which is enabled by the output signal of the logic element 50 OR NOT, and when the high output signal of the logic element 42 is NOT-AND served as a low signal in the logical element 46 OR-NOT through an inverter 48, the output signal Xd will catch up to the bias voltage through the N-channel MOS transistor 66, which is enabled by the output signal of the logic element 46 OR NOT.

During either the read mode, the NTA 42 NOT-AND will make the output signal of the logic element 44 OR IS NOT high, and the high signal of the logic element 42 is NOT-AND will make the output signal of the logic element 44 OR-NOT low. When the output signal of the logic gate 44 is high, the voltage Vmp will be installed at the exit Xd through the P-channel MOS transistor 62, which is turned on when its gate is grounded through the N-channel MOS transistor 56, which is enabled by a high signal from the logic element 44 OR NOT. When the output signal of the logic element 44 OR NOT is low, the voltage of the ground will be installed at the exit Xd through N-channel MOS transistor 64, which is enabled by a high signal from the logic element 52 OR NOT.

Although depicted and described variants of the embodiment of the present invention, specialists in the art will understand many more modifications than mentioned above are not leaving here described inventive concept. Thus, the present invention is not limited to the presented here options of its embodiment, and the scope of its patent protection is defined by the claims.

Claims

1. The method of operation of erasing one row of the matrix of flash memory, organizovannuyu with each column of the matrix, moreover, the flash memory includes multiple memory cells, each associated with one row line and one column line of the matrix and includes a transistor having a control gate connected to one of the lines of the row with which it is associated, a floating gate, a source connected to a common node of the source for the matrix memory, and a drain connected to one of bit lines to which it is linked, according to which serves the first voltage to the row line associated with erasable beside, served the second voltage, more positive, than said first voltage, in series lines in the matrix associated with the series, other than those referred to erase the number, and serves the third voltage, more positive than said second voltage to each bit line in the matrix, and the difference between the said first and second voltages is equal to the amount sufficient to cause electrons to tunnel from the above-mentioned floating gate, and the difference between the said second and third voltages is equal to such a value that said floating gate is less sensitive to the tunneling.

2. The method according to p. 1, characterized in that the said matrix flash memory further includes in the aforementioned first voltage comply with the said generator pumping line of words.

3. The method according to p. 1, characterized in that the said second voltage does not exceed Vcc.

4. The method according to p. 1, characterized in that the said first voltage is between -15 and -4 mentioned second voltage is equal to from 1 to 5, and the third voltage is equal to 5 to 10 C.

5. The method according to p. 1, characterized in that it further provides a floating state referred to the common node of the source.

6. The method of operation of erasing at least one transistor cell of the flash memory, at the same time without performing the erase operation on the other transistors of the cells of the flash memory in a matrix of flash memory, which includes a set of transistors of memory cells, where each transistor of the memory cell has a control gate, floating gate, source and drain, under which serves a first voltage to a control gate of at least one transistor in the erased memory cells, serves the second voltage, more positive than said first voltage, on the control gates of all the transistors of the cells mentioned memory, other than those referred to at least one transistor in the erased cells mentioned memory serves third voltage more positive than said second of namati and drains mentioned transistors is not erasable memory cells, where the difference between the said first and second voltages is sufficient to cause electrons to tunnel from the above-mentioned floating gate mentioned at least one transistor indelible cells mentioned memory, and where the difference between the said second and third voltages of equal magnitude, such that the said floating gates mentioned transistors indelible cells mentioned memory are less sensitive to the tunneling.

7. The method according to p. 6, characterized in that the said matrix flash memory further includes a generator pumping line of words, operatively connected with the said line of words, and referred to the submission referred to first comply with the said voltage generator pumping line of words.

8. The method according to p. 6, characterized in that the said second voltage does not exceed Vcc.

9. The method according to p. 1, characterized in that the said first voltage is between -15 and -4 mentioned second voltage is equal to from 1 to 5, and the third voltage is equal to 5 to 10 C.

10. The method according to p. 6, characterized in that it further provides a floating state referred to the common node of the source.

11. The device matrix flash past control gate, the floating gate electrode, a source and a drain, means for supplying a first voltage to a control gate of at least one transistor in the erased cells of said memory, means for supplying a second voltage, more positive than said first voltage, to the control gates of all the transistors of the cells mentioned memory, other than those referred to at least one transistor in the erased cells of said memory, means for supplying a third voltage that is more positive than said second voltage on said drain mentioned at least one transistor in the erased memory cells and to the drains of the mentioned transistors indelible memory cells, where the difference between the said first and third voltage is sufficient to cause electrons to tunnel from the above-mentioned floating gate mentioned at least one transistor non-erasable memory cell, and where the difference between the said second and third voltages is equal to such a value that the said floating gates mentioned transistors indelible memory cells are less sensitive to the tunneling.

12. The device according to p. 11, characterized in that it further the creation on p. 11, characterized in that the said second voltage does not exceed Vcc.

14. The device according to p. 11, characterized in that the said first voltage is between -15 and -4 mentioned second voltage is equal to from 1 to 5, and the third voltage is equal to 5 to 10 C.

 

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FIELD: semiconductor memory devices.

SUBSTANCE: device has a lot of memory elements, each of which contains input and output areas, isolating film, channel area, shutter electrode, area for storing electric charges, device also contains large number of periphery circuits, containing reading amplifier, register for storing recorded data of memory elements, register, which preserves the flag, indicating end of record during its check, and circuit, which after recording operation compares value, read from memory cell, to value, fixed by flag at the end of record, and overwrites value indicated by the flag.

EFFECT: higher reliability of operation.

5 cl, 71 dwg

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