The device discrete-weight addition exploded signals

 

The invention relates to techniques for radio communications. The inventive design of the device adding the separated signals, providing higher efficiency channel and hardware resources due to the redistribution of free channels. The technical result is achieved due to the introduction of additional L-1 clock blocks, L-1 blocks adders, switch, information signals, switch, clock and control unit. Information outputs of one or more free channels on command of the control unit using the switch information signals can be connected to the unit adders of the direction of communication, in which there is provided a specified reception quality message. 4 Il.

The invention relates to techniques for radio communication and can be used in multi-channel (multi-strategy) radio systems with receive diversity.

The claimed technical solution expands the Arsenal of tools for this purpose.

A device for diversity reception of Telegraph signals (see A. C. 1292195, N 04 7/02, bull. 7 from 07.02.87) containing channels explode, the adder unit feedback unit prerozdelenia contains the main reception block, block phasing, register, additional receiving unit, Phaser, block definitions-difference signals, the demodulation unit and the meter temporary distortions. Some increase noise immunity is achieved through coherent combining of signals with widely separated adaptive duanting modules - damping concentrated interference.

The disadvantage of analogue is the low efficiency of the channel and hardware resources. This is because in the direction of the communication in advance is allocated a certain number of channels explode (duanting modules), and changing conditions of communication in several directions not possible to reallocate the antenna modules between them for communication with the desired quality.

It is also known device channels for receive diversity (see A. C. 1525925, N 04 7/08, bull. 44 from 30.11.89) containing the unit of addition, a demodulator, a regenerator and N paths explode, each of which includes a radio receiver, the first and second switches, the unit of analysis frequencies and distortion meter. It provides some increased robustness due to the optimal combination of frequency-diversity reception of signals with the choice for which is the changing of the operating frequency when exposed to noise and the deterioration of radio wave propagation conditions.

The disadvantage of analogue is the low efficiency of the channel and frequency resources. This is because in the direction of the communication in advance is allocated a certain number of channels (branches) explode and frequencies, and changing conditions of communication in several directions not possible to reallocate the channels and frequencies between them for communication with the desired quality.

The closest as the number of similar features, and achieved technical result of the claimed device is a device discrete-weight adding the separated signals (see A. C. 1660184, N 04 7/02, bull. 24 from 30.06.91).

It contains a block of adders, a clock unit and N channels, where N2. The block of adders includes first and second adders, as well as the decisive element. The first and second inputs of the decisive element are connected respectively to the outputs of the first and second adders, and the output of the decisive element is the output of unit adders, i-th input of the first adder and the first input of the second adder, where i = 1, 2,...N, are, respectively, (2i-1)-th and (2i)-th inputs of the unit adders. The clock input of the decisive element is the clock input of the adders.

the selection of the clock sequence. The component output clock selection sequence is connected to the meter inlet and the first and fourth outputs of the clock unit. The fourth output of the clock unit is connected to the clock input of unit adders. The outputs of the counter are connected to respective inputs of the decoder, the output of which is the third output of the clock unit. The output element of the selection of the first response is connected to the input of the delay element. The output of the delay element is connected to the reset input of the counter and is the second output of the clock unit. Each input signal clock frequency item selection clock sequence is the corresponding clock input of the clock unit, and each input item selection clock sequence and element selection of the first response is appropriate master clock input block.

Each channel includes discrete coherent filter, managed storage element, fairway regenerator response, the driver weights, the first and second delay elements, the inverter, the first and second multiplier products, arithmetic divider, the first, second and third keys, the first and second registers, the first and second counters, the detector of oshibka delay, the output of which is connected to the input of the first key. The output of the first key is connected to the input of the first register, the output of which is connected to the input of the first counter. The outputs of the first counter connected to inputs of the dividend arithmetic divisor. The outputs of the second counter connected to inputs of the arithmetic divider divider, the output of which is connected to the input of the third key. The output of the third key is connected to the second inputs of the first and second multiplier products, and the control input of the third key is connected to the serial output of the second register.

The output of the error detector connected to the negative input of the switch and to the input of the detector centered interference. The output of the detector centered interference is connected to the input of the second key, the output of which is connected with the control input of the first key and the input of the second register. The output of the second register is connected to the input of the second counter. Information input discrete matched filter is an information channel input, and clock input discrete matched filter is a clock input of the channel. The first output discrete matched filter connected to the input of fairemode regenerator response and the input of the shaper viavra connected to the information input of the control storage element, the log record which is connected to the output fairemode regenerator responses. The clock input of the control storage device is connected to a clock input of the shaper of the weights and is the first synchronization channel input, and the input of the read-managed storage element is a second synchronization channel input. The output controlled storage element is connected to the input of the error detector and the input of the first delay element.

The output of the first delay element connected to the first input of the second multiplier and the input of the inverter. The output of the inverter connected to the first input of the first multiplier. The shaper's output weights connected to the input of the switch, the control input of which is connected with the control input of the second key and the third clock input channel. The first and second outputs of the i-th channel is connected respectively to the first and the second input of the i-th group of inputs of unit adders. The clock input of each channel is connected to the clock input of the clock unit. Synchronizing the output of each channel is connected to the corresponding sets the clock input of the block. First, second and third synchronizing the data device in comparison with analogues provides some increased robustness due to the disconnection of the channel, affected by the concentrated hindrance from block adders. This device will accept as a prototype.

The disadvantage of the prototype is the low efficiency of the channel and hardware resources (branches explode). This is because in the direction of the communication in advance is allocated a certain number of channels (branches) explode, and when conditions change communication in several directions not possible to reallocate the channels between them for communication with the desired quality.

The aim of the invention is to develop a device addition exploded signals for multiple radio for greater efficiency in the use of channel and hardware resources due to the redistribution of free channels, and channels affected by the concentrated obstacle in one direction of the communication between other areas of communication.

This objective is achieved in that in the known device, containing the first block of adders, including the first and second adders, the decisive element, the first and second inputs which are connected respectively to the outputs of the first and second adders, the output and the clock input decisive lead of the second adder, where i=1, 2,...N, a N2, are respectively (2i-1)-th and (2i)-th entry unit of the adders, the first clock unit including a decoder, counter, delay element, the element selection of the first response, the item selection clock sequence, the output of which is connected to the meter inlet and the first and fourth outputs of the clock unit, the outputs of the counter are connected to respective inputs of the decoder, the output element of the selection of the first response is connected to the input of the delay element, the output of which is connected to the reset input of the counter, each input signal clock frequency item selection clock sequence is the corresponding clock input of the clock unit, and each input item selection clock sequence and element selection of the first response is appropriate master clock input unit, the fourth output clock unit is connected to the clock input of the first block of adders.

The output of the delay element is a second output of the clock unit, the output of the decoder is the third output of the clock unit, the N channels, where N2, each of which includes discrete coherent filter, managed remember what aderemi, the inverter, the first and second multiplier products, arithmetic divider, the first, second and third keys, the first and second registers, the first and second counters, the error detector, the detector centered interference, the switch, the output of which is connected to the input of the second delay element, the output of which is connected to the input of the first key, the output of which is connected to the input of the first register, the output of which is connected to the input of the first counter whose outputs are connected to inputs of the dividend arithmetic divider, the outputs of the second counter connected to inputs of the arithmetic divider divider, the output of which is connected to the input of the third key, the output of which is connected to the second inputs of the first and second multiplier products.

The control input of the third key is connected to the serial output of the second register, the information input discrete matched filter is an information channel input, and clock input discrete matched filter is a clock input of a channel, the first output discrete matched filter connected to the input of fairemode regenerator response and the input of the shaper of the weights and is synchronizing channel output and the second output of thesis is on the record which is connected to the output fairemode regenerator response, the clock input of the control storage device is connected to a clock input of the shaper of the weights and is the first synchronization channel input, and the input of the read-managed storage element is a second synchronization channel input, output controlled storage element is connected to the input of the error detector and the input of the first delay element, the output of which is connected to the first input of the second multiplier and the input of the inverter, the output of which is connected to the first input of the first multiplier, the output of the shaper weights connected to the input of the switch, the control input of which is connected with the control input of the second key and the third clock input channel.

The outputs of the first and second multiplier products are respectively the first and the second output channel, the output of error detector connected to the negative input of the switch and to the input of the detector centered interference, the output of which is connected to the input of the second key, the output of which is connected with the control input of the first key and the input of the second register, the output of which is connected to the input of the second counter, added L-1 blocks adders, where N

In each channel serial output of the second register is the signal output of the channel and connected to the corresponding input of the control unit. The clock input of each channel is connected to the clock input of the switch clock pulses, and synchronizing the output of each channel is connected to the corresponding channel to the switch input clock pulses. First, second and third clock inputs of the i-th channel, where i=1, 2,...N, are connected respectively to the first, second and third outputs of the i-th group of the channel outputs of the switch clock. The first and second outputs of the i-th channel, where i=1, 2,...N, are connected respectively to first and second inputs of the corresponding i-th group of information inputs of switch information signals, the first group of outputs of the control unit is connected to the corresponding i-th group of control inputs of the switch clock pulses and switch information signals. N outputs of the j-th group clock outputs switch clock pulses, where j=1, 2,...L, connected respectively to N clock inputs of the j-th clock unit, and the N outputs of the j-th group specifies the output switch clock pulses connected respectively to N specifying the inputs from the public to the first, the second and third inputs of the j-th group setting inputs of the switch clock. The fourth output of each clock unit is connected to the clock input of the corresponding block of adders. 2N outputs of the j-th group outputs switch information signals are connected to the corresponding 2N inputs of the j-th block of adders.

Thanks to the new essential features by introducing additional blocks allows free redistribution of the receiving channels, and the channels affected by the concentrated obstacle in one direction of the communication between other areas of communication.

The analysis of the level of technology has allowed to establish that the analogues, characterized by a set of characteristics is identical for all features of the claimed technical solution is available, which indicates compliance of the claimed invention to condition patentability of "novelty."

Search results known solutions in this and related areas of technology in order to identify characteristics that match the distinctive features of the prototype of the features of the declared object, showed that they do not follow explicitly from the prior art. The prior art also revealed no known impact PR is a technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The inventive device illustrated by the drawings, in which: Fig. 1 shows a functional diagram of the device of discrete-weight addition to the diversity signals of Fig.2 - circuit switch information signal 33 of Fig.3 - scheme of the control unit 34 of Fig.4 is a diagram of the switch clock pulses 36.

The inventive device shown in Fig.1, consists of N channels 91... 9NL blocks adders 321...32LL clock blocks 351...35Lthe switch information signal 33, a control unit 34, the switch clock pulses 36. Each channel 9 contains discrete coherent filter 10, a managed storage element 13, fairway regenerator response 14, the driver weights 15, the first delay element 16, an inverter 18, the first 19 and second 20 multiplier products, arithmetic divider 31, the third key 26, connected in series, the switch 21, the second delay element 17, the first key 24, the first register 27 and the first counter 29, connected in series error detector 22, the detector centered interference 23, the second key 25, the second R is 31, the output of which is connected to the third input key 26. The output of the third key 26 is connected to second inputs of the first 19 and second 20 multiplier products. The control input of the third key 26 is connected to the serial output of the second register 28 is the signal output of the channel 9.

The output of the error detector 22 is connected to an inverted input of the switch 21 and to the input of the detector centered interference 23. The output of the detector centered interference 23 is connected to the input of the second key 25, the output of which is connected with the control input of the first key 24 and to the input of the second register 28. The output of the second register 28 is connected to the input of the second counter 30. The output of switch 21 is connected to the input of the second delay element 17, the output of which is connected to the input of the first key 24. The output of the first key 24 is connected to the input of the first register 27, the output of which is connected to the input of the first counter 29. The outputs of the first counter 29 is connected to the inputs of the dividend arithmetic divider 31. Information input discrete matched filter 10 is an information channel input 11, and a clock input discrete matched filter 10 is a clock input of the channel 12. The first output discrete matched filter 10 is connected to in youdim output channel 9. The second output discrete matched filter 10 is connected to the information input of the control storage element 13, the input record which is connected to the output fairemode regenerator responses 14.

The clock input of the control storage device 13 is connected to a clock input of the shaper weights 15 and is the first clock input of channel 9. The sign read managed storage element 13 is the second synchronizing input channel 9. The output controlled storage element 13 is connected to the input of the error detector 22 and the input of the first delay element 16. The output of the first delay element 16 is connected to the first input of the second multiplier 20 and the input of the inverter 18. The output of the inverter 18 is connected to the first input of the first multiplier 19. The shaper's output weights 15 is connected to the input of the switch 21, the control input of which is connected with the control input of the second key 25 and the third clock input channel 9. The outputs of the first 19 and second 20 multiplier products are respectively the first and second outputs of the channel 9.

Each block of adders 32 contains the first 1 and second 2 adders, a crucial element 3. The first and second what is the output of unit adders 32. the i-th input of the first adder 1 and the i-th input of the second adder 2, where i=1, 2,...N, a N2 are respectively (2i-1)-th and 2i-th input of the adders 32. The clock input of the decisive element 3 is a clock input of the adders 32.

Each clock unit 35 includes a decoder 8, the counter 7, the delay element 6, the element selection of the first response 5 and item selection clock sequence 4. The component output clock selection sequence 4 is connected to the input of the counter 7 and the first and fourth outputs of the clock unit 35. The outputs of the counter 7 is connected to respective inputs of the decoder 8, the output of which is the third output of the clock unit 35. The output element of the selection of the first response 5 is connected to the input of the delay element 6. The output of the delay element 6 is connected to the reset input of the counter 7 and the second output of the clock unit 35. Each input signal clock frequency item selection clock sequence 4 is the corresponding clock clock input unit 35, and each input item selection clock sequence 4 and element selection of the first reaction 5 is the corresponding master clock input unit 35. The fourth output of each t the th channel 9 is connected to the corresponding input of the control unit 34. The clock input of each channel 9 is connected to the clock input of the switch clock pulses 36 and the clock output of each channel 9 is connected to the corresponding channel input switch clock pulses 36. First, second and third clock inputs of the i-th channel 9, where i=1, 2,...N, are connected respectively to the first, second and third outputs of the i-th group of the channel outputs of the switch clock pulses 36. The first and second outputs of the i-th channel 9 connected respectively to first and second inputs of the corresponding i-th group of information inputs of the switch information signal 33. i-I group of outputs of the control unit 34 is connected to the corresponding i-th group of control inputs of the switch clock pulses 36 and the switch information signal 33. N clock outputs of the j-th group clock outputs switch clock pulses 36, where j=1, 2,...L, are connected to the corresponding N clock inputs of the corresponding j-th clock unit 35ja N specifies the outputs of the j-th group specifies the output switch clock pulses 36 are connected to N specifying the inputs of the corresponding j-th clock unit 35j. First, second and third outputs of the j-th clock unit 35jconnect law 36. 2N outputs of the j-th group of outputs of the switch information signal 33 is connected to the corresponding 2N inputs of the j-th block of adders 32j.

The switch information signal 33 is designed to connect its first and second inputs of the i-th group of information inputs defined in accordance with the control command (2i-1)-th and 2i-th outputs of the j-th group of outputs. The switch information signal 33 shown in Fig.2 and consists of N groups of control keys on L in each group 33.11..L...33.N1..L. He has N pairs of information inputs, N groups of the control inputs on the L inputs in each group and L groups o 2N outputs in each group. While the first and second inputs of the i-th group of information inputs of switch information signals 33 are respectively the first and second inputs of all L keys of the i-th group of managed keys 33.i1...33.iLwhere i=1, 2,...N, j=1, 2,.. . L. the control input of the j-th key of the i-th group of managed keys 33.i1...33.iLis the j-th managing log in i-th group of control inputs of the switch information signal 33. Doubles the output of the j-th key of the i-th group of managed keys 33. i1...33.iLis the i-th pair of output of j-th group of outputs of the switch info and the second of its inputs (a pair of inputs to the first and second outputs to a pair of outputs respectively when the control voltage on the control input. Schemes managed keys 33.1..L..., 33.N1..Lknown and described, they can be built on the chip KRKT (see Veniaminov Century. N. and other Circuits and their application. The Handbook. - M.: Radio and communication, 1983, S. 66-69).

The control unit 34 is designed to supply control voltages to the switches of information signals 33 and clock pulses 36 to connect free and not affected focused interference channels in the desired direction, i.e. to the required blocks adders (the i-th channel 9ito the j-th block of adders 32j). Control switches can be controlled automatically using a microprocessor, and with the help of the operator. In the case of the control switches by the operator, the control unit 34 can be implemented, for example, as shown in Fig.3. He consists of N inverters 34.11...34.1nN managed keys 34.21...34.2NN led i-th channel is defective and N groups of switches of the i-th channel in the j-e direction" L in each group.

Moreover, the i-th input of the control unit 34 is input to the i-th inverter 34.1iwhose output is connected to the i-th led and is the managing log i-the "case". Through an appropriate switch i-th channel in the j-e direction of j-th output of the i-th managed key 34.2iconnected to the j-th output of the i-th group of outputs of the control unit 34.

Inverters 34.11..Ndesigned to convert received at their input voltage low level signal "0" of the blocks 91..N) with the defeat of concentrated hindrance of one of the channels in the high-level voltage output (>1). Inverters 34.11..Nknown and described. They can be implemented, for example, on the chip CLA described - Veniaminov Century. N. and other Circuits and their application. The Handbook. - M.: Radio and communication, 1983, c.196-197.

Managed key 34.21..Ndesigned to cut their L inputs from the respective L outputs when the control voltage on the control input. Schemes managed keys 34.21..Nknown and described, they can be implemented on the chip KN (see Veniaminov Century. N. and other Circuits and their application. The Handbook. - M.: Radio and communication, 1983, S. 66-69).

The switches i-th channel in the j-e direction are buttons with led indication when pressed and can be combined into a single light displays.

Switch clock pulses 36 before the i-th input channel group input - to the i-th output of the j-th group specifying outputs and j-th group specifies the inputs to the i-th group of channel outputs (one or more of N). Switch clock pulses 36 shown in Fig.4 and consists of N groups of control keys on L in each group 36.1.11..L... 36.1. N1..LN groups of control keys on L in each group 36.2.11..L... 36.2. N1..Land L groups managed keys N in each group 36.3.11..N... 36.3.L1..N. Thus the i-th entry of the group of clock inputs connected to the inputs of all L controlled switches of the i-th group of managed keys 36.1.i1...36.1.iLthe output of the j-th managed key of the i-th group of managed keys 36.1.ijis the i-th output of the j-th group clock outputs switch clock pulses 36. the i-th input channel group input switch clock pulses 36 are connected to the inputs of all L controlled switches of the i-th group of managed keys 36.2.i1... 36.2.iLand the output of the j-th managed key of the i-th group of managed keys 36.2. ijis the i-th output of the j-th group specifies the output switch clock pulses 36.

First, second and third inputs of the j-th group setting inputs of the switch clock pulses 36 are connected respectively to the first, second and third inputs of all N managed the on key of the j-th group of managed keys 36.3.jiis respectively the first, second and third outputs of the i-th group of the channel outputs of the switch clock pulses 36. j-th control input of the i-th group of control inputs of the switch clock pulses 36 are connected to the control input of the j-th managed key of the i-th group of managed keys 36.1. ijand 36.2.ijand also to the control input of the i-th key of the j-th group of managed keys 36.3.ji.

Managed key 36.1.11..L. . . 36.1.N1..Land 36.2.11..L...36.2.N1..Ldesigned to connect its input to the output when the control voltage on the control input. Schemes managed keys 36.1.11..L. . . 36.1.N1..Land 36.2.11..L...36.2.N1..Lknown and described. They can be implemented, for example, on the chip CCN (see Veniaminov Century. N. and other Circuits and their application. The Handbook. - M.: Radio and communication, 1983, S. 66-69).

Managed key 36.3.11..N...36.3.L1..Ndesigned to connect its first, second and third inputs to the first, second and third outputs, respectively, when the control voltage on the control input. Schemes managed keys 36.3.1..N. . .36.3.L1..Nknown and described. They can be re the manual. - M.: Radio and communication, 1983, S. 66-69).

The inventive device operates as follows. Before starting work, the operator or microprocessor (MP) selects a certain number of channels (branches explode) njfrom N to ensure the required quality of reception of messages for each j-th direction of L directions. According to the operator's commands (using switches) or MP control unit 34 supplies control voltage to the corresponding managed key switch information signals 33 and the switch clock pulses 36. Switch information signals 33 a pair of channel outputs of each channel 9 of the njselected for the j-th direction of communication channels connected to the unit adders 32j. To ensure clock synchronization of the selected channels on the master channel they switch clock pulses 36 are connected to the respective clock unit 35j. When this clock inputs of all njselected channels 9 are connected to the respective clock inputs clock unit 35jand synchronizing the outputs of all njselected channels 9 to specify the clock inputs of the block 35j.

In turn, pemu clock inputs of all njselected channels 9. It is possible that in j-th direction of the communication is not provided the required reception quality message and there are free channels 9. In this case, to ensure the required quality of reception in this direction by the control unit 34, the switch information signal 33 and the switch clock pulses 36 can connect additional channels 9 that is available.

With the defeat of concentrated hindrance of one of the njchannel 9 this channel is not involved in the summation in j-th block of adders 32jand through the signal output to the control unit 34 receives a corresponding signal (low level) indicating that the channel is faulty. Using the control unit 34 this channel is disconnected from the j-th block of adders 32j. If, for example, a radio channel, it can change to another frequency in order to avoid exposure to concentrated interference and use them in the future as free.

In order to ensure the desired quality of communication in the j-th direction when you disable one of the channels (branches explode), the operator or MP can connect one or more channels from among the available at the moment, for which the operator selects the channel and pomoshy outputs of the control unit 34. Hereinafter, this voltage is supplied to the respective controlled the keys in the switch information signal 33 and the switch clock pulses 36. With their help connect the inputs and outputs of the selected channel 9 to the unit adders 32jand clock block 35jthe j-th direction.

The control unit 34 operates as follows. In the initial position (in the absence of concentrated noise) in the presence of high voltage level from the i-th channel 9iall L contacts of the corresponding i-th key 34.2ishorted. If the operator is using the switch "i-th channel in the j-e direction connects the i-th channel in the j-e the direction of the communication, the control voltage ("body") through the closed contacts of the corresponding key 34.2iand the corresponding switch of the i-th channel in the j-e direction is supplied to the j-th output of the i-th group of outputs and control inputs to the switch information signal 33 and the switch clock pulses 36. With the defeat of concentrated hindrance of the i-th channel 9iwith its signal output low level signal is supplied to the corresponding i-th input of the control unit 34. Inverter through this voltage is converted into a voltage of a high level, turns on led Halloween gift the s outputs of the control unit 34 is absent, the illumination of the corresponding switch to the i-th channel in the j-e direction" goes off and the channel is disconnected from the j-th block of adders 32j.

Thus, the proposed device increases the efficiency of the channel and hardware resources, as it has the possibility to redistribute the available channels (branches explode) between lines of communication, quality of communication in which there is provided isolated in their channels. This affected lumped interference channels can be disabled and if it is, for example, radio channels, then rebuild them on other frequencies, and in the future be used as available.

Claims

The device discrete-weight addition exploded signals containing the first block of adders, including the first and second adders, the decisive element, the first and second inputs which are connected respectively to the outputs of the first and second adders, the output and the clock input of the decisive element are respectively the output and a clock input of the adders, the i-th input of the first adder and the first input of the second adder, where i=l,2,...N, a N2, are respectively (2i-1)-th and (2i)-th input block sumata is a, element selection clock sequence, the output of which is connected to the meter inlet and the first and fourth outputs of the clock unit, the outputs of the counter are connected to respective inputs of the decoder, the output element of the selection of the first response is connected to the input of the delay element, the output of which is connected to the reset input of the counter, each input signal clock frequency item selection clock sequence is the corresponding clock input of the clock unit, and each input item selection clock sequence and element selection of the first response is appropriate master clock input unit, the fourth output clock unit is connected to the clock input of the first block of adders, the output of the delay element is a second output of the clock unit, the output of the decoder is the third output of the clock unit, N channels, each of which includes discrete coherent filter, managed storage element, fairway regenerator response, the driver weights, the first and second delay elements, the inverter, the first and second multiplier products, arithmetic divider, the first, second and third keys, the first and second registers, the PE the CSO is connected to the input of the second delay element, the output of which is connected to the input of the first key, the output of which is connected to the input of the first register, the output of which is connected to the input of the first counter whose outputs are connected to inputs of the dividend arithmetic divider, the outputs of the second counter connected to inputs of the arithmetic divider divider, the output of which is connected to the input of the third key, the output of which is connected to the second inputs of the first and second multiplier products, the control input of the third key is connected to the serial output of the second register, the information input discrete matched filter is an information channel input, and clock input discrete matched filter is a clock input of a channel the first output discrete matched filter connected to the input of fairemode regenerator response and the input of the shaper of the weights and is synchronizing channel output and the second output discrete matched filter connected to the information input of the control storage element, the input record which is connected to the output fairemode regenerator feedback clock input of the control storage element is connected to a clock input of the shaper weight CoE is lement is the second synchronization channel input, the output controlled storage element is connected to the input of the error detector and the input of the first delay element, the output of which is connected to the first input of the second multiplier and the input of the inverter, the output of which is connected to the first input of the first multiplier, the output of the shaper weights connected to the input of the switch, the control input of which is connected with the control input of the second key and the third clock input channel, the outputs of the first and second multiplier products are respectively the first and the second output channel, the output of error detector connected to the negative input of the switch and to the input of the detector centered interference, the output of which is connected to the input of the second key, the output of which is connected with the control input of the first key and the input of the second register, the output of which is connected to the input of the second counter, wherein the added L-1 blocks adders, where NL2, L-1 clock units, the switch information signals, the control unit, the switch of clock pulses in each channel serial output of the second register is a signal output channel and podkluchatsa to the switch input clock pulses, synchronizing the output of each channel is connected to the corresponding channel to the switch input clock pulses, the first, second and third clock inputs of the i-th channel is connected respectively to the first, second and third outputs of the i-th group of the channel outputs of the switch clock pulses, the first and second outputs of the i-th channel connected respectively to first and second inputs of the corresponding i-th group of information inputs of switch information signals, the first group of outputs of the control unit is connected to the corresponding i-th group of control inputs of the switch clock pulses and switch information signals, N outputs of the j-th group clock outputs, where j=l,2,...L, the switch of clock pulses connected respectively to N clock inputs of the j-th clock unit, the N outputs of the j-th group specifies the output switch clock pulses connected respectively to N specifying the inputs of the j-th clock unit, first, second and third outputs of the j-th clock unit connected respectively to the first, second and third inputs of the j-th group setting inputs of the switch clock pulses, the fourth output of each clock unit is connected to the clock input of the corresponding block sums of the j-th block of adders.

 

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The invention relates to the field of frequency synthesis and can be used in the frequency synthesizer with a fractional value of the division factor

FIELD: communications engineering.

SUBSTANCE: proposed system has user terminal, gateway, and plurality of beam sources radiating plurality of beams, communication line between user terminal and gateway being set for one or more beams. Proposed method is based on protocol of message exchange between gateway and user. Depending on messages sent from user to gateway, preferably on pre-chosen periodic basis, gateway determines most suited beam or beams to be transferred to user. Messages sent from user to gateway incorporate values which are, essentially, beam intensities measured at user's. Gateway uses beam intensities measured at user's to choose those of them suited to given user. Beams to be used are those capable of reducing rate of call failure and ensuring desired separation level of beam sources.

EFFECT: reduced rate of call failure in multibeam communication system.

20 cl, 27 dwg

FIELD: automatic adaptive high frequency packet radio communications.

SUBSTANCE: each high frequency ground station contains at least one additional high frequency receiver for "surface to surface" communication and at least one additional "surface to surface" demodulator of one-tone multi-positional phase-manipulated signal, output of which is connected to additional information input of high frequency controller of ground station, and input is connected to output of additional high frequency "surface to surface" receiver, information input of which is connected to common high frequency receiving antenna, while control input is connected to additional control output of high frequency controller of ground station.

EFFECT: prevented disconnection from "air to surface" data exchange system of technically operable high frequency ground stations which became inaccessible for ground communications sub-system for due to various reasons, and also provision of possible connection to high frequency "air to surface" data exchange system of high frequency ground stations, having no access to ground communication network due to absence of ground communication infrastructure at remote locations, where these high frequency ground stations are positioned.

2 cl, 12 dwg, 2 tbl

FIELD: planning data transfer in wireless communication systems.

SUBSTANCE: proposed method used for planning data transfer over incoming communication line for definite terminals of wireless communication system includes formation of definite set of terminals for probable data transfer, each set incorporating unique combination of terminals and complies with estimate-designed hypothesis. Capacity of each hypothesis is evaluated and one of evaluated hypotheses is chosen on capacity basis.

EFFECT: enhanced system capacity.

39 cl, 12 dwg

FIELD: mobile communication systems.

SUBSTANCE: system contains closed contour, thus expanding similar system with open contour and made with possible use of distancing technology during transfer with four antennas, and method for transferring signal in aforementioned system. Method for transferring signal in system for spatial-temporal distancing during transfer with closed contour, having several transferring antennas, includes: spatial-temporal encoding of symbols, meant for transfer; classification of encoded symbols in appropriate groups; and multiplication by different weight values of each group of transferred symbols and their transmission.

EFFECT: improved quality of communication.

5 cl, 5 dwg

FIELD: radio communications, possible use in space and ground communication systems, using noise-like signals.

SUBSTANCE: at transmitting side device features: first and second transmitter decoders, transmitter counter, first and second transmitter keys, transmitter phase inverter, OR circuit of transmitter, at receiving side device features: first and second receiver decoders, receiver counter, first and second receiver keys, receiver phase-inverter, OR circuit of receiver, first and second gates.

EFFECT: increased concealment of information being transferred.

4 dwg

FIELD: mobile communication system which uses adaptive antenna array circuit with a set of inputs and a set of outputs.

SUBSTANCE: in accordance to the invention, first receiver computes receipt value with usage of compressed signal received from receipt signal, to generate receipt beam of first receiver and computes weight value of transmission with usage of computed weight value of receipt to generate transmission beam of second transmitter, generating check connection information, which includes weight value of transmission. First transmitter transmits check connection information to second receiver. Second receiver receives check connection information, and second transmitter determines weight value of transmission from check connection information received in second receiver, and generates transmission beam which corresponds to weight transmission value, to transmit the signal by applying transmission beam to the signal.

EFFECT: provision of system and method for transmitting/receiving in mobile communication system using two-stage method for creating a weight value.

6 cl, 12 dwg

FIELD: onboard radio-systems for exchanging data, possible use for information exchange between aerial vessels and ground-based complexes in radio communication channels.

SUBSTANCE: complex of onboard digital communication instruments contains two receiver-transmitters of very high frequency broadcasting range, two receiver-transmitters of high frequency range, interface switching block, control block, modulator-demodulator (modem), control and indication panel, frequency-separation device of high frequency range and frequency-separation device of very high frequency range.

EFFECT: increased interference resistance of data, reduced level of collateral radio emissions and fulfilled electromagnetic compatibility requirements.

1 dwg

FIELD: method and device for receiving data in mobile communication system using a circuit for adaptive generation of receiving beam weight.

SUBSTANCE: in accordance to the invention, mobile communications system receives a compressed signal, produced from received signal, and determines first value of error, using first circuit in clock point, and second value of error, using second circuit, which is different from first circuit in clock point. The system determines weight of application of first circuit in accordance to difference between first value of error and second value of error and generates third value of error, using the circuit which combines first circuit and second circuit, and determines the weight of the receiving beam, using compressed signal, third error value and output signal.

EFFECT: realization of the device and method for generation of receiving beam with minimal error value in mobile communications system.

2 cl, 9 dwg

FIELD: information technologies.

SUBSTANCE: invention relates to the radio communications and can be used in wireless communications system. Signals are transmitted with party check code usage with low density. Raise supporting party check matrix with low density is formed with the help of elements value extension in party check matrix with low density with the help of submatrix, which conforms a number of transmitting aerials. Specific transmitting signals are coded with usage of supporting raise party check matrix with low density. After that, coded signals are conversed seria/parallel and transmitted through transmission aerials.

EFFECT: improvement of data jam resistance in channel with noises while high-speed transmission.

36 cl, 16 dwg

FIELD: communication technologies.

SUBSTANCE: detecting techniques for close components of multi-beam distribution are described. The techniques are aimed at prevention of channel merging without relative position monitoring between each of diversity channel set. Displacement limits are defined for each diversity channel. Temporary tracing commands are suppressed. Such commands may displace diversity channels beyond their displacement limits. Displacement limits are dynamically updated, with displacement limits for each diversity channel defined according to displacement limits of adjacent diversity channels.

EFFECT: prevention of diversity channel merging; increase in system efficiency and capacity and decreased improper use of system resources.

12 cl, 10 dwg, 1 tbl

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