Start-stop communication system

 

The invention relates to the field of electric and radio communication and can be used in wired, radio, radio-relay and meteor scatter communication lines. To reduce the likelihood of false positives in the communication system prototype on the transmission side introduced a differentiating unit 13, on the receiving side is second to fifth elements OR, the divider 21 frequency (K+1)-th multiplexer 23, terminal block 25, the heat cost allocator 29, the first 30 and second 40 D-triggers, the second shaper 45 pulses, second 32 and third 37 triggers, the first 36 and second 43 digital Comparators, the fourth binary counter 35, the first to fourth 18, 39, 41, 44 elements And, second to fourth 33, 38, 42 elements and the generator 26 clock pulses. 4 Il.

The invention relates to electro - and radio and can be used in wired, radio, radio-relay and meteor scatter communication lines.

Known communication system with a transmitting side encodes the block synchronizer, temporary manipulator, the transmitter and synchroblog, and at the receiving side, the receiver agreed to a filter, a comparator, first and second storage devices, the decoder, the storage device and the sampling signal, synchroblog, the pulse shaper, motivate as the message of the binary symbols in parallel as a single source).

However, such a communication system may not be used in start-stop mode.

Closest to the technical nature of the proposed communication system is start-stop communication system [2] (the second option, S. 40), adopted for the prototype.

Diagram of the prototype system is shown in Fig.1, showing: 1 - sensor; 2, 27 - first and second threshold device (PU); 3, 17 - the first and the second storage device (memory); (4-1)(4-K) - multiplexers; 5 - binary adder; 6 - subtractive counter; 7 - transmitter; 8 - trigger; 9, 24, 25 - first, second and third binary counter;
10 - the item is NOT;
11 - element OR;
12 generator grids pulses;
13 receiver;
14 - amplitude detector (BP);
15 is a lowpass filter (LPF);
16 comparator;
18 - shift register;
19 - decoder;
20 - key;
21 - synchroblog;
22 - shaper pulses;
23 - shaper burst;
the 26 - drive;
28 - unit sample and hold signal;
29 - line.

Start-stop communication system prototype contains on the transmission side connected in series sensor 1, the first PU 2 and the first memory 3. To outputs of which are connected to the tires through the respective multiplexers (4-1)(4-K).

At the receiving side communication system prototype contains serially connected receiver 13 AD 14, low-pass filter 15, a comparator 16 and the second memory 17, the shift register 18 and the decoder 19, the output of which is an output device. Moreover ZU l7, the shift register 18, the decoder 19 are interconnected by a bus. In addition, connected in series key 20, synchroblog 21, the pulse shaper 22 and form the of the motor pulse 22 is connected to the counting input of the second binary counter 24 and a clock input of the comparator 16.

The third output of the pulse shaper 22 is connected with the second input key 20, the first input connected to the output of the LPF 15. Connected in series, the third binary counter 25, a memory 26 and the second PU 27, the output of which is connected with the control input of the decoder 19. The yield of synchroblog 21 is connected with the installation of the inputs of the third binary counter 25 and a memory 26.

The first output of the pulse shaper 22 is connected with the installation of the inputs of the second binary counter 24 and the sample and hold signal 28, a counter input of the third binary counter 25 and the gate inputs of shift register 18 and the drive 26, a signal input connected to the second input of the comparator 16 and the output of the sample and hold signal 28, a signal input connected to the output of the LPF 15 and the control input with the output of the comparator 16. The output of the second binary counter 24 bus connected to the information input of the second memory 17. The input of the receiver 13 is input receiving side of the communication system. The transmission and reception sides start-stop communication system are connected through the communication line 29.

Communication system-the prototype works as follows.

On the transmission side at the initial time t=0 on the T. At a random point in time at the output of the sensor 1 (seismic, acoustic, and so on), you may receive the signal a certain level. At excess of a certain threshold in block 2 at time t1formed a short pulse (Fig. 2A), which writes Km bit binary numbers (K1, m1: for example, number of sensors) in the memory 3, the generator 12, the first output of which form short pulses with a repetition period(Fig.2B) and the second output delay 3with the period T(2K+2)(Fig.2B) and translates the trigger 8 in the state "l".

The latter leads to the counter 9, which results in the S outputs of its digits (where S is the number per unit value log2(m+1)) signals are logic "0" on the buses arrive at the control inputs of multiplexers (4-1)(4-K) (m+1) informational inputs, the first of which (Fig.1 not shown) always outputs the signal of logic "0". The total number of Km output memory 3, which are the symbols of the message is divided into K groups of m symbols in each group (Shin ZU 3, third - [(K+1)2K]-th output . . . to (m+1)-th inputs -([(m-1)K+1]Km-th outputs. Thus, at time t1the output of all blocks 4 are signals of logical "0" (coming from their first inputs).

Binary adder 5 has two groups according To the inputs. On To the inputs of the second group (Fig.1 they not shown) always outputs a binary number equal to the decimal form two, so at the same time on one of its (K+1) outputs corresponding to the second low order binary numbers, a signal of logical "1". Differential output voltage circuit OR 11 if t-t1this number is recorded in the unit 6, the output retains its previous level "1" and opens the counting input that receives the pulses from the first output GSI 12 (Fig.2B). The second of them the cutting edge will reset the counter 6 and its output will be a logic level "0" until receipt of the third pulse (Fig.2G).

This will open the transmitter and its output will be generated signal is a radar pulse durationwith a certain carrier frequency. In the moment of action of the trailing edge of the first pulse at the second output, the logical signals, acting on their first inputs, arriving by bus from the output unit 3. In the adder 5 is a binary number in parallel will increase by two and then recorded the output pulse unit 11 in the counter 6. The time of occurrence of the zero signal at the output of the last (and the output signal of transmitter) depends on the value of the binary number in force at the second inputs of the blocks 4. If it is in decimal form is q[0q(2K-1)] it will appear at time intervals(2+q) relative to the first pulse of Fig.2B (Fig.2G - 3; K=2).

Similarly transfer the remaining K-bit binary numbers. When entering the last (m+1)-th pulse from the second output of the CVT 12 on even the input unit 9 at its output, a signal is generated that returns the trigger 8 in the initial state and the output of block 6 will be a signal of logical "1". The following signal at the output of the sensor 1 can appear only after a period of time greater than or equal to 2m(2+2K).

At the receiver side the received signal after filtering in the receiver 13, the amplitude detection unit 14 and filtering in low-pass filter 15 post the stroke unit 28. In synchroblog 21, which represents an optimal temporary meter signal position (figure.7.2, [3]), in the absence of interference is formed by a short pulse corresponding to the time of the maximum of the received filtered clock (Fig. 2D). In block 22 on it are two grids of pulses at the first output with a period T (as in Fig. 2B), the second with a period of(Fig.2E), and the third outputs the pulse duration m(2K+2)normally closed at this time, the key 20.

In block 23 are formed of bundles of short pulses (Fig.2ZH). The output pulse synchroblog 21 produces counter 25 and a memory 26, and the first pulse from the first output unit 22 (rear front) blocks 24 and 28. At the time of actions leading edge of the first pulse at the second output unit 22, the input signal of the comparator compares the level signal at its second input block 28 (in this case zero). If it is more recent, then the output of comparator 16 is formed by a voltage drop, which opens the input unit 28 and allows him to memorize the output level of the LPF 15.

This procedure is repeated 2Totime. Consequently lesego of the output signals of the LPF l5 during the time T-2. Binary K-bit counter 24 is designed to count the number of pulses entering from the second output unit 22. Whenever the output of comparator 16 appears a voltage drop readings To discharge it is read into memory l7. This allows you to fix the number of temporary positions most of the output signals of the LPF 15 on the time interval T-2.

At the time of actions leading edge of the second pulse (Fig.2B) the number recorded in the memory 17, is recorded in the block 18 and then moves on To discharge the output pulses of the block 23 (Fig.2ZH). Similarly processed output signal low-pass filter l5 at other time intervals of duration T-2. As a result, the arrival time of the last (m+1)-th pulse from the first output unit 22 in the block 18 is recorded information about temporary provisions the maximum level of the output signal of the LPF 15.

The decoder 19 explicitly converts the input binary number, resulting in a binary number in parallel form on its outputs in the absence of noise in the communication line coincides with the output symbols of the memory 3. The block 26 is designed to sum the output signals of block 28 in momentit it reset. At this point in time the output signal of the block 26 is read to the input PU 27 with a threshold and, if it exceeds the threshold, the output unit 27 is formed impulse, which reads the information of the decoder 19 on its outputs.

All the blocks included in this device are known. Shapers of packets of pulses, for example, can be obtained by using schemes with the contours of the shock excitation (see the book of L. M. Hollenberg. Pulse and digital devices. M: Communications, 1973, S. 224). The blocks 16, 17, 24 and 28 were used in [1].

However, this start-stop communication system has a greater chance of false positives (see figures in [2]).

The invention is directed to reducing the likelihood of false positives.

To eliminate this drawback in start-stop communication system containing on the transmission side connected in series sensor, the first threshold unit and the storage unit, the outputs of which tyres are connected with the first inputs To the multiplexers, the outputs of which are connected To the inputs of the binary adder, respectively, the output of which bus is connected to the information input of the subtractive counter, the output of which is connected to the transmitter input, the output of which is connected to the input line and to the second input of the first trigger, the second output of the first binary counter bus is connected with the second inputs To the multiplexers, in addition, connected in series, the first elements are NOT and OR, the output of which is connected to the enable input write code subtractive counter, and the input of the first element is NOT connected to the output of the first flip-flop, an input connected to the output of the first threshold unit, the counting input of the first binary counter is connected to the second input of the first element OR the output of the pulse generator is connected to a counter input of subtractive counter, at the receiving side includes serially connected receiver, an amplitude detector, a lowpass filter, and the first pulse shaper, the second and third binary counters, the second threshold unit and the shift register, the output of the first pulse shaper connected to the installation by the entrance to the third binary counter, and an output line connected to the input of the receiver, on the transmission side introduced a differentiating unit, an input connected to the output of the subtractive unit, and the output to the second input of the first element OR, at the receiving side introduced the first element And connected in series to the second element OR the frequency divider, and t is the United States the heat cost allocator, the first D-flip-flop, the fourth element OR the second trigger, the second element is NOT, the fifth element OR the fourth binary counter whose output bus connected to the inputs of the first and second digital Comparators and connected in series, the third trigger, the third element and the second element And, in addition, connected in series, the third element And the fourth element and the second D-flip-flop, the fourth element And the second shaper pulses and clock pulses, the output of which is connected to a clock input of the frequency divider and a counter input of the third binary counter.

Thus the output of the first digital comparator connected to the input of the third flip-flop. The output of the second element And is connected to the third input of the fourth element OR. The output of the second digital comparator through the fourth element And is connected to a second input of the fourth element OR. The fourth element is NOT connected with the second inputs of the first and fourth elements And.

The first input of the third element And is connected to the third output of the frequency divider and the second input of the second trigger. The second input of the third element And is connected to the output of the third trigger, set input connected to the output Pato is connected with the second inputs of the second and fifth elements OR. The output of the first element And connected to information inputs of the first and second D-flip-flops and counter input of the fourth binary counter.

The first meter inlet valve is connected to the output of the first pulse shaper and installation inputs of the first and second D-flip-flops, and the gate input of the second D-flip-flop is connected with the second output of the meter valve, the third output of which is connected with its installation entrance. The counting input of counter-distributor connected to the second output of the frequency divider. The fourth output of the meter valve is connected to the adjusting input of the second binary counter, the output of the overflow which is connected to the input of the second pulse shaper, the output of which is connected to the second input of the second element And. the output of the second D-flip-flop is connected to the fourth input of the fourth element OR. The second output of the third binary counter is connected to a second input of the third element OR. The third output of the third binary counter is connected with its forbidding entrance.

The first output of the third binary counter bus is connected with the control input of the (K+1)-th multiplexer, the output of which is connected to the input shift register. Log (K+1)-th multiplies frequency. The output of the third element OR is connected to a clock input of the shift register. The output of the filter the lower frequencies connected in series through the second threshold unit, the first element And the first pulse shaper is connected to the input of the second OR element.

In Fig.3 presents the proposed scheme start-stop communication system, where indicated:
1 - sensor;
2, 17, the first and second threshold block;
3 - memory block;
(4-1)(4-K) - multiplexers;
5 is a binary adder;
6 - subtractive counter;
7 transmitter;
8, 32, 37 - first, second, third trigger;
9, 22, 27, 35 - first, second, third and fourth binary counter;
10, 33, 38, 42 - first, second, third and fourth element NOT;
11, 20, 28, 31, 34 - first, second, third, fourth, and fifth element OR;
12 - pulser;
13 is a differentiating block;
14 receiver;
15 - amplitude detector (BP);
16 is a lowpass filter (LPF);
18, 39, 41, 44 - first, second, third and fourth element And;
19, 45, the first and second pulse shaper;
21 is a frequency divider;
23 - (K+1)-th multiplexer;
24 - shift register;
25 - terminal block;
26 - clock (GTI);
29 - the heat cost allocator;
(4), the outputs of which are connected To the inputs of the binary adder 5, respectively, which output bus is connected to the information input of the subtractive counter 6, the output of which is connected to the inputs of the transmitter 7 and the differentiating unit 13. The output of the transmitter 7 is connected to the input of the communication line 46. In addition, it contains serially connected first trigger 8 and the first binary counter 9, the first output of which is connected to a second input of the trigger 8, the second output of the binary counter 9 bus is connected with the second inputs of multiplexers (4-1)(4), connected in series, the first elements 10 OR 11, the output of which is connected to the enable input write code subtractive counter 6.

At the entrance of the first element 10 connected to the output of the first flip-flop 8. The output of pulse generator 12 is connected to a counter input of subtractive counter 6. The output of the differentiating unit 13 is connected to the counting input of the first binary counter 9 and the second hamnoy side communication system includes serially connected receiver 14, HELL 15, low-pass filter 16, the second threshold unit 17, the first item 18, the first pulse shaper 19, the second element OR 20, the frequency divider 21 and the second binary counter 22, the output of which bus is connected to the input of the (K+1)-th multiplexer 23, the output of which is connected in series through the shift register 24 and terminal block 25 connected to the first input of the third element OR 28, the output of which is connected to a clock input of the shift register 24. The output GTI 26 is connected to a clock input of the frequency divider 21 and a counter input of the third binary counter 27, the first output of which bus is connected with the control input of the (K+1)-th multiplexer 23. The second output of the third binary counter 27 is connected to a second input of the third element OR 28. The third output of the third binary counter 27 is connected with its forbidding entrance. And the installation of the entrance to the third binary counter 27 is connected to the output of the first pulse shaper 19.

In addition, connected in series, the heat cost allocator 29, the first D-flip-flop 30, the fourth element OR 31, the second trigger 32, the second element is NOT, the fifth element, OR 34 and the fourth binary counter 35, the output of which bus is connected to the inputs of the first 36 and second 43 digital Comparators. The second output scetchy entrance of the fourth element OR 31. The third output of the meter valve 29 is connected with its installation input and a fourth output setup input of the second binary counter 22. The first meter inlet valve 29 is connected with the installation of the inputs of the first 30 and second 40 D-triggers, as well as with the output of the first pulse shaper 19. The counting input of counter-distributor 29 is connected with the second output of the frequency divider 21. The information inputs of the first 30 and second 40 D-flip-flops connected to the output of the first element And 18 and a counter input of the fourth binary counter 35. The output of the first digital comparator 36 connected in series through the third trigger 37 and the third element is NOT 38 is connected to the first input of the second element And 39. The output of the second digital comparator 43 through the fourth element And 4 is connected to a second input of the fourth element OR 31, the third input of which is connected to the output of the second element And 39.

The output of the overflow of the second binary counter 22 via a second pulse shaper 45 is connected with the second input of the second element And 39. The output of the fifth element OR 34 is connected with the installation of the entrance of the third trigger 37, the output of which is connected to a second input of the third element And 41, the first input connected to W is tovim input terminal unit 25 and the input of the fourth element 42, the output of which is connected with the second inputs of the first 18 and fourth elements 44 And. the Second output terminal unit 25 is connected with the second inputs of the second 20 and the fifth elements 34 OR.

Start-stop communication system operates as follows.

On the transmission side in the initial time (t=0) at the output of the trigger 8 applies a signal of logical "0" and the output of block 6 logic "1" and the transmitter 7 is not working. At a random point in time at the output of the sensor 1 (seismic, acoustic, and so on) generates a signal of one level or another. At excess of a certain threshold in block 2 at time t1formed a short pulse (Fig.4A), which writes Km-bit binary number (K>1, m>1, for example, non sensor) in block 3 and moves the trigger 8 in the opposite position. This leads to nullification of the block 9, which results in the S outputs of its digits (where's the nearest larger to log2(m+1) number of signals of logic "0" on the buses arrive at the control inputs of multiplexers (4-1)(4-K) (m+1) informational inputs, the first of which (Fig.3 not shown) always outputs the signal of logic "0".

The total number of K(4-K) connect one of the 1stK-th output unit 3, to the third (K+1)-th2K-th output to the (m+1) inputs [(m-1)K+1] -thKm-th. Thus, at the point in time at the output of each unit 4 applies a logic signal "0" is received from the first input binary adder 5 has group access To inputs. On To the inputs of the second group (Fig.3 they not shown) always outputs a binary number equal to the decimal form two, so in the same moment of time only one of its (K+1) outputs corresponding to the second low order, a signal of logical "1".

Obtained at the output of block 5, the number is written to the block 6 by the voltage drop from the output trigger input through the elements 10 OR 11 and the input to the writing unit 6. Its output signal remains the same and offer the counting input that receives the pulses from unit 12 (Fig.4B) with a period of repetition. The second of these will produce the zeroing unit 6 and its output level is set to a logical "0" until receipt of the third pulse (Fig. 4B). This opens peredatochnoi carrier frequency, and the output unit 13 at the time of the positive front output pulse unit 6 (Fig.3b) is a short pulse, which sets the least significant bit of the block 9 in one state, and the outputs of block 4 will be the logical signals acting on their second inputs, arriving by bus from the outputs of the block 3.

In block 5 is a binary number in parallel will increase by two and then recorded the output pulse unit 11 unit 6. The time of occurrence of the zero signal at the output of the last (and the output signal of the transmitter 7 depends on the value of the binary number in force at the second inputs of the blocks 4. If it is in decimal form is q(0q2K-1), it will appear at time intervals (2 +q)since the end of the clock (Fig.4B - 4; K=2). Similarly transfer the remaining K-bit binary numbers. When entering the last (m+1)-th pulse from generator 12 to the counting input of block 9 at its output, a signal is generated that returns the trigger 8 in the initial state and the output of block 6 will be a signal of logical "1". The following signal at the output of the sensor 1 can peewits the mg>.

At the receiver side the received signal after filtering in the receiver 14, the amplitude detection unit 15 and filtering in low-pass filter 16 is fed to the input of the second unit 17. In the absence of noise at its output torque is exceeded signal threshold is generated pulse with a logic level "1" and a duration close to the value ofon the second input of the first element And 18 applies a signal of logical "1" at the output of the element OR 31 logical "0" and the output of the trigger 32 logical "1". Therefore, the first pulse of the received signal (clock pulse) (Fig.4G) which passes through the block 18 and the output of block 19 on its front edge is formed by a short pulse (Fig.4D), which runs counter dispenser 29 and carries through the block 20, the reset of the frequency divider 21. On the first, second and third outputs of the latter are formed meanders with periods of pulses, respectively, equal to, 0,5and 16by dividing the frequency of the GTI 26, is equal to 32/and on the fourth the meter outlet valve 29 generates a pulse duration of 0.5with a delay relative to the first pulse of Fig.4D

This pulse produces a reset and permission to count pulses in the block 27, coming from the GTI 26. The resulting signals To the discharge unit 27, the current through the bus on the control inputs of the multiplexer 23, the data To the discharge unit 22 in turn fed to the input of shift register 24 with (K+1)m digits on the clock input of which through the block 28 receives the pulses from the output of the first discharge unit 27. Upon receipt of (K+1)-th pulse with the GTI 26 to the input of the last signal from the second output prohibits the counting of the remaining pulses until receipt of the next pulse from the output unit 19.

Similarly is the determination of the temporal position of the remaining (m-1) of the information pulses. In the absence of noise, as before, after receiving the last of them on the output element And 41 forming a positive differential voltage (signal "message accepted"), which launches the target unit 25 (for example, EDCM). At its first output generated clock pulses with a certain frequency, Schetyna "reset" through the unit 20 clears the block 21 and through the block 34 block 35 and the trigger 37.

When the interference signal "message accepted" will appear if there is at the same time the following events: at time intervals Tn>8to receive timing (start pause) and after the last m-th pulse messages (stop pause) will not appear false pulses at the output of block 17, the number of pulses at its output N will be equal to (m+1), there will be an overflow of the counter 22, the duration of the received pulses is less than, for example, 2and protective pause more, for example, 1.5. Control the duration of the start pause is performed by block 21.

If, at the time of the first pulse output unit 19 on the third output unit 21, the signal level is equal to a logical "1" (which indicates that Tn>8), it means that there was a reset of the trigger 32 and through the elements NOT 33 OR 34 and the counter 35, which will begin counting the number of pulses coming from the output of block 18. When N - (m+1) at the output of block 36 will appear impulse, which will set the trigger 37 in one state and opens the item And 41.

If polyetherether about the presence of the stop pause), the output element And 41 will receive a positive pulse to allow incoming messages, and the output unit 42, the signal of logic "0" prohibiting the transmission of signals through the element And 18. Dr. triggers 30 and 40 are designed to control the pulse durations of the message. Output pulses of the block 19 and they are set to zero; at their second input pulses from the output of block 18, and the third with the first (Fig.S) and the second (Fig.4I) exits the heat cost allocator 29, respectively; on the trailing edge of the latter is blocking it until the arrival of the next pulse from the output of block 19 (Fig.4K).

If there is no overlap in time of the pulses acting on the first and second of their inputs, their state does not change. In the absence of the start of the pause will not be a count of pulses in the block 35, N will be less than (m+1), the output element 36 (the second input unit 39) there will be a signal of logical "1" and, if this happens the overflow block 22, the outputs of block 45, block 39 and the OR element 31 will receive a pulse that sets the trigger 32 to its original state.

The same thing happens when overflow if N - (m+1). The same signal will appear on its output, if there is overlap of the pulses in at least one of the leads to the appearance of the pulse at the output of block 43, through outdoor output signal of the block element 42 And 44 and the element OR 31 will be received at the first input of the trigger 32.

Thus, the proposed start-stop communication system can significantly reduce the chance of false positives.

When practically used values of the probability of correct reception of the message set to 0.95-0,999, the probability of false positives in her is of the order of 10-25-10-15. In the prototype in the best case you can reach the value of this probability is of the order of 10-10.

All blocks included in the communication system, devices are known. Binary adder 5 can be performed on the chip IN [4], the counters 22 and 27 in IE [4], the counter 29 to A [4], digital Comparators 36, 43 on IM [4].

Sources of information
1. RF patent 2103827, H 04 J 11/00, H 04 Q 11/00.

2. C. I. Nikolaev, B. Volobuev, V. I. Grandfather. About the noise immunity of m-ary signals with start-stop sending messages. Telecommunications, 1, 2001, S. 38-41, (LLC "Science and technology", M., 2001).

3. Y. S. Lezin. Introduction to theory and technique of radio systems. M.: Radio and communication, 1986.

4. E. A. Zeldin. Digital integrated circuits in information-measuring equipment. HP: Energoizdat, 1986.

 

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FIELD: communications engineering.

SUBSTANCE: proposed band selection method for mobile orthogonal frequency division multiple access communication system includes following steps to classify procedures of band selection between sending end and receiving ends with respect to original band selection process, passband width selection process, and periodic band selection process: determination of source band selection code (SC)number for source band selection process; SC number to request passband width for passband width request selection process and periodic SC number for periodic band selection process; determination of periodic SC deferment value in compliance with periodic SC number, and transmission of source SCs, passband width request SC, periodic SCs, and periodic SC deferment values on receiving ends.

EFFECT: minimized time for band selection access.

22 cl, 3 dwg, 4 tbl

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