Cascade integral dynamic memory "sibl"

 

The invention relates to computing. Effect: simplified computer-aided design, increased functionality. Integral cascade module dynamic memory is made in the form of a trigger and contains cascading links (KS) of the integrated dynamic memory modules (TIR) and the decoder (D), and also contains input short circuit, consisting of a single TIR, made of two executable semiconductor switches (IPC), having at least one intermediate input bus (W) of the controlled signal, two output intermediate W controlled signal and two twin W control signal, each associated with one of the mentioned Institute. Each of the intermediate output managed another signal TIR in each SC is connected to the input of the intermediate W controlled signal TIR next SC and IEC output short circuit interconnected to D. 5 Il. table 2.

Integral cascade module dynamic memory relates to the field of computer technology and integrated electronics, namely the logical schemas, different definitions of a logical operation, in particular to circuits in which the output signal appears when vhodni logic - the trigger amplifier (see U.S. patent 4843264, IPC G 01 R 19/00 from 1989 ), contains the trigger on two inverters made by CMOS transistors cross-connected to the same conclusions of the pair of transistors of one conductivity type to the first bus of the power source, the same conclusions of the pair of transistors of the other conductivity type connected to the respective first and second inputs of the node activation trigger, the output of which is connected to the second bus of the power source, the node reset trigger two transistors, conclusions drain-source merged with the same conclusions of the respective transistors of the same conductivity type, the trigger inverters connected to the first bus of the power source, two-rail data bus connected to the same input node activation trigger bus synchronization, connected to the control inputs of the node reset trigger outputs trigger inverters are paraphase outputs of the device.

A disadvantage of the known basic amplifying element differential dynamic logic trigger amplifier are low functionality, in particular n is the train low speed and high power consumption.

Known also adopted for the prototype of the basic amplifying element differential dynamic logic (see RF patent 2154338, IPC H 03 To 19/06, publ. 10.08.2000) that contains the trigger on two inverters made by CMOS transistors cross-connected to the same conclusions of the pair of transistors of one conductivity type to the first bus of the power source, the same conclusions of the pair of transistors of the other conductivity type connected to the respective first and second inputs of the node activation trigger, the output of which is connected to the second bus of the power source, the node reset trigger two transistors, conclusions drain-source merged with the same conclusions of the respective transistors of the same conductivity type, trigger inverters connected to the first bus of the power source, two-rail data bus, connected to the same input node activation trigger bus synchronization, connected to the control inputs of the nodes activate the trigger and reset trigger outputs trigger inverters are paraphase outputs of the device, as well as an additional MOS transistor, and the node activation of t the second discharge circuit, input findings which are the corresponding inputs of the node activation trigger, and their outputs connected to the output node activation trigger, the conclusions of the drain-source of additional N-channel MOS transistor is connected to the inputs of the node activation trigger, and its gate connected to the first bus of the power source, the General conclusions of series-connected transistors of the node activation trigger connected to the corresponding two-rail information the tires, and the gates of N-channel MOS transistor based circuits are connected with the control input node activation trigger.

A disadvantage of the known basic amplifying element differential dynamic logic are low functionality, in particular the load capacity, the complexity of the automated designing of nodes based on a given item, as well as low performance and high power consumption.

The technical task of the invention is to simplify computer-aided design of sites, increase functionality with the aim of using it to control various processes of any length, increasing performance while reducing kaskady module dynamic memory made in the form of a trigger, according to the invention, contains a linked cascading units, for example three, of which the first and the last cascade links are respectively the input and output of the cascade links, the average cascade link is an intermediate cascade link, and the input of the cascade link contains one module dynamic memory, which consists of two executable semiconductor switches, with one total intermediate input bus controlled signal, two output intermediate tyres controlled signal and two separate tire control signal, each associated with one of the above executable semiconductor switches, the number of dynamic memory modules each subsequent cascade link is equal to the number of output intermediate tyres managed previous signal cascade link, with each cascade element contains one separate bus control signal for each executable semiconductor key, and executable semiconductor switches of the output cascade link switched by using the output of intermediate tyres in the controlled signal to the additionally installed device, the SGAs is cnyh tire of the controlled signal to the next module of dynamic memory in each cascade element is connected to the input of the intermediate bus controlled signal subsequent module dynamic memory subsequent cascade link.

Between the features and achieved technical result is the following causal link.

The present invention Integral cascade module dynamic memory", in contrast to the known analogs and prototypes, will greatly simplify automated control nodes and to reduce the cost by reducing the number of dynamic memory modules made in the form of a trigger, compared to the standard and well-known memory devices and due to the homogeneity of the dynamic memory modules. In addition, the present invention allows to increase the functionality of the integrated cascade module dynamic memory due to the possibility of the cascade building of the integrated dynamic memory modules, and also use it to control various processes of any length due to the separation of the managed and control signals. Due to the homogeneity of the integral cascade modules dynamic memory and their low resistance, expressed in resistance executable semiconductor switches, increasing performance while reducing noise and loss that is jut use it to control various processes of any length with a slight loss of power and high noise immunity, because regardless of Castagnoli (number of cascading links) in the proposed cascade integral module of dynamic memory used by homogeneous elements of integrated modules dynamic memory, which also reduces the complexity of the product and facilitates automated design of nodes which increases the cost.

According to the applicant's information, the set of essential features of the claimed invention "Integral cascade module dynamic memory" is not known from the prior art, which allows to make a conclusion about conformity of the invention, the criterion of "novelty."

According to the applicant, the essence of the claimed invention is not obvious from the prior art, since it is not detected above the impact on the technical result achieved is a new property of an object is the totality of characteristics that differ from the prototype of the claimed invention, which allows to make a conclusion about conformity of the invention: "Integrated cascade module dynamic memory" the criterion of "inventive step".

The set of essential features that characterize the invention, can be reused in the manufacture of integral kaimosi by simplifying the automated designing of nodes, increase functionality, improve performance and increase reliability, increase performance, which allows to make a conclusion on the compliance of the claimed invention, the criterion of "industrial applicability".

The essence of the invention is illustrated by a specific example.

In Fig. 1, 2, 3 shows the module dynamic memory, where Fig.2 and 3 are presented with the image reduction Fig. 1 for the convenience of the views of figures 4 and 5, respectively.

In Fig. 4 shows the integral cascade module dynamic memory consisting of three cascaded sections, constructed according to Fig.2.

In Fig. 5 shows the integral cascade module dynamic memory, consisting of six cascading links, constructed according to Fig.3.

Integral cascade module dynamic memory according to the first example (Fig. 4) made in the form of a trigger (A. C. Partin, Popular about digital circuits. Sverdlovsk: Medium-Ural publishing house, 1989, 40 C.) and contains one input cascade level 1 and one output cascade level 2. This integral cascade module dynamic memory consists of three cascaded links 3, 4, 5. The first cascade level is simultaneously input the m example integral cascade module dynamic memory consists of three above-mentioned cascade links 3, 4, 5, which contains seven modules dynamic memory 6, 7, 8, 9, 10, 11, 12, consisting of homogeneous modules, i.e., having the same structure. The first cascade level 3 contains one module dynamic memory 6, in the second cascade level 4 there are two module dynamic memory 7 and 8. In the third stage 5 there are four module dynamic memory 9, 10, 11, 12. Each of the dynamic memory modules 6, 7, 8, 9, 10, 11, 12 contains two executable semiconductor key 13 and 14, one intermediate input 15 and two intermediate output bus 16, 17 of the controlled signal and two separate bus 18 and 19 of control signals, each associated with one of the above executable semiconductor switches 13 and 14 of the module dynamic memory in cascade link. Each of the cascaded links (Fig.4) 3, 4, 5 contains (for convenience, is shown with a single item 20) separate bus 20 control signals for all executable semiconductor switches integral data members cascading links.

In the first cascade level 3 on separate bus 20 a control signal to executable semiconductor switches 13 and 14 receives the control currents X1-1 and X1-2. In the second cascade level 4 separate bus 20 a control signal to espanaside 20 a control signal to executable semiconductor switches 13 and 14 receives the control currents X4-1, X4-2, X5-1, X5-2, X6-1, X6-2, X7-1 X7-2. Executable semiconductor switches 13 and 14 are interconnected at the output link 2 to the decoder 21 (Integrated circuits Handbook, edited by B. C. Tarabrina, M. : Radio and communication, 1984, pp. 493-494), enabling a module dynamic memory. Each of the output intermediate tyres in the controlled signal, 16 and 17 of the next module of dynamic memory in each cascade element is connected to the input of the intermediate bus controlled signal subsequent integral dynamic memory of the next cascade level.

The work described above integral cascade module dynamic memory is as follows.

Denote the presence of the control currents in the tire 20 of the first, second and third cascade links respectively, the logical unit X1-1=1 and so on up to X7-2=1, and the lack of control of the currents in the separate bus 20 of the control signal of the first, second and third cascade links respectively, the logical zero X1-1= 0 and so on up to X7-2=0. Thus, when the control signal on at least one of X1-1 and X1-2, the control current supplied to at least one executable semiconductor key module dynamic memory 6 of the first cascade level 3, and up keys the following cascading links. The way in which control signals in separate tire 20 on executable semiconductor switches of the dynamic memory modules all cascading links allow you to get all 256 combinations of values of dynamic memory reflected in the table 1.

Integral cascade module dynamic memory according to the second example (Fig. 5) contains one input cascade level 1 and one output cascade link 2 respectively of the first cascade level and the last cascade link. In this example, the integral cascade module dynamic memory consists of six cascading links 3, 4, 5, 6, 7, 8, containing sixty-three modules of dynamic memory consisting of homogeneous elements, i.e., having the same structure. The first cascade module 3 contains one module dynamic memory. The second cascade level 4 contains two modules of dynamic memory. The third cascade link 5 contains four modules of dynamic memory. Fourth cascade link 6 contains eight modules of dynamic memory. Fifth cascade link 7 contains sixteen modules of dynamic memory. Sixth cascade link 8 contains thirty-two module dynamic memory. Each of the sixty-three modules of the dynamic memory with the controlled signal, two intermediate output bus 16 and 17 of the controlled signal and separate bus 18 and 19 of control signals, each of which is connected with one of the above executable semiconductor switches 13 and 14 of the module dynamic memory in cascade link. Each cascade link 3, 4, 5, 6, 7, 8 contains separate bus 20 control signals, one for each executable semiconductor key of all modules of the dynamic memory. The way in which control signals in separate tire 20 on executable semiconductor switches of the dynamic memory modules all cascading links allow you to get all of 1,81019combinations of values of dynamic memory, as reflected in table 2 (part 1 - the beginning of part 2 - continued).

The work described above integral cascade module dynamic memory is similar to the first example.

The present invention Cascade integral dynamic memory" will greatly simplify computer-aided design of nodes and to reduce the cost, improve the functionality of the module, use it to control various processes of any length, to improve performance when ignoreme the cascade AUX module dynamic memory made in the form of a trigger that contains a cascading links from the integral modules of a dynamic memory and a decoder, characterized in that it contains the input cascade link consisting of a single module of dynamic memory consists of two executable semiconductor switches having one intermediate input bus controlled signal, two output intermediate bus controlled signal and two separate bus control signal, each associated with one of the above executable semiconductor switches, each of the output intermediate tyres in the controlled signal to the next module of dynamic memory in each cascade element is connected to the input of the intermediate bus controlled signal module dynamic memory subsequent cascade link and executable semiconductor switches of the output cascade link is switched to the decoder.

 

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