Storage device, multiple memory devices and a method of manufacturing a memory device

 

The invention relates to a storage device of a high integration degree and method of their manufacture. The proposed storage device and the manufacturing method, the device contains a memory node in which you put the charge through the configuration of the tunnel junction having the energy band profile, which contains a relatively wide size barrier component with a relatively low height of the barrier and at least one relatively narrow size barrier component with a relatively large height of the barrier. Also offered a variety of storage devices and the array of storage devices that are formed in a matrix of memory cells on a common substrate. The result is that you can increase memory by reducing the size of devices and higher reliability. 7 C. and 57 C.p. f-crystals, 34 ill., table 1.

The technical field to which the invention relates the Present invention relates to a storage device, capable of integrating a very high degree to ensure a matrix of memory cells.

Background of the invention In conventional semiconductor memory devices, one bit of information is represented by a deficiency of N electrons, and "0" is represented by the condition of neutral electric charge. In a typical 16-megaritual dynamic storage device, random access (ZUPU) the number of electrons N is about 800000. To increase the amount of memory individual memory you want to do less, but this cannot be achieved simply by reducing the normal memory cell, since there is a lower limit for the value n. the Number of electrons N is limited by the need to coordinate the leakage current of the cell, the internal noise and the effect of the incident alpha particles, and these factors are not reduced in proportion to the reduction of the area of the memory cell. It can be estimated that N must be more than 130000 16-Gigabit ZUPU, that is, the ratio is approximately 6 times less than for the 16-megabit ZUPU. However, the cell size required for 16-Gigabit ZUPU, must be reduced by three orders in magnitude compared to the 16-megabit ZUPU and, consequently, reduced the cell size cannot accommodate the number of electrons required for satisfactory operation. Trying to keep the value of N large enough, investigated the three-dimensional capacitors have cutouts or multi-level structures with film capacitors, available is the performance turned out to be extremely difficult. In addition, significantly increased energy consumption, as during storage must be updated relatively large number N of electrons in the cells, and this has tended to decline as the scale of the device is minimized.

Another type of storage device that demonstrates the non-volatile characteristics, known as flash memory. In such a device approximately 105electrons injections in the floating gate through the tunnel junction, usually formed of SiO2with a thickness of about 10 nm. Stored charge produces a field which affects the electric current in the area between drain and source. Charge or is written to the floating gate, or erased, by applying an electric field across the gate. During cycles of erasing and writing is very high electric field, and in the film of SiO2destroyed, limiting the service life of the storage device a predetermined number of cycle of erase-write, usually equal to about 105cycles. Moreover, the time of erase-write is usually several milliseconds, four order of magnitude lower than with conventional ZUPU. Such a bad characteristic of the ordinary to ensure storage devices working with small, precise quantities of electrons, known as single-electron memory device. Single-electron memory device described in the application of the same applicant for the patent PCT/G93/02581 WO-A-94/15340). The exact number of electrons supplied to the memory node or leaves it through mnogokanalnyy transition under the control of the applied voltage of the shutter, and the electronic state of the memory node is determined using an electrometer. However, the drawback is that for each memory node requires a significant number of schemes, and the device is currently only works at low temperature, below the temperature of liquid helium at 4.2 K. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai and K. Seki in "Transactions on electron devices", Institute of electrical and electronics (IEEE), September 1994 , T. 41, 9, pp. 1628-1638, and K. Yano, T. Ishii, T. Sano, T. mine, F. Murai and K. Seki in 1996 at the "international conference on solid-state circuits". Institute of electrical and electronics (IEEE), 1996, FR 16.4, page 266, proposed and demonstrated another single-electron memory device. The device uses police the th number of electrons stored in the grain structure of the polycrystalline silicon film. The memory size is relatively small compared with the structure in the above-mentioned patent application PCT/G93/02581, and it is able to operate at room temperature. In addition, the memory shows several advantages compared to conventional flash memory, with less time erasing records from a small number of stored electrons, and operational service life is improved by the fact that use low-voltage tunneling injection and no injection of electrons in the high field. However, reading the stored information for a relatively long, of the order of several microseconds, since it is necessary to have a sufficiently high resistance between source and drain in order to guarantee a long storage time of the electrons in the granules.

Other design described S. Tiwari, F., Rana, X., Hanafi, A. Hartana, E. F. by Crabb and K. Chen in the "Journal of applied physics", March 4, 1996, vol 68, 10, pp. 1377-1379, S. Tiwari, F., Rana, K. Chan, L. Shi, and X. Hanafi in the "Journal of applied physics", August 26, 1996, volume 69, 9, pp. 1232-1234, and H. AI. Hanafi, S. Tiwari and AI. By Ken in "Transactions on electron devices". Institute of electrical and electronics (IEEE), September 9, 1996 , T. 43, 9, pp. 1553-1558. This is istwa. Electrons injections in silicon nanocrystals, which have a size of 5 nm from the silicon substrate through a thin tunnel oxide layer with a thickness of about 1.1-1.8 nm. Stored electrons shift the threshold voltage of the transistor. Reading stored information is relatively short, of the order of several tens of nanoseconds, since the channel of the transistor is a high electron mobility. Cycle durability for recording and reading information significantly improved compared with the conventional flash memory device. However, the read time is unsatisfactory high, on the order of a few milliseconds, because the alignment of the conduction adversely to tunneling of electrons from the nanocrystals in the bulk silicon.

Other storage device that operates in accordance with the principles of the flash memory disclosed in "Electrically reprogrammable memory that uses the structure of the dual electron injector" D. J. Di Maria, C. M. De Meyer and D. Y. Dong, "Journal of electronic devices". Institute of electrical and electronics (IEEE), vol EDL-1, 9, September 1980, pages 179-181. In this device, the conductivity of the area between the drain and itoko the shutter. However, the disadvantages of this device are that it has a slow time, read-write, the order of milliseconds, and that the service life of tunnel junction is limited because, as in the conventional flash memory, used injection high field Fowler-Nordheim. A similar device is described in U.S. patent 3878549, issued to S. Yamazaki.

Summary of the invention in order To overcome these problems and disadvantages, the invention provides a storage device containing a channel for charge carriers, a node for storing charge to form a field that changes the conductivity of the channel, and the configuration of the tunnel, through which charge carriers tunneling in response to this voltage to be remembered in the node where the configuration of the tunnel shows the energy band profile, which contains a relatively broad terms of the size of the element with a relatively low barrier height of the barrier and at least one relatively narrow from the point of view of the size of the barrier element with a relatively large height of the barrier.

The invention allows to optimize for memory device during recording, reading and erasing.

Regarding the Yes in the node. Wide barrier element can be increased or decreased by choice so that the charge can tunnel through the relatively narrow barrier element to be written to or erased from a node.

The profile element energy zone, which has a relatively large height of the barrier may be provided using element with a width of 3 nm or less. You can include many elements of a relatively high barrier and can appropriately to ensure the configuration megatonnage transition.

The configuration of the barrier can be done using a number of different ways. It may include alternating layers of relatively conductive and electrically insulating material, where the layers together to provide a relatively large item small barrier height of the energy band profile, and a separate insulating layers provide the elements of a relatively high barrier. The alternating layers may include polycrystalline silicon and silicon nitride, respectively, although it is possible to use other materials.

Alternatively, the configuration of the barrier may contain the configuration of the barrier Schottky with alternating layers of electrically conductive material and poluprovodnikovyye and channel. A node can contain multiple conductive islets. In the alternative device Islands distributed in the barrier configuration and can give rise to elements of relatively low barrier energy band profile due to their energy charge. Islands can have a diameter of 5 nm or less. They can be placed in layers separated by insulating material.

Islands can be created using several methods. They may contain nanocrystals of semiconductor material. Alternatively, they can be formed from metal, for example, by spraying, so as to distribute them in the electrically insulating metal oxide. Alternatively, the Islands may contain particles deposited from a liquid suspension of metal or semiconductor particles.

The configuration of the tunnel junction can be positioned between the channel and the control electrode so that the voltage on the gate electrode can be controlled by the amount of charge that tunnels in the storage node charge. In another corresponding to the invention, the configuration includes a gate electrode for the application of additional fields to the configuration of the barrier charge is to ranicoats by the blocking effect of the pendant, a discrete number of electrons.

When using the configuration of the tunnel shows the locking range of voltages in which the charge carrier tunneling in the node is blocked, and may be provided with a management tool to increase or decrease the range of blocking voltages to control the amount of charge stored in the node. The amount of charge which can be stored in the node, can be limited by many discrete electronic States. The management tool can act to raise and lower the locking range of voltages, to be able to show only the selected one of the States in the node.

Alternatively, the control may operate to change the width of the locking range of voltages.

Corresponding to the invention a storage device suitable for the manufacture of a number of memory cells in a matrix of rows and columns on a common substrate.

Data can be selectively read from each cell separately, and new data can be written into the cell or you can update the recorded data. The matrix of memory cells may include a line reading for the detection of current, about the mi configuration memory cells to their respective columns, circuit pre-charging intended for pre-charging line read line read, removing the battery level depending on the stored charge in the storage node charge of a particular one of the cells in its column, read with voltage readout applied to the respective lines of words, the schema is read-write for transmission-level voltage line are read into the appropriate line of column output in response to the voltage level at the data line to provide output data corresponding to the stored data in the cell is read, and the data update tool for the application of a voltage of a write to a line of words read out of the cell so that that data corresponding to the voltage level at the data line is written back in a matter before the cell. This matrix can also include a means for changing the voltage level on the data line after the action schema is read-write under the influence of the input data to be written into the cell, so that the input data is written into the cell.

The preferred scheme for the matrix may be formed on a common substrate with the memory cells and the source and drains of the transistors in the peripheral Shaw and origins in the cells of the matrix.

The invention also includes a method of manufacturing a memory device that includes a channel for charge carriers, a node for storing charge, which changes the conductivity of the channel, and the configuration of the tunnel, through which charge carriers tunneling in response to this voltage, so that will be remembered in the node, and the method includes the configuration tunnel junction so that it shows the energy band profile, which contains a relatively wide size barrier component with a relatively low height of the barrier and at least one relatively narrow size barrier component with a relatively large height of the barrier.

Brief description of drawings in order that the invention more clear, now, as an example will be described of its variants, with reference to the accompanying drawings, in which; Fig. 1 is a schematic representation of the first type corresponding to the invention of the storage device.

Fig. 2 is a graph of current-voltage characteristics shown in Fig.1 barrier structure 2.

Fig. 3 is a schematic representation of an electrical circuit matrix configuratie shown in Fig.3 scheme of the matrix memory.

Fig. 5 is a view in section, taken along the line a-a' of Fig.4 through the memory cell M11.

Fig.6 is a cross-section of the cell M11Fig.4, taken along the line B-B'

Fig. 7 illustrates a method of reading and writing data in a separate cell in the matrix memory.

Fig. 8 is a graph of voltage V of the memory node 1 storage device, constructed relative to the voltage VSYon the source and the drain of the device while recording a binary "0" (Fig.8A-8d) and write binary "1" (Fig.8E-8h).

Fig. 9 is a plot of the current of the drain-source of the ISYfrom the control of gate voltage VXfor a binary "1" and "0" stored in the memory node 1.

Fig. 10 is a more detailed view in section of the barrier structure 2 of the storage device.

Fig. 11a illustrates the energy diagram of the conduction barrier structure 2, when memorizing charge carriers in the memory node 1.

Fig. 11b illustrates the corresponding energy band diagram when the charge carriers are written in the node 1 by tunneling from the control electrode X.

Fig. 12A-12f are views in transverse section corresponding to line a-a' in Fig. 4, illustrating different manufacturing floor the market barrier of a Schottky, which alternatively can be used in a storage device.

Fig.14 is a schematic cross section of an alternative barrier structure that includes conductive Islands nanometric scale, for the third variant implementation of the storage device in accordance with the invention.

Fig. 15 illustrates the number of production steps for the manufacture of the invention a storage device in which silicon crystals nanometric scale distributed around the SiO2.

Fig. 16A-16f illustrate the process steps for the formation of an alternative implementation in which the barrier structure includes gold particles of nanometric scale deposited from a colloidal solution.

Fig. 17 is a schematic representation of the second type corresponding to the invention of the storage device.

Fig. 18a and 18b are graphs of current I flowing through the barrier structure 2 of Fig. 17, as a function of voltage VYapplied to the contact Y in the presence (mode enabled) voltage applied to terminal X, and in the absence of such voltage (mode, "off").

Fig. 19 is Uwe is iagram energies in the conduction band for shown in Fig.19 barrier structure.

Fig.21 is a schematic top view of a matrix of memory cells including a storage device shown in Fig.17 the second type.

Fig. 22 is a view in transverse section taken along the line a-a' of Fig. 21.

Fig. 23 is a view in transverse section taken on line-In' Fig. 21.

Fig. 24 is an electrical schematic diagram shown in Fig. 21, 22 and 23 of the configuration memory cells together with built-in drivers and other peripherals.

Fig. 25 is a diagram of waveforms illustrating the process of reading information from the memory cell M11.

Fig. 26 is a diagram of waveforms illustrating the process of writing data in the memory cell M11.

Fig.27A-27E illustrate the processing steps for manufacturing shown in Fig.21-23 storage device.

Fig. 28 is a schematic cross section of a modification of the storage device.

Fig.29 is a schematic cross section of the next modification of the device.

Fig.30 is a schematic cross section of an alternative barrier structure designed for use in the second type corresponding to the invention Zap is shown in Fig.30 barrier structure.

Fig. 32 is a schematic cross section of a third type corresponding to the invention of the storage device.

Detailed description of the invention In the following description correspond to the invention embodiments of memory devices can be classified into three different types.

Type 1 In Fig.1 shows the overall configuration of the first type corresponding to the invention of the storage device. The memory node 1 and the barrier structure 2 United inside the control electrode of field-effect transistor having outputs of the source and drain S, Y, and the output of the control electrode X. When the information is stored, the charge carriers tunneling through the barrier structure 2 in the memory node 1, and the device acts as a storage capacitor, so that the charge held in the node 1. For reading information, the conductivity of the channel, the source-drain S, Y is controlled and varies between relatively high and relatively low sostoyanie conductivity depending on the charge level stored in the memory node 1.

In Fig. 2 shows the volt-ampere characteristic of the barrier structure 2, where V is the voltage of the memory node. Electron flow I through the barrier structure from the output X is strongly �.gif">VC. However, outside this area the blocking voltage of the charge carriers can tunnel into the memory node 1 or from a barrier structure, depending on the polarity of the bias voltage VXapplied to the output X. the Barrier structure can be considered as mnogokanalnyy transition, in which two or more tunnel junction connected in series.

It is shown in Fig.1 storage device can be used as memory cells in a matrix of such devices arranged in rows and columns, as shown in Fig.3, with related lines of words of X1X2and so on, and lines of binary bits S1, Y1, S2, Y2and so on, Thus, the matrix includes a memory cell Mmnwhere m and n represent the number of rows and columns, respectively.

The first variant implementation of the invention will Now consider the structure of the first variant implementation of the memory cell Mmnwith reference to Fig.4, 5 and 6, where Fig.4 is a top view of a matrix of cells, and Fig.5 and 6 are transverse sections taken along the line a-a' and b' of Fig.4, respectively, of the cell M11.

Let us consider Fig.5, where the device is formed in the substrate 3, which in DM n+and drain regions 5, 6. Insulating region SiO27 isolates the cell from the next cell in the matrix. The substrate closes the insulating layer of SiO28. The memory node 1 and a closing configuration 2 tunnel junction is formed in the area surrounded by the layer 8. Conductive control electrode 9 covers the configuration of the 2 tunnel junction. Control electrode 9 forms a line of words X1, which runs along the row of the matrix. The area of the source and drain 5, 6 form a line of binary bits S1, Y1that pass through the column of the matrix shown in Fig.4. It should be clear that other cells in the matrix have their own line of words and bits.

The memory node 1 consists of point elements or pellets nanometric scale, limiting the number of electrons that can be stored by charging through the barrier configuration 2 so as to provide a uniform field in the lateral direction on the node.

Now will be described the election as a write-read data to the memory cell M11with reference to Fig.7 and 8. In this process, the line of words X1and lines of binary bits S1, Y1associated with the memory cell M11, AK the lines of words of X1is supplied as a pulse waveform voltage with a positive peak value of VX(W)and a negative value - VX(W). When you write "0" to the lines of binary bits Y1and S1is supplied a positive voltage pulse height VYW. On the other hand, when you write "1", a pulse voltage with a peak value of VY(W)is applied to the lines of binary bits Y1and S1. These pulses are such that they should be blocked during the time T. In this example, VX(W)=1.2 V, VY(W)=1.8 V, T=10 NS.

Let us consider Fig.8, where the number of electrons that can reside in the memory node 1, is limited by the extent of the region of the blocking voltage and the configuration of the tunnel junction 2. Thus, the voltage at the node cannot exceedVC. In Fig.8(a) of the bit "1" of binary data is displayed positively charged condition 11 (shortage of electrons) in the memory node 1, while "0" is displayed negatively charged condition 12 (excess of electrons) in the memory node 1. In this example, the voltage of the memory node in the States "1" and "0" is +0.4 V and 0.4 V, respectively. Now cobrajet final electronic state, which occurs at each stage. As shown in Fig.8(a), a positive voltage VY(W)(1.8 V) is applied to the lines of binary bits S1and Y1, two States 11 and 12 are moved to a point 13 (1.6 In) and point 14 (0.8 In), respectively, along lines of constant number of electrons in the memory node, i.e. V = (Cg/C)VSY+VO, (1)
where Cthis represents the total capacity of the memory node Withgrepresents the capacitance between the memory node and the terminals Y1and S1and VO- voltage of the memory node, when VSY= O(-CVO/q represents the number of excess electrons in the host memory, where q is the elementary charge). In the present embodiment, C/Cg= 1,5.
When the negative voltage - VX(W)(-1,2) is applied to the line of words X1as shown in Fig.12b, the region of the blocking VBoffset, as shown, state 13 state is 14, because 13 is outside the scope of the block and is not allowed to exist.

When a positive voltage VX(W)(1,2) prikladyvat discharges are grounded, as shown in Fig.12d, and the state 14 becomes "0" state 12 along the line of a constant number of electrons in the memory node 1.

It should be noted that any state of electrons between the States "0" and "1" 11, 12 is updated with the process for establishing the state "0". A corresponding process for recording "1" 11 shown in Fig.8E-8h. In this sequence any state between the States "0" and "1" is changed to update the state of "1".

You may notice that the recording process requires the simultaneous filing of the waveform record on the line binary digits and a line of words associated with a particular memory cell. Thus, it can be individually addressed memory cell. During the recording area of the block is shifted sequentially up and down in such a way as to force the state of electrons in the node selectively be set to either "1" or "0". However, if the recording signal is applied to line words X1but not to the lines of binary bits Y1and S1or the recording signals are applied to the lines of binary digits, but not to a line of words, the write will fail, and node 1 will remain in the current state.

For reading the stored information is positive on the>and Y1. As shown in Fig.9, the threshold voltage of the transistor is set by the voltage VTwhen the memory node 1 is charged negatively ("0"), and the value of Vt-VTthen , the memory node is charged positively ("1"). These threshold voltage VTand VT-VTpositive, so that the unselected memory cells electric current between S and Y does not flow (VX=0). The voltage at the gate of the VX(r)on the selected line of words is selected between the VT-VTandVT. Thus, ISY>0 to 1 and ISY=0 to "0". Thus, it is possible to use the detector current (not shown) for detecting the current flowing between the lines of binary bits Y1and S1(and other relevant portions of lines of binary digits in the matrix), when the voltage of the gate VX(r)applied to a line of words X1. In order to read data from the whole matrix in memory, the process is sequentially repeated for the other lines layer X matrix. In the present embodiment of the invention, V(r)X=0.8 V, VT-VT=0.4 V and VT=1,2 Century according Tawania record. The storage node 1 is determined by the ability of the configuration of the tunnel junction 2 to suppress the flow of electrons in a blocked region VBit is shown in Fig.2 volt-ampere characteristics. The storage time tSapproximately defined by the expression
tS=tWexp(-qVC/kT), (2)
where k is Boltzmann's constant, T is absolute temperature, q is the elementary charge, a tW- recording time. It is desirable to provide, for example, the storage time tSfor ten years, and tWequal to 10 NS, the voltage VCmust be greater than 1 for operation at ambient temperatures. If it were necessary to use the effect of the charge of one electron, then it would require an education barrier structure 2 of the metal particles smaller than 1 nm, which is not easy to achieve using currently available manufacturing techniques.

In the method, with which it is possible to achieve high blocking voltage VCuse the effect of the curvature of the energy band barrier configuration 2 charge, which are described in connection with mnogokanalnyy transition in the work of K. Nakazato and H. Ahmed, "Journal of applied physics", June 5, 1995, vol 66, 23, page 31 separately. For cycle storage height and width of the tunnel junction can be denoted by the symbols fSand dSaccordingly, and for a write cycle fWand dW. To save the memorized information for more than 20 years, the height of the barrier fSmust be greater than 1.8 eV for the suppression of thermally activated current issue of the Poole-Frenkel, and the thickness of the tunnel junction dSshould be thicker than 8 nm{fS(eV)}-1/2to control the tunneling current leakage. However, for a small recording time of about 10 NS, the width of theWtunnel junction must be less than 2 nm{fW(eV)}-1/2where fwis the height of the barrier for loop recording.

Barrier configuration 2, which can satisfy these criteria, shown in Fig. 10 and contains mnogokanalnyy transition, consisting of layers 15, 16 electrical and elektroizolyacionnogo material, respectively. In this example, the insulating layers 15 contain 1-3 nm thickness Si3N4and elektroizoljatsionnye layers 16 include polycrystalline silicon of a thickness of 3-10 nm.

The resulting energy diagram of the conduction for displaying the first component 17, with a width of BW1corresponding to the combined width of all of the layers 15, 16, which form a barrier configuration 2. In addition, each of the insulating layers 15 gives rise relatively narrow barrier components 18a, 18b, and so on, each of which has a width of InW2spaced from each other by means of locking regions, which in this case is formed of a layer 16 of polycrystalline silicon. Relatively wide barrier component 17 has a relatively low barrier height Bh1, while the barrier components 18a, 18b, etc. provide much higher barriers Inh2Bh2b.

Two components 17, 18 of the barrier perform different roles. Narrow and high barrier components 18 act as tunneling transitions that keep the combined effect of tunneling, namely, spontaneous tunneling through two or more tunnel junction due to the mechanical effect of quantization, so that the electrons flow only through one barrier 18 at the same time and remain for some period of time in the field between them. While in this region the electron inelastic scattered in the direction of the local state uravnoveshennoi impact a wide barrier component 17. The width and height of tall, narrow barrier component 18 cannot be changed by external offsets, since they are determined by the materials forming the barrier configuration 2. However, the broad, low barrier 17 can be modulated via an external offsets.

In Fig.11a is a diagram of a zone in the absence of applied voltage VX. You may notice that when the control electrode 9 is not applied voltage, the electron 20 in node 1 storage charge is forced to tunnel through the entire width of the relatively wide barrier component 17, if there is leakage from node 1, resulting in leakage of charge is strongly suppressed. However, when the electrode 9 is applied voltage, the energy diagram of the conduction for the barrier 2 is changed to the configuration shown in Fig.11b, from which you can see that the applied voltage causes a relatively wide barrier component 17 to form running down the slope towards the node 1 storage charge, resulting in a 20 electron has to tunnel only through a relatively narrow barrier components 18 in order to achieve the storage node. Thus, the barrier configuration provides relative to the extremely high voltage to the electrode 9, to force electrons to tunnel to the node 1 during the recording process.

In the layers 16 pellets of polycrystalline silicon have a diameter, which is almost the same size as the thickness. The size of granules in the memory node 1 may be larger than the size of the layers 16, causing the electrons can stably be stored in the memory node 1 to ensure reliable operation. In the device of Fig.10, the memory node 1 has a thickness of 5-30 nm and is formed of polycrystalline silicon. In the modification of node 1 can be legitemate to improve the stability of States of electrons in the node. From the foregoing it is seen that when memorizing information layers 17 of polycrystalline silicon to form the transition region and thus increase the dSwhile in the process of recording layers 16 does not act as a barrier, but instead, the device provides a potential gradient which accelerates electrons from the electrode 9 toward the node 1, which facilitates the rapid entry of electrons into the node.

Now will be described more in detail an example of manufacture of the device with reference to Fig.12. For the substrate 3 is used, the plate of silicon is p-type with a resistivity of 10 Ohm-see First form the insulating layer 7 from oxidation in the upper part of the silicon substrate 3 p-type increase of the oxide film of the gate 21 of a thickness of 10 nm. Then put a layer that is suitable for the formation of the memory node 1. Layer 1 contains Si n-type caused by the thickness of 10 nm, with a surface that is converted to silicon nitride in an atmosphere of NH3at a temperature of 900oC. the Thickness of the resulting silicon nitride samoogranichivatsja 2 nm. This corresponds shown in Fig.10 nitride layer 15A. Then put a layer of undoped silicon with a thickness of 5 nm so as to form a covering layer 16A (Fig. 10), which is then subjected to nitriding for the formation of the next layer 15b of silicon nitride 2 nm thickness. To build the barrier structure 2 the process is repeated several times.

Then, on the barrier layer structure 2 is applied film 22 doped silicon n-type thickness of 20 nm. The film 22 is applied film 23 of the SiQ2thickness of 20 nm by the method of chemical vapor deposition (CVD).

The different layers of a silicon film is applied in an amorphous state, but they are converted to polycrystalline silicon during the nitriding process and thick with CVD deposited layer 23 SiO2then the upper part of the film 23 SiO2structure using conventional methods of lithography and reactive ion etching in an atmosphere of CHF31 polycrystalline silicon and silicon nitride is etched using reactive ion etching, using CF4for the formation of a configuration of the shutter 24, as shown in Fig.12b. The configuration of the shutter 24 typically has a length 1 equal to 0.15 μm.

After this album occiderit for the formation of the outer layer 25 with a thickness of 30 nm thermal SiO2as shown in Fig.12C. Then, using ion implantation, arsenic ions are formed region of the source and drain 5, 6.

Then, as shown in Fig.12d, put 100 nm on the film 26 SiO2that is covered by the optical layer of photoresist 27 is applied with sufficient thickness to obtain a flat upper surface, in this example, a thickness of 1500 nm. Then, the photoresist 27 is again etched to until the upper part of the layer 26 SiO2will not protrude through the surface. Etching performed by the method of sputtering in the atmosphere of O2. The resulting configuration is shown in Fig.12.

The upper portion 26a of the film 26 SiO2removed by reactive ion etching in a gas atmosphere WF6until then, until you find the upper part of the film 22 of polycrystalline silicon, as shown in Fig.12f.

After removal of the optical photoresist 27 on the resulting surface put a metal structure using conventional lithographies>It should be clear that the storage device can be modified in various ways. For example, the thickness of the conductive layer 15 may be different from the described values of 5 nm and, in General, may be a satisfactory thickness of 10 nm or less. The thickness of the insulating layer 16 can be changed from the above values in the 2 nm so as to be in the range of 3 nm or less to form a satisfactory narrow high barrier components 18, although the described manufacturing process results in the proper administration of the thickness of each layer 16 so that it becomes of the order of 2 nm. In addition, the number of sets of layers 15, 16 may be different from those described in example seven to sufficient quantities for the formation of a satisfactorily wide, narrow barrier component 17 across the barrier configuration 2.

The second option of carrying out the invention
In the modification shown in Fig.10, barrier configuration 2 can be replaced by the configuration of the barrier Schottky, as shown in Fig.13. In this case, instead of using the insulating layer 15 of silicon nitride using metal layers 28 in such a way as to provide multiple configurations of diodes Schottky, perekryvaya the , formed between the films 16 of undoped polycrystalline silicon.

Now will be described in the following relevant to the invention embodiments of a storage device in which configuration 2 tunnel junction consists of islets of nanometric scale, distributed in the crystal lattice of insulating material. In the following examples, the Islands of nano-scale have a diameter of 5 nm or less and separated by insulating material with a thickness of nanometric scale in the crystal lattice, for example, the size of 3 nm or less, which gives rise to a narrow, high barrier components configuration tunnel junction. The storage node of the charge may be formed using conductive Islands so that they were distributed across the barrier configuration, but did not form a separate layer 1, as described above. To ensure that the resulting configuration megatonnage transition, you can use several different manufacturing processes, as will now be described.

The third variant embodiment of the invention
Fig. 14 illustrates a schematic cross section of another corresponding to the invention Varian is 2 implemented by combining crystals nanometric scale, which are distributed in the surrounding crystal lattice SiO2. Let us consider Fig.14, on which the substrate 3 provided with regions of source and drain 5, 6 with channel 4 between them. The oxide layer of the gate 29 covers the channel 4 and has a thickness of 5 nm was formed using the process of thermal oxidation on the substrate. Then put a layer of silicon of a thickness of 6 nm by electron-beam evaporation or CVD, which is then subjected to rapid thermal oxidation and crystallization. This process is described in the work of E. H. Nicolina and R. TSU, "Journal of applied physics, volume 74, 1993, pp. 4020-4025, and M. Fukuda, K. Nakagawa, S., Miyazaki and M Hirose, "Extensive annotations" (Extended abstrakts) International conference on solid state devices and materials, 1996, Yokohama, 1996 , pp. 175-178. It forms Islands in the form of Si nanocrystals with an average diameter of 3 nm, located in the layer 30 with an oxide layer tunneling 31 with a thickness of 2 nm, the covering layer 30. Native capacity 3 nm of Si crystals gives the charging energy of about 100 MeV, which is sufficient to limit the use of Coulomb blockade in the number of electrons within each nanocrystal, at room temperature. Applying a layer 29 with a subsequent rapid thermal about the second thickness. In this embodiment, the process was repeated five times to ensure the thickness of the joint layer is 20 nm, containing five layers of nanocrystal 30 within this thickness. Then on the top surface of the contact layer is formed of silicon of n-type 32. It should be clear that the resulting structure of the shutter can be included in the above-described manufacturing process of the storage device with reference to Fig.12. However, it should be clear that the memory node 1 is no longer provided as a separate layer, but instead formed in each layer 30 nanocrystals provide a location for storage of electrons distributed in the insulating oxide layers 29, 31.

The fourth variant embodiment of the invention
Fig. 15 illustrates the process steps for the formation of another variant implementation of the storage device. In this embodiment, the Association of silicon nanocrystals and the surrounding layers of SiO2formed through the use of porous Si films. Let us consider Fig.15A, where the porous Si film 33 with a thickness of 20 nm is formed by anodization of Si p-type. Anodizing is performed in a 25% aqueous solution of hydrofluoric acid, diluted with ethanol is~5 nm nanocrystalline Si, embedded in the crystal lattice of SiO2. This method is known in itself and is described in more detail in the work of J. Kanemitsu and other "Physical review" (Phys. Rev.), that V, 1993, pp. 2827.

Then the porous silicon film 33 is thermally oxidized for the formation of the oxide film of the gate 34 with a thickness of 5 nm together with the upper oxide layer 35 with a thickness of about 7 nm, as shown in Fig.15b. This process also leads to annealing, which reduces the diameter of each
the nanocrystal in the porous Si film, and the thickness of the porous layer 33. After the annealing the porous Si layer 33 has a thickness of 14~16 nm, and the average particle diameter is reduced to about 3 nm. The corresponding energy charge for particles of nanocrystalline silicon is equal to about 100 MeV, which, as explained above, leads to the limitation of the number of electrons that can penetrate into the host, due to the Coulomb blockade. The resulting film is indicated by position 36 in Fig.15b and contains approximately 3-4 nanocrystalline particles in its thickness, thus ensuring mnogokanalnyy transition (ICC) in considering the transfer of electrons vertically through the layer.

After that, the upper oxide layer 35 is removed and nanosilicas silicon as a mask, the composite film 36 and the underlying oxide shutter 34 is removed using conventional techniques of etching and then implanted region of the source and drain 5, 6 described above with reference to Fig.12 by the way. This method of manufacture has the advantage in comparison with described with reference to Fig.14 the method lies in the fact that mnogokanalnyy transition form using one of the anodizing process, reducing the amount of deposition of Si and the necessary stages of oxidation.

The fifth variant embodiment of the invention
The composite materials of the nanocrystals and the surrounding crystal lattice can be done in other ways, using different materials. One example is described in the work of E. Bar-Discussing and other "Physical review", volume 50, 12, 1994 , page 8961-8964. In this way the layer of particles AI in the crystal lattice of Al2About3can be used for replacement shown in Fig.15 porous silicon layer. The composite film of 30 nm thickness of AU and Al2O3you can do with a joint deposition of gold and aluminum on the layer of silicon oxide with a thickness of 5 nm, which is formed through thermal oxidation of the substrate 3. The subsequent fabrication of the device is the same as in the fourth embodiment, assistanoe the gold content, equal to 0.4. In these conditions formed isolated particles AI in the composite film having a diameter of about 3~5 nm. Therefore, a 30 nm film contains 5~10 particles AI its thickness, forming a vertical ICC. It should be clear that it can be used as a substrate for the porous silicon layer described with reference to Fig.15.

Through this process of co-deposition can be used to form the composite film of the other precious metals, of the type Ag, Pt, with some other crystal lattice of the metal oxide, the type of SiO2or IG2About3.

A composite film of an oxide crystal lattice with metal Islands can be formed by thermal decomposition of metal oxides. For example, the oxide of gold, which is the original metal oxide may be formed using reactive sputtering from an alloy of Au - Si in oxygen plasma, as described in the work of L. Maya, and others in "J. Vac. Sci. Tectnol." (Journal of vacuum science technology, vol B14, 1996, pp. 15-21.

The sixth variant embodiment of the invention
In Fig.16 shows a method of forming a composite insulating nanocrystals and the tunneling transitions with the help of way chemical Osada thermal oxidation on the substrate 3 of the Si p-type. Then on the surface layer 21 of SiO2is monomolecular layer 37 from octadecyl-trichlorosilane (OTS). As described in more detail in the work of M. J. Lercel etc., "J. Vac. Sci. Technol." (Journal of vacuum science technology, vol B11, 1993, pp. 2823-2828. In more detail, the substrate 3 with a layer 21 of SIO, SIS2immersed in a solution containing 1 milligram-molecule hexadecane OTC more than 12 hours. Resulted in spontaneous formation of a monomolecular layer UTS 37. The OTS molecules can be removed from the surface of SiO221 by irradiating an electron beam power of 60 kV. Thus, the image window in the OTC formed on the monomolecular layer 37 using a conventional electron-beam lithography. After the formation of the window in the OTC, the substrate was immersed in 1% aqueous solution of hydrofluoric acid for 30 sec, washing away the remnants of the irradiated electron beam OTS, leaving the window 38. The edge area of the window shown in the enlarged view inside the dashed outline 39. Shows an example of OTS molecules 40. It consists of a chain alkanes having siloxane connection on one end and a methyl group at the other. As shown in the enlarged space 39, the molecules 40 form a siloxane bond with a layer of SiO221 and form a tightly Packed Kowal is ü resistant to aggressive chemical exposure during processing of the substrate.

Then the substrate with a structured monomolecular layer UTS 37 placed in a dilute (0.05%) of anhydrous toluene solution (3-Mercaptopropyl) trimethoxysilane under conditions of fractionation with delegacia (i.e. heating to approximately 100o(C) within ten minutes. Then the substrate was placed in an oven at a temperature of 105oWith 30 minutes for curing siloxane links. The result is shown in Fig.16b. This procedure creates a monomolecular layer of alkane thiol 41 on the layer of SiO221 in the area of the window 38. The structure of individual molecules 42, which form a monomolecular layer of alkane thiol, consists of siloxane connection on one end alanovoy chain with mercaptanes group on the other. This process is described in more detail in the work of A. Doron and others, "Langmuir, vol 11, 1995, pp. 1313-1317. The OTS molecules outside of the window region 38 will not be affected. Location on the same line molecules 37, 42 can be seen more clearly in the enlarged view of the edge of the window, shown inside the dashed line 43. In principle, this surface modification can be performed with other alkhanovym thiol-terminated on one end of the alkoxysilane ((CH3O)3Si - or (C2H5O)3-Si-).

Then the substrate is dipped in Collina 38 is attached monomolecular layer of colloidal gold particles 44. This only happens in Windows, where the surface ends mercaptane groups (-SH), because of the strong affinity of sulfur and gold. The average size of gold colloid particles is 2 nm.

It is known that colloidal gold particles can be prepared by chemical means and have average diameters in the range of 2~5 nm with a well defined distribution in size, usually with a standard deviation of 10%. These nanoparticles are deposited on the surface, caniveau mercaptane groups, forming a covalent bond between the sulfur atom in the substrate and the gold atom in the surface of the gold colloidal particles. The deposition of particles automatically stops when the layer approaches the monomolecular layer, since the electrostatic force due to the surface charge of gold particles, which is provided by the ionization of the adsorbed substances on the gold colloid particles, prevents the deposition of other colloidal particles on the top surface of the substrate, or very close to the already deposited particles there. For a more detailed description we refer to our patent EP 96300779.4 registered 6 February 1996 Colloidal suspensions of such particles with a pre-defined average s Inc. ), 25E Loop road STI 124, stony brook (Stony Brook), new York 11790-3350, USA. Particles in aqueous suspensions. The adsorbed citrate ions reported a negative charge to the particles AI.

Then the substrate is dipped in 5 milligram molecular ethanol solution dithiol (namely, 1,6-hexanedithiol) after the above deposition of gold particles from the colloidal solution. One of the two sulfur atoms in the dithiol forms of communication Au - S with a gold colloid surface, replacing surface substances adsorbed gold particles developed, while the other end of the sulfur atom in the dithiol is focused on gold surface in the form of free mercaptan group. This arrangement is shown in Fig.16d with the dithiol molecules, denoted by the reference position 45. Therefore, the surface of gold particles is converted into the surface covered mercaptan group, which can take an additional layer of gold particles.

Next, the processed dithiol surface again immersed in the colloidal gold solution for the deposition of an additional layer. This process is repeated five times to form five layers of 2 nm gold particles, which are connected using alkanovykh chain dithiol. Two of the gold levels 46, 47 shown ndca 10 nm, marked on Fig. 16d reference position 49.

After that, as shown in Fig.E, the deposition of gold is repeated five times with a gold colloidal solution which contains gold particles of larger size, for example, 40 nm. Using this process forms a composite layer 50 of 40 nm gold particles with a thickness of 150 nm on the upper part of the layer 49. Because the particles form a layer 50 have a substantially larger diameter, they are negligibly small charge energy of about 1 MeV and, therefore, the electronic conductivity through the composite layer 50 exhibits ohmic in nature, in contrast to smaller particles, which form a layer 49, showing the characteristics of conductivity, dominated by the effect of Coulomb blockade. Therefore, the structure 50 of the larger gold particles functions as a conventional metal layer and, therefore, performs the function of the shutter in the same way as, for example, the shutter 22 of polycrystalline silicon described in the previous embodiments of the invention.

After this gold composite layer 50 is used as the weight for the dry etching of the OTS layer 37 and the gate oxide layer 21 so as to be able to implant the field Istana General configuration of another type corresponding to the invention of the storage device. A similar device is shown in Fig. 1 and similar parts are denoted by the same reference position. The device Fig. 17 additionally includes a control gate 51, which allows you to selectively apply a field to the barrier configuration 2 thus, in order to modify the characteristics of the tunnel junction. Thus, when the output Y is applied voltage, by changing the voltage on pin X box on the shutter 51 may vary, and, as a result, the field changes the characteristics of the tunnel junction in transition 2. The influence of the field applied through gate 51, you can see on the graph of Fig.18. The voltage on the gate 51 can be used to switch the device between the States "on" and "off", illustrated in Fig.18a and 18b, respectively. Applied to the gate 51, the voltage change width of the blocking voltage VB. As shown in Fig.18a, when the voltage VX"on" is applied to the gate 51, the locking voltage is relatively small and in some conditions is missing. In Fig.18a barrier voltage VBextends from - VCLto + VCLwhereas in the case of another voltage "off" on the shutter 51 block is when the device switches to the "on" state, the charge can tunnel in the host memory 1 and stored within a state "off". During the "off" bias voltage can be applied to the stopper 51 is essentially to enhance the VCHas described in the work of K. Nakazato and H. Ahmed. "Journal of applied physics", June 5, 1995, vol 66, 23, pp. 3170-3172. Generated voltage VXfield supplied on line 51 words, applied to the configuration of the barrier transition 3 thus, to compress a non-conductive region, as can be seen when comparing Fig.18a to 18b.

Will now be presented with a more detailed description with reference to Fig.19 and 20 of the modulation region, the blocking voltage for the tunnel junction 2 via gate 51. Fig.19 illustrates a section of the memory node 1, the configuration of the barrier transition 2 and output Y. the Shutter 51 is omitted in Fig.19, but will be described below. The configuration of the tunnel junction 2 is composed of alternating layers 15, 16 undoped polycrystalline silicon of a thickness of 3-10 nm and silicon nitride with a thickness of 1-3 nm, educated described above with reference to Fig. 10. The memory node 1 consists of a layer of doped polycrystalline silicon of n-type with a thickness of 5-30 nm and closes layer 52 undoped polycrystalline cramped layer 54 is doped polycrystalline silicon of n-type with a thickness of 30 nm.

As you can see from the energy band diagram in Fig.20, seven of the insulating layer 15 of silicon nitride give rise respective relatively narrow and relatively high barrier components 18 are similar to those described with reference to Fig.11 way, with relatively broad, but low barrier component 17. The effect of applying voltage to the gate 51 is in raising and lowering the barrier component 17 by choice, together with the barrier components 18, which, respectively, are fond up and down.

In the process of recording the voltage VXapplied to the output X (Fig.17), set the voltage recording VW (OV) and the height of the wide barrier component 17, which is actually the internal electrostatic potential in the configuration of the transition, which in this example is a relatively low value of the order of 0.2 C. Thus, electrons can tunnel through the narrow barrier components 18 and do not stay low wide barrier component 17A, so that the electrons are tunneling from the output Y in the memory node 1.

The stored charge in the node 1 can be maintained, due to the increase in VXto the auxiliary voltage VSBin Dublin core 17 b, which in this example is about 3 C. the resulting increase in the height of the barrier component 17 inhibits tunneling of carriers from the memory node 1 so that the information may persist in the host for long periods of time ~10 years.

For reading information VXset at the voltage reading VRwhich in this example is about -4 C. As will be described below, it holds a charge stored in the memory node 1, but allows you to read information from the channel source-drain devices within a relatively short cycle of reading equals ~100 NS. The barrier component 17 takes the form 17c shown in Fig.20.

The seventh variant embodiment of the invention
Now will be described in more detail the structure of the matrix of such devices with reference to Fig.21, which depicts a rectangular matrix of four cells on the horizontal projection, in conjunction with Fig.22 and 23, which illustrate the sections of one of the cells, along the lines a-a' and b' of Fig.21, respectively. Let us consider Fig.22, where the General structure of each memory cell is similar to the structure of the first type, as shown in Fig.5, but with the addition of the shutter 51, and the same channels are denoted by the same reference ptoca 5, 6 together with the insulating region 7 to isolate one cell from another. The device includes a memory node 1 and lying on top of the barrier structure 2 is formed, as shown in Fig.19, with the coating layer 53 undoped polycrystalline silicon and a line of binary bits, formed by a layer 54 of doped polycrystalline silicon is n-type. Line binary digits 54 closes insulating CVD SiO255 and the walls of SiO256, as will be described in more detail below. Side shutter 51 for the cell consists of a layer of polycrystalline silicon of n-type with a thickness of 100 nm, which passes across the line of binary digits and covers the side edges 57 of the barrier structure 2.

Consider again Fig.21, which shows that drains 6 for neighboring memory cells in a particular row do with using a total area of flow 6, which reduces the size of the memory cell.

Information can be recorded in a particular cell, for example, a memory cell M11shown on Fig.21 by applying a voltage write VWthe line of words X1(51) and a suitable voltage to the line of binary bits Y1(54) depending on the binary code "0" or "1". This causes the entry of the charge in the memory node 1 sub>1. Data is not written into the other memory cells in the column, as on the line of words X2and so on other cells enters the auxiliary voltage VSB. After that, the line of words X1apply auxiliary voltage VSBto save the data in node 1 cell M11. On line binary digits should not be applying the voltage. When you want to read stored data from cell M11voltage reading VRon line words X1served lower than the auxiliary voltage VSB. Peripheral circuits (not shown) perceive the conductivity of the source-drain of the cell M11by reading the current flowing between the lines S1and G (lines 5, 6). Other memory cells in the column are shifted by means of an auxiliary voltage VSBapplied to their lines of words of X2and so on, and thus these cells are not addressed when reading M11.

You can also use another method of operation of the circuit similar to the conventional method used in conventional ZUPU, in which stored information is transmitted to the peripheral circuit and is then replaced by new information, which is recorded in each memory node. This method has b> whereby allowing the emergence of significant changes in the values of VCLand VCHin different cells. Binary "1" is represented by the voltage of the memory node VHand binary "0" is represented by the voltage of the memory node VL. In the schema, there is only the requirement that VCHthere were more than VHand that VCLit was smaller than VLi.e. VCH>VH>VL>VCLand actually there is no need to determine their size. This wide settlement tolerance makes possible the Union of a large number of memory cells in the chip.

Now is the detailed description of this method of work with reference to Fig.24-26. Fig.24 schematically illustrates an electric circuit of a matrix of memory cells corresponding to Fig.21, and additionally shows a peripheral circuit, which are incorporated on the same semiconductor substrate 3, and the matrix of memory cells. Each memory cell M11-Mmncorresponds to a storage device of the second type, as described above, although the scheme is represented by an equivalent circuit consisting of two transistors QRand QR. The memory node 1 is represented by the index n In Fig.24 shows the configuration for the cell p is I chip voltage Converter VC, which creates a series of control voltages, described in more detail below, from the external source voltage VSS, which in this example is a voltage source 5 C. Each column of the matrix of memory cells has an associated circuit pre-charging 60 (PC) and diagram of the read-rewrite 61 (RWC), PC 60 and RWC 61 shown in detail for column n=1 of the matrix of memory cells and the corresponding schema for the column n is shown in dotted outline.

Diagram of input-output data 62 receives data from an external source and transmits the data from the matrix memory in the manner described in more detail below.

System legend various signal lines and components used in Fig.24, 25 and 26, are summarized in table.

Now will be described the process of reading the data with reference to Fig. 25. When the unlock signal chip CE rated voltage VCC, hereinafter referred to as "high", the chip is inactive. Under these conditions, the pre-charging signal fpis "high", a S1... Sn, Y1...Ynand I/O pre-charged to a voltage VPbecause the transistors in the PC 60 are in the "open" state. When CE is charged from the high level becomes low for the switching transistors PC 60 in the "locked" state. After this voltage lines S1... Sn, Y1...Ynswim, keeping the voltage VP. The line of words is selected using a signal address range (axi) on the driver number 59. When the voltage reading VRapplied to X1from the first row of memory cells M11...M1nread the information, and the output signals appear on the relevant lines read, S1. .. Sn. Considering, as an example, the memory cell M11when the voltage on the memory node N is equal to VPtransistor QRis in the "open" state, and the corresponding readout line S is discharged to 0 C. alternatively, when the voltage on the memory node is 0, S1charged on the value of VPas transistor QRis in the "locked" state. After the voltage S1 is set to 0 V or VPthe signal read-write frwbecomes "high", and the information S1passed Y1through PWC 61. That is, when S1is 0, Y1charged on the value of VPsince QDis in its "locked" state. However, when S1equal to VP, Y1is discharged to 0 V, so it is high in response to the supplied address signals column (ayj), so that QY1goes into the "open" state. Thus, the change in the voltage Y1is transmitted to the output data Doutthrough the line I / o I/O IOC 62. After Y1set to 0 or VPthe voltage on the lines of words of X1changes in voltage write VWso that transistor QW"opened", and the voltage Y1is restored to the memory node N. Thus, even if there have been any irregularities in the voltage of the node memory during read operations, the information is updated to 0 or VP. In the same way are reading and rewriting in other cells of the same number, M12... M1nbut few information is not transmitted to the line I/O, as in the case of cell M11. When the read operation and the rewrite is complete, the CE becomes high, X1mounted on the auxiliary voltage VSBand fpthen becomes high.

Now will be described write operation. As an example, in Fig.26 shows a write operation to the memory cell M11. Using the same operations as described in the read operation, stored in the M11information is transmitted in S1and Y1. The ZAT is asaeda this voltage. Then it is stored in the memory node N with the application of voltage write VWthe line of words X1. During the same operation can be restored to other cells in the same row, M12...M1n. It should be clear that this process is repeated sequentially, row by row, to write data into all cells of the matrix memory.

Now will be described an example of a method of manufacturing the corresponding shown in Fig.21-23 variant implementation of the memory cell with reference to Fig. 27.

Let us consider Fig. 27A, where the plate 3 of the silicon substrate is p-type with resistivity 10 Ohm-cm thermally oxidized for the formation of a layer 21 of SiO2thickness of 5 nm. Then layer 21 is applied to the film 1 from the doped silicon n-type thickness of 10 nm. Her cover film 52 of the undoped silicon of 30 nm thickness. The surface of the film 52 is covered by a layer of silicon nitride with a thickness of 1 nm surrounded by NH3at a temperature of 700oFor the formation of the first layer of the layers 15, shown in Fig.19. The thickness of the layer of silicon nitride can be controlled by controlling the temperature of its growth, from 2.5 nm at 1000oWith up to 1 nm at 700oC. Then put a layer 16 of undoped silicon and attirbute for the formation of another layer 15 nitri which contains seven sets covering layers 15, 16, shown in more detail in Fig. 19. After that put the film 53 of the undoped silicon of 30 nm thickness, which, in turn, cover the 20 nm film 63 of Si3N4that is applied with the purpose of masking, and structure by using lithography and dry etching in an atmosphere F3and argon gas. Then etched layers of silicon nitride, 53, 15, 16, 52, and 1, using known by itself, the method of dry etching.

Let us consider Fig. 27b, where the surface of the plate oxidases for the formation of SiO264 with a thickness of 30 nm, with the side edges 64A on the vertical sides of the barrier configuration 2, using as the mask film 63 of Si3N4. For the formation regions of the source and drain 5, 6 are implanted arsenic ions.

Then, as shown in Fig.27C, remove the film 63 of Si3N4and put the tape 54 from the doped silicon n-type with a thickness of 30 nm, followed by film 55 of SiO2thickness of 50 nm, applied using a conventional CVD process. After this layer 55 is structured by using lithography and dry-etching methods. The line width of binary digits, i.e. the width shown in Fig. 21 line Y1(54), is chosen equal to 60 nm, which provides good handling in 1 you can choose depending on the size of the matrix of memory cells. For wider lines of binary digits layers should do thicker. Using the protective layer and the film 55 of SiO2as the mask layers 54 and 55 is selectively etched in a gas atmosphere CL2until then, until you reach the first layer of silicon nitride configuration tunnel junction 2.

As shown in Fig.27d, to provide side walls 56 put a layer of CVD SiO2with a thickness of 30 nm and is subjected to dry etching in an atmosphere F3and argon gas.

Then, as shown in Fig. 27E, where from that time to determine the line of the words cause and structure using conventional lithography and dry etching the layer 51 of polycrystalline silicon.

MOSFET (metal - oxide - semiconductor) n-type and p-type, are shown in Fig.24 peripheral circuits can be run on the same substrate 3 using conventional methods. The area of source and drain for the MOS transistors are n-type may be formed at the same time, when you create the source and drains 5, 6 of the memory cells Mmnas described with reference to Fig.27b.

In this embodiment, to save in a separate memory nodes 1 memorized informtica when the device is turned off through the use of an external battery or capacitor. Because a small amount of current flows, except for a negligibly small leakage current, you can get a really non-volatile characteristics. In the following modification of the use of an external battery or capacitor is eliminated, thanks to the offset voltage up to +5 C. In this case, the secondary voltage becomes equal to 0 and, thus, the external battery is not required.

The eighth variant embodiment of the invention
In Fig.28 shows one way to offset auxiliary voltage, under pads, lines, words formed alloy region of the p-type 65. This configuration can be regarded as a modification shown in Fig. 22 configuration. Alloy region of the p-type 65 is formed by ion implantation of boron ions, using as a mask the layers of SiO255-56 after step process, shown in Fig.27(d). The voltage in the line of words is shifted by about 1 V At room temperature. In this structure has another advantage, namely that it is possible to manage more effectively the internal electrostatic potential, and therefore, the edge energy zone energy conductivity. Sledstvenoe potentials formed by the implanted transition type p-i, effective line width binary digits can be significantly less than the actual width of the line binary digits, so that even the line width of binary digits equal to 1 μm, sufficient for the realization of the presented storage device, instead of the width of 0.06 μm line binary digits in the seventh embodiment of the invention. In this structure, VSB=-4 V; VR=-3 V and VW=1 B.

The ninth variant embodiment of the invention
In addition, as shown in Fig.29, inside the barrier structure can be used to form a thin doped layer 66 of p-type, to deliver even higher contact potential difference. The configuration of Fig.29 can be regarded as a modification shown in Fig.28 configuration. Such a layer 66 of p-type can be easily formed by depositing a silicon film p-type or implantation of boron ions at an intermediate stage of formation of the barrier structure as it is formed using the method of repeated application. To reduce the diffusion of boron thin tunneling transitions 15 in Fig.19 have in between the doped layer 66 of p-type. In this case, the line voltage of words directly manages the internal electrostatic potential is between cycles reservation and write. In this structure, VSB=-2, VR=-1V and VW= 1st Century

The tenth variant embodiment of the invention
In this embodiment of the invention uses a thicker tunnel junction, about 5 nm, as shown in Fig.30. The configuration of Fig. 30 can be regarded as a modification shown in Fig.19 configuration, and the barrier structure can be entered in the device described with reference to Fig. 21-23. The memory node 1 in Fig.30 block non-alloy layer 52 of polycrystalline silicon with a thickness of 30 nm, which itself closes one barrier layer 67 with a thickness of 5 nm formed from a material Si3N4. Film Si3N4can be formed by using plasma nitriding at a temperature of 550oAnd when the power level of 300-500 watts. It is covered with a layer 53 undoped Si with a thickness of 30 nm and a layer 54 is doped Si n-type with a thickness of 30 nm, as described above with reference to Fig.19. The resulting energy diagram of the conduction barrier structure shown in Fig.31 and consists of a relatively wide barrier components 17 to the relatively low height of the barrier together with a relatively narrow barrier component 18 formed layer 67, a relatively large height b is Si3N4thickness of 5 nm. During a write operation, the voltage recording is applied to the side shutter 51 (not shown) in Fig.30. In this example, the voltage write VW=5 V reduces the barrier configuration in the transition state so that a relatively wide barrier component takes the configuration 17A shown in Fig.31. To read data to the gate 51 serves voltage VR=1, so that the barrier takes the configuration 17b. In this device you can read data from the storage device. To store information used by the auxiliary voltage VSB=0 In such a way that the configuration 17c positively blocks the leakage of charge from the memory node 1 using the voltage 0 V, input to the line of words X.

Type 3
Eleventh variant embodiment of the invention
Another type corresponding to the invention a memory device is shown schematically in Fig.32. The device in General like the version of the implementation described with reference to Fig.4 and 5, and similar parts are denoted by the same reference position. In the corresponding Fig.32 embodiment, the barrier structure consists of a matrix of horizontal dot elements 68. Point cell battery (included) is the work of the U. Chen, H. Ahmed, and K. Nakazato, "Journal of applied physics", June 12, 1995, vol 66, 24 p. 3383-3384 or using monatomic lithography, as described H. Ahmedov in proceedings of the Third international Symposium on new phenomena in mesoscopic structures", December 1995 in Addition, the horizontal dot elements 68 can be replaced by granules in the film of polycrystalline silicon, for example, as described Yano and others (see above) using nanocrystals, as described by way of these third, fourth and fifth embodiments of the invention, and using colloidal particles as described by the method in the present sixth embodiment of the invention.

Many variations and modifications are within the scope of the present invention. For example, different areas of the material is n-type and p-type can be replaced with each other for the formation of devices with additional conductivity to the above devices. In addition, the thickness of the various layers that make up the described examples nakaweesi tunneling transitions may differ from the specific examples given above. Similarly, you can use different insulating materials. N is, what you can use other systems semiconductors with different primary substrate type silicon-on-insulator, SiGe, Ge, GaAs and other well-known specialists in this field of technology. In addition, various other embodiments of the barrier structure and its modifications described for use in the first type corresponding to the invention of the storage device, can be used in embodiments of implementation of the second type with side shutter 51 and the corresponding second type of options exercise can be modified for use without the side gate, or with a fixed voltage applied to the side gate to operate in accordance with the principles of the first type.


Claims

1. A storage device containing a channel for charge carriers, the node for the stored charge to the education field that changes the conductivity of the channel, the electrode and the configuration of the tunnel, through which charge carriers tunneling from the specified electrode to the specified node and Vice versa under the influence of these voltages, and charges are stored and discharged from the site, and the configuration of the tunnel junction has a PR is Ino low height barrier and at least one relatively narrow size barrier component with a relatively large height of the barrier.

2. The memory device under item 1, characterized in that the electrode contains a single bus, covering the configuration of the tunnel.

3. The memory device under item 1, characterized in that the profile of the energy zone of relatively great height of the barrier is provided by the element width of 3 nm or less.

4. The memory device under item 1 or 3, characterized in that the energy band profile configuration tunnel junction includes many of the above-mentioned components with a relatively large height of the barrier.

5. The storage device according to any one of paragraphs. 1-4, characterized in that the configuration of the barrier contains the configuration megatonnage transition.

6. The memory device under item 4 or 5, characterized in that the configuration includes alternating layers of relatively conductive and electrically insulating material, where the layers work together to provide the mentioned component with a relatively low height of the barrier energy band profile, and a separate insulating layers provide a relatively high barrier components.

7. The memory device under item 6, wherein the alternating layers contain polycrystalline silicon and dobrovolny layer has a thickness less than 10 nm, and insulating layers have a thickness of about 2 nm.

9. The memory device under item 1 or 3, or 4, characterized in that the barrier configuration contains the configuration of the barrier Schottky.

10. The memory device under item 9, wherein the configuration includes alternating layers of electrically conductive material and a semiconductor material.

11. The storage device according to any one of paragraphs. 1-10, characterized in that the storage node of the charge contains a layer of electrically conductive material between the barrier configuration and the above-mentioned channel.

12. The storage device according to p. 11, characterized in that the layer contains a doped semiconductor material.

13. The storage device according to any one of paragraphs. 1-12, characterized in that the storage node of the charge contains a set of conductive islets.

14. The storage device according to p. 13, characterized in that the Islands are distributed in the barrier configuration.

15. The storage device according to p. 14, wherein the Islands have a diameter of about 5 nm or less.

16. The memory device under item 14 or 15, characterized in that the Islands give rise to a relatively narrow low barrier components of the profile of the energy band between roughly the Cai placed in layers, separated by insulating material.

18. The memory device under item 17, characterized in that the separation layer is less than 3 nm.

19. The memory device under item 13, wherein the Islands have a diameter of about 3 nm, and the separation layer is about 2 nm.

20. The storage device according to any one of paragraphs. 13-19, characterized in that the Islands contain nanocrystals of the semiconductor material.

21. The storage device according to any one of paragraphs. 13-19, characterized in that the Islands are formed of metal.

22. The storage device according to p. 21, characterized in that the metal Islands are formed by means of sputtering and distributed in the insulating metal oxide.

23. The storage device according to any one of paragraphs. 13-21, characterized in that the Islands contain particles deposited from a liquid suspension.

24. The storage device according to any one of paragraphs. 1-22, characterized in that the configuration of the tunnel junction has a range blocking voltage (Vin), in which the charge carrier tunneling in the node is blocked, and includes control means functioning to raise and lower range blocking voltage to control Velicina configured to store charge in many discrete States.

26. Storage device on p. 25, characterized in that the control means operates to raise and lower range of the blocking voltage in such a way as to ensure the existence of a node, only the selected one of the States.

27. The memory device under item 24 or 25, characterized in that the control means operates to change the width of the range of the blocking voltage.

28. The storage device according to any one of paragraphs. 24-27, characterized in that the control means operates to lower the height of the relatively wide barrier component so that the charge tunnels through the or each referred to a relatively narrow barrier component to memorize in the node, and the control means operates to raise the height of the relatively wide barrier component so that the charge stored in the node is restrained from tunneling through the barrier configuration.

29. Storage device on p. 28, characterized in that the control means operates for application to the barrier configuration voltage recording (VWfor enforcement of charge to tunnel in the node voltage reading (VRexceeding the voltage recording (VW), to provide the boost voltage reading (VR), to deter tunneling of charge from the node.

30. The storage device according to any one of paragraphs. 1-29, characterized in that it includes a control electrode, with which the charge carriers tunneling through the barrier configuration in the node under the action attached to this voltage.

31. The memory device under item 1 or 3, characterized in that it includes only one of these relatively narrow barrier component with a width greater than 3 nm.

32. The storage device according to p. 31, characterized in that the only barrier component is formed from a layer of Si3N4located between the layers of undoped Si.

33. The storage device according to any one of paragraphs. 1-32, characterized in that it includes a gate electrode for applying an electric field to the configuration of the tunneling transition to change its barrier configuration.

34. The storage device according to any one of paragraphs. 1-33, wherein the amount of charge that can be stored in the storage node of the charge is limited by the effect of the Coulomb blockade.

35. The storage device according to any one of paragraphs. 1-34, wherein the region includes a source and drain connected to the channel.

36. Many storage UEC memory (Mmn) of rows (m) and columns (n) on a common substrate.

37. Many storage devices on p. 36, wherein the storage device includes bus source and drain (S, Y, 5, 6) connected to the respective channels of the columns of cells, and dictionary buses passing along the rows of cells to control the tunneling of charge through the barrier configuration cells (Mmn).

38. Many storage devices under item 36 or 37, wherein the storage device includes means for reading the selection of the stored data from individual cells and to update the stored data.

39. Many storage devices on p. 38, wherein the storage device includes a data recorder for storing data in separate cells.

40. Many storage devices on p. 36, or 38, or 39, wherein the storage device includes bus read (S1. . . Sn) for detecting the current flowing through the channels of the respective columns of memory cells (Mmn), dictionary of tires (X1. . . Hmm), data bus ( Y1. . . Yn) for control barrier configurations of memory cells to their respective columns, the circuit pre-charging intended for will prefix the charge in the storage node charge (N) of a particular one of the cells in its column, read under the action of voltage reading(VR) applied to the corresponding dictionary bus scheme, read-write for the transmission level of the bus voltage reading in the appropriate dictionary tire for a column, means data output (Qy1, 62), is sensitive to the voltage level of the data bus, for providing output data (Dout), the corresponding data stored in the read cell, and the data update tool designed for applying voltage recording (Vwto dictionary bus read cell so that the data corresponding to the voltage level of the data bus is written back to read the first cell.

41. Many storage devices according to p. 40, characterized in that it includes means (Qy1, 62) to change the voltage level of the data bus after the action schema is read-write in response to the input data (Din) subject to entry into the cell, whereby the voltage recording calls recording input data in a cell.

42. Many storage devices according to any one of paragraphs. 36-41, wherein the matrix comprises a peripheral circuit formed on a common substrate with the memory cells (Mmn).

43. Sets the transistors, which include a region formed using the same process used for the formation of the corresponding regions in the cells of the matrix.

44. A method of manufacturing a memory device, which includes a channel for charge carriers, the node for the stored charge, which changes the conductivity of the channel, the electrode and the configuration of the tunnel, through which charge carriers tunneling from the electrode node to the specified node and Vice versa under the influence of these stresses so that will be remembered and stored in the node that you are carrying out the configuration tunnel junction so that it has the profile of the energy band, which contains a relatively wide size barrier component with a relatively low height of the barrier and at least one relatively narrow size barrier component with a relatively large height of the barrier.

45. The method according to p. 44, characterized in that it includes the configuration of the tunneling transition from areas of relatively conductive and insulating materials.

46. The method according to p. 45, characterized in that it includes the formation of the above-mentioned areas in the form of overlying layers.

47. The method according to the persons under item 46 or 47, characterized in that it comprises the formation of a conductive layer thickness of 10 nm or less.

49. The method according to any of paragraphs. 46-48, characterized in that it includes the provision of a layer of silicon for the formation of a conductive layer and processing the surface for formation of the insulating layer.

50. The method according to p. 49, characterized in that it includes nitriding the surface layer of the silicon for the formation of the insulating layer.

51. The method according to any of paragraphs. 44-50, characterized in that it includes the education hub in the form of a layer of electrically conductive material.

52. The method according to any of paragraphs. 44-50, characterized in that it includes the education hub in the form of a variety of conductive islets.

53. The method according to p. 52, characterized in that it includes the distribution of Islands in the barrier configuration.

54. The method according to p. 52 or 53, characterized in that it includes the formation of Islands of semiconductor material.

55. The method according to p. 52 or 53, characterized in that it includes the formation of Islands by spraying.

56. The method according to p. 52 or 53, characterized in that it comprises the deposition of islets from a liquid suspension.

57. The method according to any of paragraphs. 44-56, characterized in that it includes the formation of electrode sat what horatia.

58. The method according to any of paragraphs. 44-57, characterized in that it includes the formation of regions of source and drain connected to the channel.

59. The method according to any of paragraphs. 44-57, characterized in that it includes the formation of multiple storage devices in a matrix on a common substrate.

60. The method according to p. 59, characterized in that it involves the formation of peripheral circuits for reading and writing data in the matrix and out mentioned on total substrate.

61. Storage device, characterized in that manufactured by the method according to any of paragraphs. 44-60.

62. A matrix of storage devices, wherein the memory device is fabricated on a common substrate in a manner consistent with any of the PP. 44-60.

63. A storage device containing a channel for charge carriers, the node for the stored charge to the education field that changes the conductivity of the channel and the configuration of the tunnel through which the charge carriers are tunneling under the influence of this voltage with the ability to store in the node, the configuration of tunnel junction has an energy band profile that contains a relatively wide size barrier component with a relatively low height of the barrier and mentora the specified node for storing charge contains a set of conductive islets, distributed in the barrier configuration.

64. The memory device containing the channel source-drain for charge carriers, the node for the stored charge is made for the education field that changes the conductivity of the channel, the source-drain electrode lying on the specified host, and the configuration of the tunnel through which the charge carriers are tunneling under the action of these stresses between the said electrode and the node so that was stored and discharged from the site, and the configuration of the tunnel junction includes a layer of polysilicon material corresponding conductivity, the first layer relative to the insulating silicon nitride layer between the polysilicon material and the specified node and a second layer of relatively electrically insulating silicon nitride layer between the polysilicon material and the electrode, the configuration of tunnel junction has an energy band profile that contains a relatively wide size barrier component with a relatively low height of the barrier and at least one relatively narrow size barrier component with a relatively large height of the barrier.

 

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FIELD: semiconductor engineering.

SUBSTANCE: high-power semiconductor device 10 has active region incorporating drift area 20. At least part of drift area 20 is disposed in membrane 16 that has upper and lower surfaces 15 and 17 opposing one another. Upper surface 15 of membrane 16 in one of alternatives has power leads connected thereto directly or mediately to enable crosswise voltage application through drift area 20. As an alternative, at least one power lead is connected directly or mediately to upper surface 15 and at least one power lead is connected directly or mediately to lower surface 17 enabling vertical application of voltage through drift area 20. Lower surface 17 of membrane 16 has no semiconductor substrate in immediate proximity of this surface in each of mentioned alternatives.

EFFECT: improved design.

40 cl, 43 dwg

FIELD: electrical engineering.

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EFFECT: obtaining high-precision heavy duty transistors with stable electrical parametres.

21 cl, 9 dwg

FIELD: electricity.

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EFFECT: provision of possibility of smooth electronic control of inductance value of passive coil by means of core addition to its structure, properties of which vary under action of applied electric field, thus influencing inductance value.

2 cl, 7 dwg

FIELD: nanoelectronics and microelectronics.

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4 cl, 2 dwg

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1 dwg, 2 tbl

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EFFECT: increase of resistance to external actions, percentage of proper produce, fast-action.

5 dwg

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