The memory cell of the dynamic memory device

 

The invention relates to nano-electronics. Its use in the creation of dynamic random access memory with random access (dram) allows to obtain a technical result in increased reliability and performance of the memory cell by introducing into the circuit of a bipolar transistor (BT) and non-linear resistor (R) that allows you to amplify the information signal and, thereby, allows for faster recharging parasitic capacitance Withpbit bus Y. the memory Cell is functionally integrated element in which a collector region of a bipolar transistor (BT) is simultaneously the gate region of the MOSFET transistor, the drain region (D) MOSFET transistor forming region of the base (In) of a bipolar transistor and a resistor (R) is formed by quasi-neutral part of the active base region R-a bipolar transistor. As a result of functional integration in a single structure MOSFET and BT transistors and resistor implemented the design of a memory cell layout size and manufacturing techniques similar to the transistor memory cell of dram. 2 S. p. f-crystals, 2 Il.

The invention is VA with random access (dram) with increased reliability and performance.

Known memory cell for dram are functionally integrated structure, in which a combined key of the MOS transistor, a storage capacitor, address and bit bus (1, 2, 3). Such memory cells contain very small information charge storage capacitor, which leads to a small amount of the information signal bit on the bus due to the large parasitic capacitance, which it contains, as well as a great time of an information signal on bit bus.

The closest in technical essence is a memory cell of dram containing key n(p) - channel MOS transistor, the source of which is connected to the first output storage capacitor, the drain of the MOS transistor is connected to bit bus, and the gate to the address bus, a second output storage capacitor connected to the shared bus (Z) power.

The technical effect of this invention is to improve the reliability and speed of dram. These effects are achieved by the fact that the memory cell of dram contains additional n-p-n (p-n-p) and bipolar n-p-n (p-n-p transistor and the resistor, and the collector of a bipolar transistor is combined with a gate area of a channel MOS tra the second resistor, the second output of which is connected to the base of a bipolar transistor and the drain of the MOS transistor.

The main thing is that bipolar n-p-n (p-n-p transistor and resistor functionally integrated with the MOS transistor (see Fig. 2B), i.e., the collector region of the n-(R-type bipolar transistor is simultaneously the gate region of the MOS transistor, and its base region is a drain region of the MOS transistor, the active area of the base p-(n-) of the transistor, enclosed between the n+(R+area of the emitter and n-(p-) a collector region of a bipolar transistor is a nonlinear resistor, the passive p+(n+base n+(p+) emitter connected to bit bus.

The equivalent circuit of the memory cells of the dram In Fig. 1A shows the equivalent circuit of the simplest memory cell of dram, which includes a MOS transistor, the source (S) of which is connected to the first output capacitor (C), the second terminal of which is connected to a common bus (Z), drain (D) connected to the bit-line, the gate region (BS) with a common bus (Z), and the gate to the address bus (X).

In Fig. 1B shows the simplest structure of a memory cell of dram, in which the barrier capacitance istokpoga p-n power is s with the bit-line (Y), and the gate (G) connected to the address bus (X).

In Fig. 2A shows the equivalent circuit of the proposed memory cell of dram, which includes a MOS transistor, the source (S) of which is connected to the first output capacitor (C), the second terminal of which is connected to a common bus (Z), collector (C) of a bipolar transistor, source (D) of the MOS transistor is connected to the base (B) bipolar transistor and the first output register (R), the second terminal of the resistor (R) connected to the emitter of the bipolar transistor and the bit-line ().

In Fig. 2B shows the structure of the proposed memory cell of dram, in which the barrier capacitance istokpoga p-n junction (S) forms a storage capacitor (C) With gate area (BS), which is also the area of the collector (bipolar n-p-n transistor, the base region (B) which is simultaneously the drain region (D) of the MOS transistor, while the active area of the base (p-) n-p-n transistor forms a nonlinear resistor (R), the passive base region (R+and the emitter region (n+bipolar transistor located in the area of the base (B), are connected to the bit-line (Y). Gate region (BS) is formed by a substrate.

Dynamic cell dram operates as follows: the mode is ncial relative to the gate region (BS) and stop threshold voltage (Vo) - The MOS transistor. When this bit bus (Y) is the potential corresponding to the state of logic "0" (low potential relative to the Z bus), or the potential corresponding to the logical state "1" (zero potential relative to the Z bus). As a result, the MOS transistor is open and the storage capacitor (C) is charged through the resistance (R) of the potential available in this time for bit bus ().

In the reading mode information bit bus Z is supplied to a negative (low) potential and in the case of the capacitor is high (zero) potential relative to the common line (2), corresponding to the state of logic "1", through the inversion channel MOS transistor through the base of the bipolar p-n-p transistor passes current for charging a storage capacitor. This current is amplified bipolar transistor by an amount equal to its gain base current (h12 ~ 100). This increases the current information signal is permitted on the bus, which increases the reliability of the dram. It is important that the time of charging of the parasitic capacitance (CP) of data bus is also reduced in h12 times, which increases in a corresponding number of times the speed of dram. In the case of the second bus is determined by the parasitic capacitance (CP). In the mode information storage to the gate (G) of the MOS transistor serves zero potential, which corresponds to its closed condition.

The proposed memory cell and dram on its basis, as is evident from Fig.2B, can be easily implemented in standard CMOS technology, which is used in the production of dram. It should be noted that increasing the reliability and speed of dram ~ h12 times achieved almost without increasing the area of the memory cell of dram.

Sources of information 1. Matsue S, Vamamoto H, Kobayski K, et al. A 256 Kbit dymamia RAM IEEE. J. 1980.V sc-15. N5, p.872-874.

2. Rideout V. L. One-device-alls for dynamic random-access memories; a tutorial-IEEE, 1979, v. ED-26, N6, p.839-862.

3. US Patent 3387286, R. H. Dennard, Field-effect transistor memory application filed July 14, 1967, granted June 4, 1968.

Claims

1. The memory cell of dynamic storage device that contains a storage capacitor, address, bit, and a common bus and p-(n-channel MOS transistor, characterized in that it further comprises a non-linear resistor and a bipolar n-p-n (p-n-p transistor, the collector of which is connected to the gate region of the channel of the MOS transistor, the gate of which is connected to the address bus, the source is connected to the first output storage capacitor, the second position is RA and the first output of the nonlinear resistor, the second output of which is connected to the emitter of the bipolar transistor and the bit-line.

2. The memory cell of dynamic storage device that contains the address, bit, and a common bus, p-(n-channel MOS transistor, the area of the source which forms a storage capacitor with the gate region connected to a shared bus, and the gate is connected to the address bus, wherein the resistor, R-(n-channel MOS and bipolar n-p-n (p-n-p transistors are single functional-integral structure in which the collector region of n-(p-) type bipolar transistor is a gate region of the MOS transistor, its base region is a drain region, which is n+-(p+-)the area of the emitter of a bipolar transistor, the resistor is formed of p--(n--) the base region located between the n+-(R+-) emitter and n--(R--) a collector region of a bipolar transistor, the field of passive p+-(n+- base and n+-(R+-) emitter connected to bit bus.

 

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FIELD: semiconductor memory devices.

SUBSTANCE: device has a lot of memory elements, each of which contains input and output areas, isolating film, channel area, shutter electrode, area for storing electric charges, device also contains large number of periphery circuits, containing reading amplifier, register for storing recorded data of memory elements, register, which preserves the flag, indicating end of record during its check, and circuit, which after recording operation compares value, read from memory cell, to value, fixed by flag at the end of record, and overwrites value indicated by the flag.

EFFECT: higher reliability of operation.

5 cl, 71 dwg

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