A signal receiver for digital audio broadcasting

 

The invention relates to receivers for receiving signals digital audio broadcasting. Technical result achieved - ensuring the normal reception of the broadcast signal even in adverse environmental conditions types of conditions of multipath reception. The signal receiver digital audio broadcasting contains a mixer, an analog-to-digital Converter, an orthogonal detector, digital Converter Fourier, the detector delay for detecting discrete converted by Fourier transform data and digital to analog Converter, a voltage controlled oscillator, two means of detection of frequency deviation, two integrator, a comparator and switching circuitry. 1 S. and 2 C.p. f-crystals, 2 Il.

Technical field the Present invention concerns a receiver for receiving signals, digital audio broadcasting, more specifically, receiver, equipped with a demodulator for demodulation of a signal modulated by a frequency of compaction of orthogonal signals (hereinafter called CHAOS).

Description of prior art In the patent EP-A-606941 and the work of M. Lucia and others: "Aquistion* and tracking of the carrier frequency for systems CHAOS", edition "TRANS is Ala, modulated by CHAOS. In such a conventional demodulator shown in Fig.2, CHAOS-modulated signal is supplied to the input terminal, carried out a frequency conversion by the mixer 1 and the analog-to-digital conversion (a/d) a/d Converter 2. Converted by the a/d Converter, the signal is converted into I/Q-data bandwidth of the modulating signals through an I/Q detector (orthogonal detector) 3, and these I/Q-data comes in scheme 4 fast Fourier transform (hereinafter referred to as scheme FFT). Scheme 4 FFT performs Fourier transformation, and converts the input signal to the time domain into a signal of a frequency domain. The output signal from the circuit 4 FFT is supplied to the block 6 delay/detection and the detector 40 frequency deviation. Unit 6 delay/detection detects the input signal by a delay of one symbol, and outputs the demodulated data through the output terminal.

The detector 40 frequency deviation detects the magnitude of the frequency deviation in accordance with the phase reference symbol contained in the input signal. Detected value of the frequency deviation is converted by d/a Converter 41 and is supplied to voltage controlled oscillator 9, kotoryi frequency shift is controlled by the frequency of vibration of a voltage-controlled oscillator 9 for correcting the frequency deviation, to the mixer 1 has received the output signal of the voltage controlled oscillator 9 with the adjusted phase shift for the frequency conversion.

However, the above conventional receiver is associated with a certain problem, consisting in the fact that the normal signal reception may be impossible in conditions of multipath propagation due to the large magnitude of the detected frequency deviation.

Brief description of the invention the present invention is the task of creating a receiver capable of receiving signal even in adverse environmental conditions, type of admission to the conditions of multipath propagation.

In accordance with one aspect of the present invention, is provided a signal receiver digital audio broadcasting, containing the mixer, one input of which is fed an analog signal, an analog-to-digital (a/d) Converter to the output signal of the mixer into a digital signal, the orthogonal I/Q) detector to obtain the orthogonal I/Q data from the digital signal, digital Converter Fourier transform for discrete-time Fourier transform of the received orthogonal (I/Q) data, the detector delay for the detection of discrete, change the capacity of the supply voltage control frequency to voltage controlled oscillator to control the frequency of its oscillations and adjustment of the frequency deviation, and the problem is solved in that there is a first detection means for detecting frequency deviation in accordance with the phase reference symbol contained in the output signal circuit of discrete transducer Fourier, second means for detecting frequency deviation to detect the phase of the demodulated data and calculating the difference between detektirovanii phase to phase without care frequency integrator for integrating the output schema of the absolute value data of the magnitude of the frequency deviation, detektirovanie first-mentioned means for detecting the frequency deviation and a comparator for comparing the integrated output signal from the integrator with the first predefined range of the first threshold value, the circuit selector to select and output a first means for detecting frequency deviation or the output of the second means of detection of frequency deviation in response to the comparison results of the specified comparator, and when the output signal of the integrator is outside the first range of threshold values is selected first means for detecting frequency deviation, and when the output signal of the integrator within the first who were nursing frequency, received from circuit switch, integrated by the integrator, and the output of the integrator serves on timofeisolovei Converter.

It is desirable that the receiver contained a comparator for comparing the output schema of the absolute value with a second predefined threshold range, the logical sum calculator for calculating a logical sum of the output signal of the comparator and the integrated output signal of the comparator, the switch.

It is desirable that the receiver contained a comparator for comparing the output schema of the absolute value with a third predefined range of threshold values and generate the output signal level, the output signal of the comparator is delayed by the delay unit, while the output of the delay block is additionally delayed by the delay unit and the output of the comparator and the output line and the delay unit are added together by the adder, and the switch.

In the case of a receiver according to the invention, provided with a means of loading, if the magnitude of the frequency deviation detected by the first means of detection of frequency deviation is in the second range of threshold values and the value of ne frequency, the magnitude of the frequency deviation detected by the first means for frequency detection, can immediately switch to the magnitude of the frequency deviation detected by the second means for frequency detection. Consequently, it is possible to avoid frequent switching, which otherwise may be caused by external interference.

The receiver of the present invention further comprises: means for comparing a comparison of a predetermined third threshold range, narrower than the second range of threshold values, with the magnitude of the frequency deviation detected by the first means of detection of frequency deviation; and a cleaner for cleaning the integrator, if the result of the comparison means comparing determined that the magnitude of the frequency deviation detected by the first means of detection of frequency deviation, continues to be the second threshold range for a predetermined period of time.

In the case of a receiver according to the invention, provided with a means of cleaning, automatic frequency control can be maintained by the magnitude of the frequency deviation detected by the second means of detection of frequency deviation, even if you create instant samehada frequency, detected by the first means of detection of frequency deviation.

A brief description of the drawings Fig. 1 is a block diagram illustrating the major parts of the receiver, corresponding to a variant of implementation of the present invention.

Fig. 2 is a block diagram illustrating the major parts of a conventional receiver.

A detailed description of the preferred variant embodiment of the invention will be described Below, the receiver according to the invention, corresponding to the implementation of the present invention. Fig. 1 is a block diagram illustrating the major parts of the receiver, corresponding to the variant embodiment of the invention.

In the receiver this option implementation converts the frequency signal into a signal of intermediate frequency by the mixer 1 in cooperation with the generator 9, a voltage controlled, functioning as a local oscillator. The intermediate frequency signal is converted into a digital signal by the analog-digital Converter 2. The intermediate frequency signal converted into a digital signal, is supplied to the I/Q detector (orthogonal detector) 3, which converts the input signal into I/Q data baseband. O the om point FFT and Fourier-transform of the input data in the element window to thereby convert the input signal to the time domain into a signal of a frequency domain. Output circuit 4 FFT is supplied to the block 6 delay-detection, which outputs the demodulated by delaying the detection data through the output terminal. Output circuit 4 FFT is supplied also to the first means (7) detection of frequency deviation for detecting frequency deviation of the input signal. The demodulated by delaying the detection data are provided to the second means (8) detection of frequency deviation.

First means (7) detection of frequency deviation detects the magnitude of the frequency deviation in accordance with the phase reference symbol contained in the output signal of the FFT scheme, and produces the values of the frequency deviation. Second means (8) detector frequency deviation detects the phase of the data demodulated by the delay detection unit 6 delay-detection and coming from him, and calculates the difference between the detected phase and the phase without departure frequency for detecting the magnitude of the frequency deviation. The values of the frequency deviation detected by the first means 7 for detecting frequency deviation, multiplied by the value ofthe multiplier 81 ratio and delivered to the circuit 10 of the switch. The output value of the frequency deviation from scheme 10 switch are integrated by the integrator 11. The output of the integrator 11 is converted by a d/a Converter 41 and act as a voltage control frequency to voltage controlled oscillator 9 to control the frequency of its oscillations and adjustment of the frequency deviation. The output signal of the voltage controlled oscillator 9 with the adjusted frequency deviation is supplied to the mixer 1 for frequency conversion.

Scheme 10 switch controls the output signal from the controller 15 of the switch. In the controller 15 of the switch circuit 16 calculates the absolute value of the absolute value data of the magnitude of the frequency deviation detected by the first means 7 for detecting frequency deviation. Output circuit 16 of the absolute value integrated by the integrator 17. The integrated output signal of the integrator 17 is compared by the comparator 18 with the first predefined range of the first threshold value (reference signal 1) is 18 produces a signal of high level, in accordance with which the integrator 11 receives the output signal of the first means (7) detection of frequency deviation. On the other hand, if the output signal of the integrator 17 is within a first threshold range, the comparator 18 produces a low level signal, whereby the integrator 11 receives the output signal of the second means (8) detection of frequency deviation.

The integrator 17 for integrating the output circuit 16 of the absolute value consists of: multiplier 171 coefficient for multiplying the output values of the circuit 16 absolute values by a factor ofadder 172, which uses as one of its input signal the output signal of the multiplier 171 ratio and delivers the output signal of the integrated value from the integrator 17 to the comparator 18; block 173 delay for delaying the output value of the adder 172 for the period of one cycle of the data groups; and a multiplier 174 coefficient for multiplying the output unit 173 delay by a factor of (1-a) and feed its output signal to the adder 172 as its other input signal. Coefficientsand (1-a) are used for operations of multiplication cleverly the output of integrator 17.

In addition, the controller 15 switches the output circuit 16 absolute values are compared by the comparator 19 with the second predefined range of the second threshold value (reference signal 2: for example, from +/10 radians to/10 radian). If the output circuit 16 absolute values are outside of the second threshold range, the comparator 19 produces a signal of high level, whereas if the output circuit 16 absolute values are in the second range of threshold values, the comparator 19 produces a low level signal. The calculator 20 calculates the logical sum of the logical sum of the output signal of the comparator 19 and the inverted output signal of the comparator 18. Only when the output signal of the calculator 20 logical sum signal will be low, it will load a predetermined value n, the value of one previous cycle of the data groups, through switch 21 in block 173 delay instead of the value stored in block 173 delay.

In the controller 15 switches the output circuit 16 absolute values are compared by the comparator 22 also if">/50 radians to/50 radians). If the output circuit 16 absolute values are outside the third range of threshold values, the comparator 22 produces a high signal, whereas if the output circuit 16 absolute values are in the third range of threshold values, the comparator 22 produces a low level signal. The output of comparator 22 is delayed by the delay block 23 for the period of one cycle of the data groups, and the output unit 23 delays are additionally delayed by the unit 24 delays for the period of one cycle of the data groups. The output signal of the comparator 22 and the output signals of the blocks 23 and 24 delays are added together by the adder 25. Only when the output signal of the adder 25 is a low-level signal, the value stored in block 173 delay, reset switch 26.

The operation of the receiver of this variant implementation, constructed as described above will be described as an example for the case in which modulation is used the way CHAOS (/4-DQPSK) (EMPLOYEES) European specifications for signals of the digital audio broadcast.

In accordance with the phase reference singolda frequency and produces data, the corresponding value of frequency deviation. The output of the first means 7 for detecting frequency deviation multiplied by a factor ofthe multiplier 71 factor and is selectively transmitted by the circuit 10 switch on the integrator 11. In accordance with the phase of the symbol quadrature manipulation phase shift (CMPS) subjected to delay detection unit 6 delay-detection, the second means 8 for detecting frequency deviation detects the magnitude of the frequency deviation. The output of the second means 8 for detecting frequency deviation multiplied by a factor ofthe multiplier 81 ratio and selectively transmitted by the circuit 10 switch on the integrator 11.

When the delay-detecting the detectable phase difference of 1.2 MS (the length of the symbol COOS transfer mode) each character CMPS. If there is a frequency deviation, the output signal of block 6 delay/detection contains the phase shift corresponding to the frequency deviation, so that the magnitude of the frequency deviation can be calculated by the amount of phase shift. Presenting real part in KBI (fast information channel) output value of block 6 delay/detection by the symbol "Re" and representing the imaginary is agenies "arctan (Im/Re). The phase error Err () can be represented by expressions Err()=Re2-Im2if ReIm0, and the expression Egg()=Im2-Re2if ReIm<0./4+n/2 radians). For example, if n=0 (if the output value of the delay detection is in the first quadrant) and there is no phase error, the phase of the output signal of the delay-detection equal to (/4 radians) and Im2-Re2=0. If there is a phase error, phase error, or error of frequency deviation is determined by the difference (Im2-Re2). Therefore, the frequency deviation detected by the detector 8 frequency deviation range (from/8 -/8 radians).

In the receiver this option, the exercise of the absolute value data of the magnitude of the frequency deviation received from the detector 7 frequency deviation, calculated scheme 16 the absolute value of the output signal cat is ogowych values (for example, +/8 -/8 radian), the output signal of the comparator 18 causes the selection circuit 10 switches the output value of the detector 8 frequency deviation to implement thereby automatically control the frequency. This state corresponds to the state of the lock automatic frequency control.

If the output signal circuit 1 absolute value integrated by the integrator 17 is located outside the third range of threshold values, the output signal of the comparator 18 causes the circuit 10 of the switch to select the output value of the detector 7 frequency deviation to implement thereby automatically control the frequency. In particular, if the comparator 18 detects the magnitude of the frequency deviation that causes a large phase error is outside of the range (from +/8 -/8 radian), then selects the output signal of the detector 8 maintenance frequency, and the detector 7 of the frequency deviation to perform automatic frequency control.

Conversely, if the absolute value of the frequency deviation determined by the detector 7 maintenance frequency and integrated by the integrator 17 is in the third range of threshold values, then vybere determines the amount of frequency deviation, causing the phase error in the range (from +/8 -/8 radian), then selects the output value is not the detector 7 maintenance frequency, and detector 8 frequency deviation to perform automatic frequency control.

Since the output signal of the integrator 17 enters the third threshold range, the circuit 10 of the switch changes its output signal from the detector 7 frequency deviation in the output signal from the detector 8 of the frequency deviation. In this case, if only the signal output circuit 16 of the absolute value is within a first threshold range (from +/10 to/10 radian), and the inverted output signal of the comparator 18 is a low-level signal, that is, the circuit 10 to switch the selected output of the detector 7 maintenance frequency, then switch 21 in block 173 delay load a pre-defined valueThis predefined value n is set to such a small size that when it is added in the case of a small amount of frequency deviation, immediately selects the output signal of the detector 8 maintenance frequency, and when it is added in large validwriter certain valueloaded in block 173 delay when the output signal of the circuit absolute value enters the first threshold range due to the reduced magnitude of the frequency deviation and when the output signal of the comparator 18 selects the output of the detector 7 maintenance frequency, the output of the detector 8 frequency deviation is immediately blocked by the circuit 10 of the switch, and remains possible to select the output of the detector 7 frequency deviation, even if a pre-defined valueadded due to the increased magnitude of the frequency deviation. Thus, it is possible to avoid unstable switching, which otherwise can be called external interference.

The output signal of the detector 7 frequency deviation is multiplied by a factor ofwhile the output signal of the detector 8 frequency deviation is multiplied by a factor ofso the real gain of the detector 7 maintenance frequency is reduced. However, for example, the output signal of the integrator 17 can instantly increase under the condition of excessive interval protection, if it is reflected from the mountains interfering signal and the gain of the detector 7 maintenance frequency is abruptly changed, or when other conditions. In this case, CX the ne signal detector 8 frequency deviation. Therefore, the locked state can be released by the phase error caused by adding a predetermined valueand interfering signal, and even if the lock state is restored again selects the output signal of the detector 7 frequency deviation.

However, in the case of the receiver of this variant implementation, if the signal output circuit 16 of the absolute value remains in the second range of threshold values during three cycles of data groups output signal of the adder 25 is a low-level signal, so that the value stored in block 173 delay is cleared by the switch 26. Therefore, even if the phase error instantly grow after cleansing block 173 delay for the lock status, lock status is released, and the voltage controlled oscillator 9 continues to be managed in accordance with the output signal of the detector 8 frequency deviation.

In addition, the second threshold range is set narrower than the first range of threshold values. Therefore, when the comparator 22 has a low-level signal comes rather later than the time when comparator 22 continues for a period of three cycles of data groups. Block 173 delays, respectively, is cleared only when the control voltage controlled oscillator 9 via the output signal of the detector 7 frequency deviation completely changed to control a voltage controlled oscillator 9 via the output signal of the detector 8 frequency deviation.

Therefore, in the case of the receiver of this variant implementation, after the oscillation frequency of the voltage controlled oscillator 9 starts again be controlled and blocked on the receive frequency in accordance with the magnitude of the frequency deviation received from the detector 8 frequency deviation, the control detector 8 frequency deviation is not carried out and the possible sustainable broadcast receiving in the case of control by the detector 8 frequency deviation, with the possibility of erroneous detection of the magnitude of the frequency deviation caused by multipath propagation.

Scheme 16 absolute values can be omitted, but the use of this scheme reduces erroneous detection of the magnitude of the frequency deviation. Regardless, does the low-level signal of the comparator 22 in a period of three cycles of groups of data, and whether to clear the block 173 delay, detection can be performed through the use of counters is the factorsand (1-a) multipliers 171 and 174 of the coefficients. The above functions of the receiver implementation of this option can be implemented by using a digital signal processor or similar device.

As described so far, the receiver according to the invention is beneficial in that it can perform normal reception of the broadcast signal even in adverse environmental conditions types of conditions of multipath reception.

Claims

1. The signal receiver digital audio broadcasting, containing the mixer, one input of which is fed an analog signal, an analog-to-digital (a/d) Converter output signal of the mixer into a digital signal, the orthogonal I/Q) detector to obtain the orthogonal I/Q data from the digital signal, digital Converter Fourier transform for discrete-time Fourier transform of the received orthogonal (I/Q) data, the detector delay for detecting discrete converted by Fourier transform data and digital to analog (d/a) Converter, made with supply voltage control frequency to voltage controlled oscillator to control the frequency of its oscillations and adjustments ear the s in accordance with the phase reference symbol, contained in the output signal circuit of discrete transducer Fourier, second means (8) detection of frequency deviation to detect the phase of the demodulated data and calculating the difference between detektirovanii phase to phase without care frequency integrator (17) for integrating the output schema of the absolute value data of the magnitude of the frequency deviation, detektirovanie first-mentioned means (7) detection of frequency deviation and the comparator (18) for comparing the integrated output signal from the integrator (17) with the first predefined range of the first threshold circuit (10) switch to select or output of the first means (7) detection of frequency deviation or the output of the second means (8) detection of frequency deviation in response to the comparison results of the specified comparator (18), and when the output signal of the integrator is outside the first range of threshold values is selected, the first means (7) detection of frequency deviation, and when the output signal of the integrator within the range of threshold values is selected the second means (8) of the first detection frequency deviation, and the values of care frequency to analog Converter (41).

2. The receiver under item 1, additionally containing a comparator (19) for comparing the output schema of the absolute value with a second predefined threshold range, the calculator (20) logical sum for calculating the logical sum of the output signal of the comparator (19) and the integrated output signal of the comparator (18), the switch (21).

3. The receiver under item 1, additionally containing a comparator (22) for comparing the output circuit (16) the absolute value of the third predefined range of threshold values and generate the output signal level, the output signal of the comparator is delayed by a unit (23) delay, while the output of the block (23) delay additionally delayed by the unit (24) for the delay and the output of the comparator (22) and the output block (23) and block (24) delays are added together by the adder (25), and the switch (26).

 

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