The way the code frame synchronization

 

The invention relates to a method of transmitting digital data and can be used for frame synchronization in systems robust data protection with application of the adjustment, in particular, concatenated codes. The essence of the method is that the characters numbering sequence summarize the part of the characters in the test part of the error correcting code, and the rest of the characters validation part of the error correcting code summarize the characters synchronizing sequence, the detection of which is carried out by multiplication of the input sequence on the check polynomial error-correcting code, and the numbering sequence include control bits, while stateful control bits when comparing numbering sequences use only the numbering sequence for running a control test. Achievable technical result in the implementation of the method code frame synchronization is to increase the noise immunity and reduce the complexity of hardware and software implementation. 1 Il.

The invention relates to a method of transmitting dy information using corrective, in particular the cascade codes.

The way the code frame synchronization described in this application is applicable to a synchronization message transmitted by the sequence of words cyclic error-correcting code. When this synchronization indication is transmitted words error-correcting code. For synchronization does not require the transmission of additional special characters, and uses the redundancy of the error correcting code. After establishing synchronization signs synchronization subtracted from the error-correcting code, not reducing correcting ability of the code.

The most effective use of the code frame synchronization in noise-tolerant cascade codes. In this case, synchronization is provided by repetition of signs synchronization in different words internal code cascade code.

The main task is to improve noise immunity, the code frame synchronization when working in communication channels with high noise level, as well as reducing the number of operations for synchronization and simplified way.

The known method code frame synchronization, in which the input posledovateli, multiplied by the check polynomial error-correcting code, and as a result providing the synchronization sequence. Upon detection of a certain combination of the selected synchronization sequence shall take the decision on whether frame synchronization [1].

However, this method is insufficient immunity. Closest to the proposed method is a method (prototype), code frame synchronization, namely, that the accepted input sequence representing the sum modulo two error-correcting code, numbering and timing sequences, multiplied by the check polynomial of the code. Resulting allocate numbering sequence. Next, carry out the detection of the synchronizing sequence. Then define the error vector and carry out the correction of errors in the numbering sequence. Then compare numbering and synchronizing sequence with previously adopted and as a result of comparison get a certain number of matches selected numbering and timing sequences with appropriate numbering and synchronizing sequences previously adopted code is a predefined threshold of matches make a decision about the presence of frame synchronization at the current time. Next, subtract the appropriate numbering and synchronizing sequence of code words and then perform the decoding code words with the detection and correction of errors. [2] .

The disadvantage of this method is the low immunity and increased complexity of hardware and software implementation.

The purpose of the invention to increase the noise immunity of the code frame synchronization messages and reducing the complexity of the hardware and software implementation.

To achieve the goal proposed method code frame synchronization, namely, that the accepted input sequence representing the sum modulo two error-correcting code, numbering and timing sequences, multiplied by the check polynomial of the code. Resulting allocate numbering sequence. Next, carry out the detection of the synchronizing sequence. Then define the error vector and carry out the correction of errors in the numbering sequence. Then compare numbering and synchronizing sequence with previously adopted and as a result of comparison Westwoodone numbering and synchronizing sequences previously received code words, moreover, if the result of comparison of the number of matches with a threshold will be exceeded by the number of matches a predefined threshold of matches, take the decision on whether frame synchronization in the current time. Next, subtract the appropriate numbering and synchronizing sequence of code words and then perform the decoding code words with the detection and correction of errors. What's new is that the characters numbering sequence summarize the part of the characters in the test part of the error correcting code, and the rest of the characters validation of the code is then summed with the symbols of the synchronization sequence. This requires detection of the synchronizing sequence to carry out by multiplying the input sequence to test the polynomial error-correcting code. It is advisable that the numbering sequence consisted of the control bits, while stateful control bits numbering sequences and comparing the numbering sequences use only the numbering sequence, you are in control checks.

The implementation of the method code for the form input sequence. For this purpose, the transmitting side of the original message, the volume of k m-ary (m>1) characters at the beginning encode m-ary error-correcting code, such as m-ary error-correcting code is a reed-Solomon. A reed-Solomon code is the outer code or code first-stage robust cascade code.

In the encoding information is a code word reed-Solomon code (n, k), the information length is equal to k, and the block - n characters.

Further information code binary code, such as binary Bose - Roy-Chaudhury - Hocquenghem (BCH codes) with the check polynomial h(x). Code BCH is an internal code or code of the second stage of error-correcting cascade code. Code BCH has parameters: n1- block code length, k1information length of the code.

The source information for each word of the BCH code are symbols of a reed-Solomon code, considered as a sequence of binary symbols. A coding code BCH receive n binary words BCH code(n1, k1) or a binary sequence with1.

Then perform addition modulo two pieces of check symbols of the code BCH symbols numbering sequence c2. As the log2(n) a sequence corresponding to the binary representation of integers: 1, 2, 3, etc. To the numbering sequence add one or more control bits, such as parity.

The first word of the BCH code is folded modulo two binary representation 1 and the corresponding parity, the second 2, and so on, Such an addition perform all the words of BCH code. When selecting the appropriate check polynomial h(x) obtained by adding the code will be quite certain guaranteed minimum code distance and, therefore, have certain curative properties.

The remaining characters in the test part of the code BCH put modulo two with the third synchronization sequence with3constant for all words BCH code. Such a sequence can be any sequence of suitable length with good timing properties, such as a Barker sequence or sequence of maximal length code (reed - Muller 1-th order).

At the receiving side input sequence, formed as the sum of three sequences, and synchronizing and numbering sequence is.

The drawing shows the sequence of operations that illustrates the processing of the input sequence at the receiving side.

At the receiving side first carry out a reception of the input sequence.

Then perform the multiplication of the input sequence on the check polynomial of the BCH code-h(x). Thus, compute the syndrome BCH code or a sequence with1.

When entering the infallible word syndrome code is zero and the result of the calculation of the syndrome will receive a combination of the d0corresponding numbering and synchronizing sequences: d0= c2|c3. Upon receipt of the input words with errors will be calculated combination of some set {di}, corresponding to the sum of the non-zero syndrome code sequences and c2|c3. Next, perform the allocation of the numbering sequence of the first bits of the respective combinations of d0or in combination from the set {di}.

Next, carry out the detection of the synchronizing sequence c3in the last digits of the combination of d0or in combination from the set {di}. This is possible if the ratio of error lies within the syndrome, values for different fixed combinations of errors will be different from each other. Combination syndrome for such errors can be calculated in advance and, for example, be placed in a table.

In recognition of combination syndrome superimposed on the synchronizing sequence, perform the definition of the error vector. Components of the error vector are located at positions corresponding to the position numbering of the sequence. The definition of the error vector can be performed, for example, by using a predetermined fault tables, the entrance of which are recognized by the combination of the syndrome, and output corrected error vector numbering sequence.

Then carry out the correction of errors in the numbering sequence, if the input code word BCH accepted with errors. Correction of errors in the numbering sequence is the sum modulo two dedicated numbering sequence and the previously calculated error vector.

Next scan control bits numbering sequence.

If adopted for numbering sequence checks the control bits, compare well the activity with the previously accepted sequence is to verify the compliance of the adopted non-natural sequence of these numbers. Also compare the relative position of the synchronizing sequence for the received code words. Synchronizing sequence must defend from each other at a distance, times the number of bits n1in the BCH code.

Next, compare the number of matches with the threshold.

If the number of matching numbers of words BCH and synchronizing sequences is greater than the selected threshold, then is driven synchronization. This means that the input information is supplied for further processing. Moreover, the location of the synchronizing sequence uniquely identifies the beginning of the words BCH code, and the numbering sequence determines the position of the first word in concatenated BCH code or the beginning of the message.

The threshold number of matching numbers and a synchronizing sequence is chosen in such a way as to ensure high accuracy frame synchronization.

The choice of the optimal threshold is important when implementing the proposed method. The probability of correct synchronization should not get worse probability of correct reception of the message, provide robust cascade code on this cantodellerane proposed method frame synchronization on the computer taking into account the real statistics of the communications channel, will be following. For cascade code, internal code which is an advanced binary BCH code (32, 16) with correction triple error, and the outer reed-Solomon code (32, 16) defined over the Galois field GF(28with hotfix 8 multiple errors, numbering sequence had 6 bits, with one bit of parity, and the synchronization sequence of 10 digits. The allocation of numbering and timing sequences was performed with the correction of single errors in the inner BCH code. For a channel with an average probability of error per bit equal to p= 0.05 and the coefficient grouping errors Purtova=0.3, the optimal value of the threshold is in the range 2..3.

For other parameters the cascade code and decoding algorithm, a different channel and a different number of bugs fixed in the allocation of numbering and timing sequences, the optimal threshold value will differ from the above values.

Clock and numbering sequence is passed in the testing part of the inner code error correcting cascade code that does not require the introduction of additional redundancy for their predecomposition by comparing the number of matches with a threshold perform subtraction numbering and timing sequences of code words. Next, perform the decoding code words with the detection and correction of errors. Decoding is performed after removing the clock and numbering sequences, therefore the considered synchronization method does not affect the corrective properties of error-correcting code.

Cycle synchronization is not only error-free code words and the code words with errors. This increases the robustness frame synchronization and allows synchronization with a higher level of interference in the communication channel, where the number of undistorted code words is reduced.

In the present invention, unlike the known method, for comparison use only the numbering sequence for running a control test. This increases the robustness of the code frame synchronization, because it allows to exclude from the comparison portion of the erroneously received numbers.

Numbering and clock sequence, the proposed method is developed only test part of the BCH code, which allows for their separation at the receiving side to multiply the accepted sequence only one check polynomial is OMA: one for the allocation of numbering sequence, the other is for the clock. Therefore, the proposed method requires fewer operations for frame synchronization and has a lower complexity.

Achievable technical result of the proposed method code frame synchronization is to increase the noise immunity and reduce the complexity of hardware and software implementation.

Sources of information 1. Losev centuries, Brody E. B., Korzhik Century. And. Search and decoding of complex discrete signals / Ed. by C. I. Korzhik. - M.: Radio and communication, 1988, S. 136.

2. Beck, C., B. N. Bogdanovich, judge O. P. Method of synchronization messages. Sat.: Construction and analysis of communication systems. M.: Nauka, 1980, S. 84.

Claims

1. The way the code frame synchronization, namely, that the accepted input sequence representing the sum modulo two words cyclic error-correcting code, numbering and timing sequences, multiplied by the check polynomial of the code, resulting allocate numbering sequence, then carry out the detection of the synchronizing sequence, then when recognizing combination syndrome superimposed on the clock on the integrity of the characters numbering sequence and then perform the error correction in the numbering sequence by summing modulo two dedicated numbering sequence and the calculated error vector, then compare numbering and synchronizing sequence with previously adopted, while checking whether the received non-natural sequence of these numbers and compare relative position of the synchronizing sequence for the received code words, and synchronizing sequence must defend from each other at distances that are multiples of the number of bits in error correcting code, as a result of comparison get a certain number of matches selected numbering and timing sequences with appropriate numbering and synchronizing sequences previously received code words, then compare the number of matches with a threshold, and if the number of matching numbers of words error-correcting code and the synchronizing sequence is greater than the selected threshold, then carry out cyclic synchronization, while the location of the synchronizing sequence uniquely identifies the beginning of the words of error-correcting code, and the numbering sequence determines the position of the first word error correcting code in the message, characterized in that the characters numbering after the tin validation of the code is then summed with the symbols of the synchronization sequence, moreover, the detection of the synchronizing sequence is carried out in the result of multiplying the input sequence to test the polynomial error-correcting code.

2. The method according to p. 1, characterized in that the numbering sequence include control bits, while stateful control bits numbering sequences and comparing the numbering sequences use only the numbering sequence for running a control test.

 

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