Way to normalize the metric values of the component decoder in a mobile communication system and device for its implementation
The invention relates to communication systems and can be used in means of mobile communication. The technical result is to use changes in the set of metrics on the set of time segments. The decoder contains a decision tree, which generates a signal decisions when all metric values exceed the predetermined value. MyCitadel subtracts the predetermined value from the metric values in response to the signal decision to normalize the value of metrics. The decision tree contains many storage devices that remember the appropriate value metrics. 3 S. and 3 C.p. f-crystals, 13 ill., table 1. Technical field the Present invention relates to a device and method of iterative decoding for mobile communication systems and, in particular, relates to devices and method for normalizing metric values stored in the component decoder is an iterative decoder in a mobile communication system.The prior art In General, iterative decoding is used in such mobile communication systems, as IMT-2000 (or systems multiple access, code-division multiplexing mdcr-2000 and UMTS), which is applied that is a similar connection, using cascaded convolutional codes, cascading block codes or composite codes. The technical scope of iterative decoding is associated with the so-called "soft" (not defined) solutions and optimal characteristics-correcting code errors.In Fig.1 shows a known iterative decoder, comprising two component decoder. According Fig.1 the first component decoder 101 receives signals Xtosystematic code, the first signal parity Y1Kreceived from the demultiplexer 107 (which demuxes input signals parity Ytoand first external information signal. The first component decoder 101 decodes the received signals, giving primary decoded signal associated with the decoding results. This signal consists of component Xtosignals a systematic code and the second external information component. The interleaver 103 performs interleaving of primary decoded signal. The second component decoder 105 receives the primary decoded signal coming from the output of the interleaver 103, and the second signal parity Y2Kreceived from demultiply parity Y2Kby issuing a second decoded signal is converted interleaver 111. Next, the second component decoder 105 via directed interleaver 109 delivers the external information component to the first component decoder 101.As shown in Fig.2, the first component decoder includes unit 113 measurements of branching (WWII) to calculate metrics branching and block 115 summation-compare-select (CERs) to calculate metrics and perform the comparison in each state to choose the path with fewer errors.In the General case, the iterative decoder computes the metric value Mtaccording to the following equation (1).where Mt- the accumulated value of the metric at time t; Ut- the code word for the systematic bits, the code word for each bit Xto; xt,j- codeword redundancy bits; yt,j- the resulting value for the channel (systematic + excess); Lc is the reliability of the channel, and L(ut) is the a priori value of reliability at time t.From equation (1) implies that at each calculation of the metric the metric value Mtcontinuously growing by the second, third and fourth members. When perepolneny. However, the main purpose of the iterative decoder is performing iterative decoding to improve the characteristics of the decoding (i.e. error rate bit (hospital has no facilities) or error rate for personnel (PSCS)). Thus, during execution of the iterative decoder's function after a number of consecutive iterations metric values can increase and grow beyond the specified range. Therefore, if you are developing hardware decoder assumes the task of a certain range for the values of the metrics, the value metric may exceed the specified range, and there is a problem of overflow.Summary of the invention Therefore, the object of the present invention is to provide a device and method for normalizing metric values of the component decoder, and exceeding all accumulated metric values for the current state of a certain threshold, these accumulated metric values are normalized to a specific level after subtracting from them the specified value.To achieve the above result, it is proposed a decoder that uses the change in the set of metrics on the set of time segments. The decoder includes therefore the TES value. MyCitadel it subtracts a predetermined value from the metric values in response to the signal decision to normalize the metric values. The decision tree includes multiple storage devices for storing the corresponding values of the metrics with a predetermined number of bits. The logical element AND-NOT to generate a signal ("1" or high signal) when all values most bits (PRS) provided in the respective storage device is equal to "1" (high level). MyCitadel sets to zero the PRS in each storage device, when the logical element AND-NOT outputs of higher-level decisions, resulting from each of the metric values is subtracted preset value.Brief description of drawings
The above and other objectives, features and advantages of the present invention are explained in the following detailed description, illustrated by the drawings, which represent the following:
Fig. 1 is a block diagram showing the iterative decoder containing two-component decoder;
Fig.2 is a detailed block diagram showing the component decoders of Fig. 1;
Fig. 3 is a diagram illustrating the operation of CERs komponentov is but first embodiment of the present invention;
Fig. 4 is a flowchart showing the procedure of normalizing metric values according to the first embodiment of the present invention;
Fig. 5 is a diagram illustrating the operation of the CER component decoder, which has the facility to normalize the metric values in the block CER component decoder according to the second variant of the present invention;
Fig. 6 is a diagram showing the format of the storage device for the values of metrics to normalize the metric values according to the second variant of the present invention;
Fig. 7 is a flowchart illustrating the procedure of normalizing metric values according to the second variant of the present invention;
Fig. 8A and 8B is a diagram illustrating the right way, a wrong way and a difference of ways, and the quantization scheme for the code symbols;
Fig. 9A-9C is a diagram illustrating a right way and wrong way in accordance with the signal-to-noise ratio; and
Fig. 10 is a graph showing the value ofmaxin the saturation state, depending on the relationship of energy (signal) to the noise power Eb/No.Detailed description the preferred option of carrying out the invention
CERs for a component decoder in accordance with the present itaut the threshold value.There are two ways to normalize the accumulated metric values in accordance with the present invention. According to the first method the accumulated metric values are normalized using the minimum accumulated metric values when one of the accumulated metric values of the respective States exceeds the threshold value. According to the second method accumulated metric values are normalized using the pre-set value, when all the accumulated metric values exceed the threshold value.Normalization for CERs of the present invention can be used for the normalization to unit CERs 115 iterative decoder 101 described above in connection with Fig.2.A. the First option
Next with reference to Fig.3 describes a first variant embodiment of the invention. In Fig.3 shows the block structure of CERs, with the device normalizing metric values for the code restriction K=3 according to the first embodiment of the present invention.Below with reference to Fig.3 describes a device normalizing metric values. In Fig.3 shows four "current state", each of which has a metric value. When K=3 the number of shift registers for the values of the metrics is the La of each state. When all defined values of the metrics exceeds a threshold value, the comparator 117 outputs the specified value to the adders 125 - 125d, and each adder connected between one's current state and one by the following conditions. Then the adders 125 - 125d of the accumulated metric values for the current state subtracts the specified value, and the resulting values are given in the following States. In this description, the term "cumulative metric values of the current state" is used instead of the term "metric values of the current state and on the contrary, to emphasize the fact that the values of the metrics for the current state of the sequential computation of the metrics are accumulated.In Fig. 4 shows the procedure for normalizing metric values according to the first embodiment of the present invention. According Fig.4, the comparator 117 at step 401 determines the metric values for the four current States. After determining the values of the metrics comparator 117 at step 403 checks whether at least one of the specific accumulated metric values in the threshold value. If none of the accumulated metric values exceeds the threshold value, the comparator 117 passes to step 407 for performing, the comparator 117 at step 405 outputs the adders 125-125d minimum of four detected accumulated metric values. Then the adders 125-125d from all four of the accumulated metric values are subtracted minimum accumulated metric value, and then proceeds in the following States. After that, as shown in step 407, the decoder goes to the normal operation of CERs.C. the Second option
The following describes a second variant embodiment of the invention.In Fig.5 shows the block structure normalization of CERs according to the second variant of the present invention. According Fig.5, the comparator includes many storage devices 130, 132, 134 and 136 for storing the accumulated metric values of the respective States, the logical element And 121 to determine whether all the accumulated metric values stored in the storage devices 130, 132, 134 and 136, exceeds a threshold value, and the inverter 119 for setting to zero the high order bit (PRS) of the respective storage devices 130, 132, 134 and 136 in response to a high signal issued by the logical element And 121.The format of the memory devices described with reference to Fig.6. Here it is assumed that each accumulated Zn is with one additional bits to prevent overflow of the accumulated metric values. Thus, the accumulated value of the metric is only 9 bits per sample. As shown in Fig.5, the logical element 121 And receives the ninth bit, which is the highest bit (PRS) storage devices 130, 132, 134 and 136, and generates an output signal of high level when all the input signals is "1". That is, when none of the PRS storage devices 130, 132, 134 and 136 is not equal to "1", the logical element 121 And does not generate an output signal (low level signal). When all of the PRS of the storage devices have a high level or "1", the logical element 121 And generates a high signal. When the logical element 121 And outputs a signal of high level, the inverter 119 outputs a signal installation in the zero bit of the PRS storage devices 130, 132, 134, 136, thereby establishing the PRS bits to zero. This is equivalent to subtraction of 256 from each of the accumulated metric values, which allows to Express the accumulated metric values using 8 bits.Suppose, further, that the difference between the accumulated values of the metrics of the two States isk= (uki-ukj-)maxwhere i and j represent one of the values 0, 1, 2 and 3, a k - p the IR for the two States ismax= 255 = 28-1. Finally, suppose that u1k- minimum metric value, a u3k- maximum metric value, as shown in Fig.6.As for overflow, if all bits of the PRS metric values at time k is equal to "1", the minimum value is 256.According to the above assumptions, if the PRS for u3kis "1", then the PRS other States will be equal to "0" or "1". Until all bits of the PRS for uik(where 0i3) becomes equal to "1", the output signal of the transfer will not appear even if the PRS u3k(and maybe one or two other metric values) is equal to "1". That is, until all bits of the PRS becomes equal to "1", the output signal of the transfer on the ninth bit does not occur for any of them. This means thatkdoes not exceedmax.
In Fig.7 shows a flowchart illustrating the procedure of normalizing metric values according to the second variant. According Fig.5 and 7, at step 501, the comparator 117 determines the accumulated metric values in specific units, the logical element 121 And the comparator 117a determines (or receives) PRS bits of the accumulated values ametryplene metric values corresponding to the current state exceeds a threshold value. That is, the logical element 121 of the comparator 117 determines whether all bits of the PRS is "1", as shown in decision block 503. If none of the PRS is not equal to "1", the comparator 117 proceeds to step 507 to perform common operations CERs. If all bits of the PRS accumulated metric values are equal to "1", the comparator 117a goes to step 505, where each metric value is subtracted threshold value. That is, all bits of the PRS are set to zero. This corresponds to the logical element 121 And applying a high signal to the inverter 119, which in response to this signal generates a setting signal to zero bits PRS respective accumulated metric values, thereby establishing the PRS to zero. After installing PRS bits to zero comparator 117a, as shown in step 507, performs the normal operation of CERs.Next with reference to Fig. with 8A 10 descriptionmaxdefined above. Whenk<maxoverflow does not occur.maxhas a lower value at low value of the ratio Eb/No and has a higher value at high value of the ratio Eb/No. That is, the difference between the values of the metrics has the m, that noise at low Eb/No increases, resulting in reduction of the aforementioned difference, at high Eb/No noise is extremely small, which increases the differencemaxbetween the values of the metrics. Therefore, it is very important, which is set tomaxat high Eb/No. In the first case, you can just assume thatmaxhas an infinite value at infinite value of Eb/No. However, for example, the Viterbi algorithm with weakly defined ("soft") output (SOVA algorithm) the difference between the metrics is limited to a constant, defined asfree.For example, suppose you have 4 bits per sample, the rate of the code R= 1/3, K= 9 convolutional code transmits a code word with all zeros "000". In this case, when the high value of the ratio Eb/No most of the errors you receive during the comparison/selection between the way with all zeros and by dfreeas shown in Fig.8A. Here, the value of the branch metric and the metric value of the path is calculated by the following equations (2) and (3) respectively.
where 1=0, 1, 2, and 3, Ck,j- code word y(i)k,j- received signal, r is the PTO is sup>ki= us,ki-uc,kimaxwhere "s" denotes the selected path, and "C" indicates a competitive way. You must calculatemaxat high Eb/No, whenkihas a maximum value. This means that ifkilessmaxat high Eb/No, whenkihas a maximum value, then the difference between the values of the metrics does not exceedmax.
In this state of "i" there is a difference metric between two paths: the path with all zeros and the path dfree. In Fig.8B shows that the difference between the two paths depends on the code symbol dfree.In other words, the metric of the selected path is a value obtained by summing the metric of the path for the zero path with a metric value in the first state in the previous time, and the metric competitive path is a value obtained by adding the path metric corresponding to a competitive way, with the metric value in the second state in PA more than the metric of the path between the first state and the time of the comparison, the differencemaxequal to or greater thanki. Therefore, when the conditions are satisfied formaxalso satisfied the terms andki. The fact that the difference does not exceedmaxthat means that the difference in metric values between the two conditions in the above-mentioned point in time does not exceed
The difference metric is given by the following expression:
(dfree(convolutional encoder)=18 for K=9, R=1/3)
where M denotes the value of the metric at the point of branching of the chosen path and competitive way. Therefore, when a condition is metmax270, the value of the difference between the corresponding States does not exceedmax. Because it was assumed that the sample has 4 bits, the number of storage devices for storing the metric values is 8, and as to prevent overflow is added 1-bit storage device,/p> In Fig. 9A shows the value ofmaxat high signal-to-noise ratio, the value ofmaxis calculated by the formula
max= dfreeMax(Q[ctot]) ... (4)
where Q denotes the level of quantization, a Max(Q[.]) denotes the distance between "0" and "1". For example, 4 bits per sample Q=16 and Max(Q[.])= 15, and 3 bits per sample Q=8, a Max(Q[.])=7.In Fig.9B shows the value ofmaxwith an average signal-to-noise ratio, where a value ofmaxat this point, is calculated by the formula
max= (dfree+)Max(Q[.]) ... Ur.5
where the value ofdue to noise, a very small value, and it is less than or equal to 2 x dfreex Max(Q[.]) in the convolutional encoder (SC). However, this is not the case whensummed as shown in equation (5).In Fig. 9C shows the value ofmaxat low signal-to-noise, while at this point, the value ofmaxis calculated by the formula
max=0, it should be noted that the value ofmaxgradually increases with increasing Eb/No, and starting from a certain point saturation occurs. Ifmaxsatisfies equation (5), equation (6) is also satisfied.The following describes the characteristics of the convolutional encoder in the system of the CDMA-2000.For K=9 and R=1/2, dfree=12, and dfree14, 16, 18, 20.For K=9 and R=1/3, dfree=18, and the next dfree20, 22.For K=9 and R=1/4, dfree=24, and the next dfree26, 18.The table shows the value ofmaxin the convolutional encoder (SC).Therefore, the number of bits that are added to prevent overflow for 8 bits per sample, which are assigned for metric values, is defined as follows.For R=1/2 the number of bits equal to 1, since 28=256 180<256; for R= 1/3 the number of bits is 2, because 29=512, and 270<512; for R=1/4 the number of bits is 2, because 29=512, and 360<512. In other words, because the rate of the code R=1/2 requires 8 bits to prevent overflow, you need to add only 1 bit. In addition, because scene, adding to the number of bits required for a given speed of your code, only 1 bit.As described above, the new device can prevent errors due to overflow by normalizing the accumulated metric values for decoding, resulting in more efficient memory usage.Although the invention has been shown and described with reference to specific preferred implementation, specialists in the art it is obvious that it can be made various changes in form and detail, not beyond being and scope of the invention defined in the claims.
1. The decoder uses the change in the set of metrics on the set of time segments, containing the decision tree, which generates a signal decisions when all metric values exceed the predetermined value, and myCitadel, which subtracts the predetermined value from the metric values in response to a signal solutions.2. The decoder under item 1, characterized in that the decision tree contains many storage devices having a pre-set E, which as the input signal gets values most bits (PRS) supplied from the respective storage devices, and the output of the logical element AND-NOT given the signal of the higher-level decisions, when all values of the PRS have a high level.3. The decoder under item 2, characterized in that myCitadel contains an inverter that has an input signal, which is combined with the output signal of the logical element AND-NOT, and the output signal, which mates with the PRS storage devices, and the signal of the higher-level decisions issued by the logical element AND-NOT on the inverter generates an output signal of the inverter, which sets to zero the value of the PRS of the respective storage devices.4. The method of normalizing metric values in the decoder, using the edit multiple values of the metrics on the set of time segments, comprising the steps of determining whether all of the metric values exceed the preset level, and subtracting a predetermined value from the values of the metrics for transition to the next state when all metric values exceeded this predetermined value.5. The method according to p. 4, characterized in that the subtraction pre-installed is achene metrics.6. The method of normalizing metric values in the decoder, using the edit multiple values of the metrics on the set of temporal segments and having multiple storage devices for storing the metric values with a predetermined number of bits, comprising the steps of determining whether all the values of the PRS of the respective storage devices is equal to 1, and setting to zero the values of the PRS, when all values of the PRS is equal to 1.
FIELD: radio engineering; construction of radio communication, radio navigation, and control systems using broadband signals.
SUBSTANCE: proposed device depends for its operation on comparison of read-out signal with two thresholds, probability of exceeding these thresholds being enhanced during search interval with the result that search is continued. This broadband signal search device has linear part 1, matched filter 2, clock generator 19, channel selection control unit 13, inverter 12, fourth adder 15, two detectors 8, 17, two threshold comparison units 9, 18, NOT gates 16, as well as AND gate 14. Matched filter has pre-filter 3, delay line 4, n attenuators, n phase shifters, and three adders 7, 10, 11.
EFFECT: enhanced noise immunity under structural noise impact.
1 cl, 3 dwg
FIELD: radio engineering for radio communications and radar systems.
SUBSTANCE: proposed automatically tunable band filter has series-connected limiting amplifier 1, tunable band filter 2 in the form of first series-tuned circuit with capacitor whose value varies depending on voltage applied to control input, first buffer amplifier 3, parametric correcting unit 4 in the form of second series-tuned circuit incorporating variable capacitor, second buffer amplifier 5, first differential unit 6, first amplitude detector 7, first integrating device 9, and subtraction unit 9. Inverting input of subtraction unit 9 is connected to reference-voltage generator 10 and output, to control input of variable capacitors 2 and 4. Automatically tunable band filter also has series-connected second amplitude detector 11, second integrating unit 12, and threshold unit 13. Synchronous operation of this filter during reception and processing of finite-length radio pulses is ensured by synchronizer 14 whose output is connected to units 10, 8, and 12. This automatically tunable band filter also has second differential unit whose input is connected to output of buffer amplifier 3 and output, to second control input of variable capacitor of band filter 2.
EFFECT: enhanced noise immunity due to maintaining device characteristics within wide frequency range.
1 cl, 1 dwg
FIELD: radio communications engineering; mobile ground- and satellite-based communication systems.
SUBSTANCE: proposed modulator that incorporates provision for operation in single-channel mode with selected frequency modulation index m = 0.5 or m = 1.5, or in dual-channel mode at minimal frequency shift and without open-phase fault has phase-shifting voltage analyzer 1, continuous periodic signal train and clock train shaping unit 2, control voltage shaping unit 3 for switch unit 3, switch unit 3, switch unit 4, two amplitude-phase modulators 5, 6, phase shifter 7, carrier oscillator 8, and adder 9.
EFFECT: enlarged functional capabilities.
1 cl, 15 dwg
FIELD: electronic engineering.
SUBSTANCE: device has data processing circuit, transmitter, commutation unit, endec, receiver, computation unit, and control unit.
EFFECT: high reliability in transmitting data via radio channel.
FIELD: electronic engineering.
SUBSTANCE: method involves building unipolar pulses on each current modulating continuous information signal reading of or on each pulse or some continuous pulse sequence of modulating continuous information code group. The number of pulses, their duration, amplitude and time relations are selected from permissible approximation error of given spectral value and formed sequence parameters are modulated.
EFFECT: reduced inetrsymbol interference; high data transmission speed.
16 cl, 8 dwg
FIELD: communication system transceivers.
SUBSTANCE: transceiver 80 has digital circuit 86 for converting modulating signals into intermediate-frequency ones. Signal source 114 transmits first periodic reference signal 112 at first frequency. Direct digital synthesizer 84 receives second periodic signal 102 at second frequency from first periodic reference signal. Converter circuit affording frequency increase in digital form functions to convert and raise frequency of modulating signals into intermediate-frequency digital signals using second periodic signal 102. Digital-to-analog converter 82 converts intermediate-frequency digital signals into intermediate-frequency analog signals using first periodic reference signal 112.
EFFECT: reduced power requirement at low noise characteristics.
45 cl, 3 dwg
FIELD: radio engineering; portable composite phase-keyed signal receivers.
SUBSTANCE: proposed receiver has multiplier 4, band filter 6, demodulator 8, weighting coefficient unit 5, adding unit 7, analyzing and control unit 10, synchronizing unit 3, n pseudorandom sequence generators 21 through 2n, decoder 1, and switch unit 9. Receiver also has narrow-band noise suppression unit made in the form of transversal filter. Novelty is that this unit is transferred to correlator reference signal channel, reference signal being stationary periodic signal acting in absence of noise and having unmodulated harmonic components that can be rejected by filters of simpler design than those used for rejecting frequency band of input signal and noise mixture. Group of synchronized pseudorandom sequence generators used instead of delay line does not need in-service tuning.
EFFECT: facilitated realization of narrow-band noise suppression unit; simplified design of rejection filters.
1 cl, 8 dwg
FIELD: mobile radio communication systems.
SUBSTANCE: proposed method and device are intended to control transmission power levels for plurality of various data streams transferred from at least one base station to mobile one in mobile radio communication system. First and second data streams are transmitted from base station and received by mobile station. Power-control instruction stream is generated in mobile station in compliance with first or second data stream received. Power control signal is shaped in mobile station from first power control instruction stream and transferred to base station. Received power control instruction stream is produced from power control signal received by base station; power transmission levels of first and second data streams coming from base station are controlled in compliance with power control instruction stream received. In this way control is effected of transmission power levels of first data stream transferred from each base station out of first active set to mobile station and of transmission power levels of second data stream which is transferred from each base station out of second active set to mobile station.
EFFECT: enlarged functional capabilities.
80 cl, 21 dwg
FIELD: radio engineering.
SUBSTANCE: proposed method and device designed for fast synchronization of signal in wade-band code-division multiple access (WCDMA) system involve use of accumulations of variable-length samples, testing of decoder estimates for reliability, and concurrent decoding of plurality of sync signals in PERCH channel. Receiver accumulates samples required for reliable estimation of time interval synchronization. As long as time interval synchronization estimates have not passed reliability tests, samples are accumulated for frame synchronization estimates. As long as frame synchronization estimates have not passed reliability tests, samples are analyzed to determine channel pilot signal shift.
EFFECT: reduced time for pulling into synchronism.
13 cl, 9 dwg
FIELD: satellite navigation systems and may be used at construction of imitators of signals of satellite navigational system GLONASS and pseudo-satellites.
SUBSTANCE: for this purpose two oscillators of a lettered frequency and of a fixed frequency are used. Mode includes successive fulfillment of the following operations - generation of a stabilized lettered frequency, its multiplication with an oscillator's fixed frequency and filtration of lateral multipliers with means of filters of L1 and L2 ranges and corresponding option of a fixed and a lettered frequencies.
EFFECT: reduces phase noise and ensures synthesizing of lettered frequencies of L1 and L2 ranges of satellite navigational system from one supporting generator at minimum number of analogous super high frequency units.
3 cl, 1 dwg