Dynamic wave-pipelined interface and a method for its use

 

The claimed invention relates to data processing systems, in particular to the bus interfaces. The technical result is to enable the alignment of the data at the receiving side of the interface. This interface contains a delay device, scheme job each pre-selected delay period, the logical comparison circuit data and schema to change the pre-selected periods of delay. In the way of data signals received from the transmitting circuit are delayed using a programmable delay device corresponding to each signal, and then fixed receiver, a programmable delay is set for each device delays when carrying out the initialization procedure, the result is the alignment of each signal according to the latest arriving signal. In addition, the phase of the clock signal I / o, control latching data signals is adjusted so that the transition of fixation data was located almost in the middle of the window, the reliability of the data. 3 c. and 12 C.p. f-crystals, 5 Il.

The present invention relates to data processing systems, in particular to tire intersnyh, reflecting the increased clock frequency of CPUs that should appropriately increase the speed of data transfer on the system bus. The speed of data transfer on the bus connecting the components of a data processing system, is naturally limited by the physical separation of the components. One of the developed methods of data transfer on the bus is a wave pipeline method, in which the data signal is transmitted on the bus before the previous data has been captured by the receiving device on the bus. In other words, the data is sent via the bus interface between the elements of the data processing system as in the "pipeline". After filling in the "pipeline" data is delivered at an average speed exceeding the timeout for an interface.

In a typical data processing system can be transmitted from the transmitting device to multiple receiving devices. Different receivers will be connected with the source or transmitting device via the bus interfaces having different length of the electric path and, therefore, different timeout.

In addition, if a device receives a lot of data signals, each signal can bili, for example, differences in the length of lines, and in connection with time-dependent effects, for example, data-dependent jitter (intersymbol interference), the jitter of the clock signal and the noise.

In addition, it is assumed that the data will be received synchronously. That is, it is expected that data will be received on a previously defined quantum system clock generator. If the data arrives earlier or later than expected, errors may occur.

In wave-pipelined interface analysis of temporal dependencies is more complex, as equally important as the fast and slow path. Decreases the interval reliability of the data, i.e. the time interval during which possible reliable data reception, as it increases the time difference between the fast and slow paths connecting the source or transmitting device to one or more receiving devices. The synchronization will be lost if the time difference between the fast and slow path reaches the period of the clock signal. In addition, the clock skew of the clock signal receiving device may further narrow the scope of validity of the data. Increasing performance interf tenovate tolerances on the clock skew of the clock signal. However, the management of the clock skew of the clock signal and differences over time may be limited by the physical characteristics of the system data. In this regard, there is a need for methods and devices that enable alignment of the data at the receiving side of the interface, and also increase the period of time during which it can be made reliable data reception.

In the US 5229668 describes the data signal, which can be taken at high speed using the clock signal by passing the data signal and the clock signal through a series of delay elements of the data and the clock signal, respectively, and latching the delayed data signal and the clock signal. Thus, the reception rate is controlled by the relative clock skew of the clock signal and data signal, which may be made relatively small and may be limited only by noise and random deviations in manufacturing. This can be obtained a high sampling rate".

In Wong and others in "Inserting Active Dalay Elements to Achieve Wave Pipelining" describes the algorithms for automatic adjustment of the delay by entering the minimum number of active elementality way which would allow to eliminate the above drawbacks.

In accordance with the present invention, an interface with a lot of delay devices, each of which serves to receive a respective data signal and has a pre-selected delay period, and outputs the data signal after a preselected delay period, and a circuit connected with many devices delay and is used to specify each pre-selected delay period based on the time of receipt, with the specified scheme, designed to set each pre-selected delay period, has a logical comparison circuit data, designed to receive a specified subset of data signals and to output the first set value of the output signal when a specified subset of data signals includes the first set of values, and to output the second set value of the output signal when a subset of data signals includes a second specified set of values, and, depending on the time of receipt of a specified subset of data signals includes one of these parvovernyh periods of delay depending on the first and second set values of the output signal.

Features and manner of performing dynamic wave pipelining interface with many devices delay and a circuit connected with many of these devices delay, namely, that admit using these delay devices, each of which has a pre-selected delay period corresponding to the data signal and the output of the data signal after a preselected delay period, and using the specified schema ask each pre-selected delay period, each of such pre-selected periods of delay set on the basis of the time of receipt, with the specified circuit has a logic circuit comparing the data designed to receive a specified subset of data signals and to output the first set value of the output signal when a specified subset of data signals includes the first set of values, and to output the second set value of the output signal when a subset of data signals includes a second specified set of values, and, depending on the time of receipt of a specified subset of data signals of vklucheniya pre-selected periods of delay depending on the first and second set values of the output signal.

It is also proposed a data processing system to interface with a Central processing unit (CPU) and the receiving device, which is connected with this CPU and is designed to receive at least one data signal from the CPU and which has a block of data reception interface according to the invention.

Above was given a rather General description of the features and technical advantages of the invention, to make it more clear below its detailed description. Hereinafter will be described further features and advantages of the invention.

Below the invention is described in more detail on the example of some variants of its implementation with reference to the accompanying drawings on which is shown: in Fig. 1 is a structural diagram of a data processing system in accordance with the embodiment of the invention, Fig. 2 is a structural diagram of a variant of implementation of the dynamic wave-pipelined interface in accordance with the invention, Fig. 3 - input timing diagram for the interface shown in Fig.2, in Fig. 4 is a structural block circuit diagram of the reception data in accordance with the embodiment of the invention, Fig.5A is a block diagram of a technique in accordance with the embodiment of the invention, f is of, in Fig. 5B is a timing diagram corresponding to the shown in Fig.5B, the method of Fig. 5G is a block diagram of a data alignment method in accordance with the embodiment of the invention, Fig. 5D is a timing diagram corresponding to the shown in Fig.5G way,
in Fig. 5E is a block diagram of a method of adjusting the phase of the clock signal in accordance with the embodiment of the invention, and
in Fig. I - time diagram corresponding to the shown in Fig.5E method.

In accordance with the present invention serves wave conveyor mechanism to reduce the difference in time of arrival of the data and the jitter of clock pulses. When performing the initialization procedure can be increased zone size the reliability of the data, with a corresponding reduction in the sensitivity of the interface to the temporary differences between the connected to the bus circuits. Temporary differences for the set of data signals received at a receiving device, are eliminated by defining data signals, which come very first and the most recent, and retaining data signal, which comes first, at pre-selected magnitude determined by the difference remunerative clock signal, coming from a transmitting device, and thus obtained the clock signal centered approximately on the data window.

In the further description for a detailed understanding of the essence of the present invention provides a large number of specific data, such as clock frequency tires, the fronts of the clock signals, and so on, But experts it is clear that the invention may be practiced without such specific data. In other instances, well known circuits are shown in the form of structural diagrams, in order not to burden the invention with unnecessary detail.

Below, Fig.1-I on which items are not always portrayed in scale and in which identical or similar elements are denoted by the same numbers of items.

In Fig. 1 shows the hardware that can be used in the present invention, and represents a typical hardware configuration of the processor 100 data according to the invention, which includes a Central processing unit (CPU) 110, such as a conventional microprocessor, and a few other blocks connected by a system bus 112. Part of processor 100 data includes a storage device 114 with a random sample (NVR), a persistent storage device is of Savadov 120 and drives 140 tape, the adapter 122 user interface designed to connect to the bus 112 keyboard 124, mouse 126 and/or other devices of the user interface such as a touch screen (not shown), communication adapter 134, designed to connect the processor 100 to the network data, and a display adapter 136, designed for connecting the bus 112 to a display device 138. The composition of the CPU 110 may include others not shown here schemes, including schemes, usually included in the microprocessor, such as an operating unit, a connection unit with a communication unit arithmetic logic, and so on, the CPU 110 may also be included in one integrated circuit.

In Fig. 2 shows wave-pipelined interface 200 in accordance with the invention. The interface 200 is embedded in each of the circuits 202 and 204, which communicate with one another using interface 200. In the embodiment of the invention the chips 202 and 204 may, for example, to match the CPU 110 and NVR 114 of the processor 100 of the data. The data transmission between the chip 202 and 204 are transmitted at a speed determined by the clock signal bus, a clock signal 206 and 208 of the tire. Clock signals 206 and 208 bus nominally have the same frequency and out osnovan of the invention reference clock signal 310 may be a system clock signal. Each of the PLL 212 generates a local clock signal 214 in the chip 202 and the local clock signal 216 in the chip 204, which is synchronized in phase with the reference clock signal 310 and the period which may be equal to the period of the reference clock signal 310, multiplied by a pre-selected integer M Local clock signal 214 buffered driver 218 the purpose of receiving the clock signal 206 bus for the chip 202. Similarly, the local clock signal 216 buffered driver 220 with the aim of obtaining the clock signal 208 bus for chip 204.

A clock signal is sent to the chip together with the transmitted data. Data 222 of the chip 202 are fixed output schema-latch 224 and output and buffered by the driver 226. Data is recorded on a pre-set edge of the local clock signal 214. Data is received using a multiplexer 228. During the procedure the initial alignment (IRP) multiplexer 228 also receives a predefined synchronization sequence. Detailed explanation is given below.

Data 222 buffered receiver 230 and sent to the block 232 receive data. The clock signal 206 is inhibiting signal 236 I/o, also sent in block 232 receive data. Data from the chip 204 is sent to the chip 202 together with a clock signal bus 208, similarly accepted by the interface 200 in the chip 202, and it is obvious that the following description of the block 232 receive data in the same extends to the receiving chip 202 data from the chip 204.

In Fig. 3 shows a timing diagram of arrival of the data 222 to the input circuit 204. Although synchronization is described for data 222, the interface 200 is a two-way, and similar chart applies equally to the transmission data sent from the chip 204 in the IC chip 202. The first data signal, the data 302, comes after a nominal time-out associated with the end time of the transmission path between the chip 202 and 204. In Fig.3 shows that the data 302 received at the initial moment of time T0. For the second data signal, the data 304, the wait time will be longer wait times for data signal 302, and their arrival is delayed relative to the initial time by the amount TSwhich will be the maximum time delay for the set of data signals transmitted with a delay on the data bus 222. Similar obrazach 302. The diagram shows that the data 306 are received before the initial moment of time T0the value of Tf. In the subsequent description of the operation of block 232 receive data it is assumed that the value of Tfcorresponds to the earliest time of receipt for a variety of data signals received on the data bus 222 to the initial moment of time. The difference between the time of receipt of data on the data bus 222 is called clock skew data. The clock skew data can be caused by various reasons, including tolerances in the manufacture, design constraints, such as differences in the length of lines, and time-dependent effects, such as data-dependent jitter (intersymbol interference), the jitter of the clock signal and noise. (For simplicity, image timing diagram of Fig.3 the initial moments of time are shown in relation to the centers of the transitions. Specialists will be clear that the allowed transitions can be defined in relation to other pre-specified percentage values from steady state values).

Data is recorded receiving device such as a chip 204, on the front of the clock signal 236 input/output. In the absence of clock skew data of movado/o. The clock skew of the data reduces the width of the window the validity of the data Twthe sum of the values of Tfand TS.

In order to restore the width of the window the validity of the data interface 200 in accordance with the present invention introduces a lot of data signals in block 232 receive data shown in Fig.4. Data is buffered by the receiver 230 and transmitted to programmable line delay device, in one of the lines of devices 406-408 delay. Programmable line device 406-408 delays provide a preset delay signal input to the delay line. A delay line receiving the signal from the most recent time of arrival corresponding to the data 304 in Fig.3, programmable zero delay. (Obviously, for each chain has a minimum propagation time of a signal. It is also clear that the zero delay is relative to this minimum time of flight). Thus, for shown in Fig.4 example, the data 402 correspond to 304 in Fig.3, and for the line device 408 delay is programmable zero delay. Delay line, receiving other data signals can be programmed for all large values of delay, and the delay line, the I on the maximum delay. Thus, for shown in Fig.4 example, the data 404 correspond to the data signal with the earliest arrival time, and the delay line device 408 is programmed for the maximum delay value. In this case, all signals input to the chip 204, i.e., data 402-404, aligned with the data signal with the latest arrival time. Although the alternative embodiment of the invention shown in Fig.4 has been shown and described for the individual data signals, it is obvious that the principles of the invention can be applied to groups of data signals, such as data bytes or any other groups of data signals. This alternative embodiment of the invention will be asked to meet the claims of the frame.

Delay line devices 406-408 programmed for pre-selected delay values during execution of the initialization procedure align (IRP). BEERS can be performed at power-up or reset of the processor 100 of data processing, which has a wave-pipelined interface 200. In the embodiment of the invention, execution of the BEERS can be controlled by the signal of the CPU 110 shown in Fig.1. When performing BEERS predvaritel BEERS, thus the multiplexer 228 displays the predefined synchronization sequence. The sync sequence is sent with all data signals transmitted on the data bus 222.

The sync sequence is fixed circuits-latches 412-414, which take the output signal of delay line devices 406-408. Input circuit-latch 412-414 data is recorded on the front of the clock signal 236 I/o, which is derived from a clock signal 206 bus using buffer 234. The clock signal 236 I/o is delayed in the device line 410 delay unit 232 receive data. The delayed clock signal I/o is regenerated in the buffer 416 and sent to the circuit-latch 412-414.

The line control device 410 delays and lines of devices 406-408 delay is performed using a finite state machine 418. When performing BEERS state machine 418 adjusts the programmable delay line devices 406-408 and 410 delays in accordance with the takeover of the synchronizing sequence circuits-latches 412-414.

Outputs 420-422 connected to respective inputs of the logic circuit 424 comparison data. Use appropriate synchronization follow the battle clock skew data. One such sequence is a sequence of data values "100010001000". This sequence is periodic, and its period is equal to four periods of the clock signal I/o, this sequence is used for flexible interface that has a degree of flexibility, equal to four periods of the clock signal. Flexible interface described in the simultaneously filed by the applicant in the application for U.S. patent entitled "An Elastic Interface Apparatus and Method Therefor" ("Flexible interface and method of use"), which is incorporated into this description by reference. Can be used and another synchronization sequence, provided that such synchronization sequence should provide a clear resolution of synchronous data capture. For example, alternatively, can be used synchronization sequence, which is complementary to the above sequence data. Next will be described the choice of the delay line devices 406-408 and 410 delays, and thus will be described the operation of the state machine 418.

In Fig.5A illustrates a method 500 of selecting delays using a finite state machine 418. In step 502 taktovima delay line device 410 delays. Step 502 is further described using Fig.5B and 5B. The data signals are aligned in step 504, which will be further described using Fig. 5G and 5D. In step 508 adjusts the point of reception clock signal input/output. Step 508 will be further described using Fig.5E and G.

In Fig. 5B shows a block diagram of step 502 delays the clock signal input/output. In step 512 is the start of BEERS together with the input synchronizing sequence, as described above. In step 514 the state machine 418, shown in Fig.4, determines whether the synchronization sequence, fixed circuits-latches 412-414, the same data signal, which for the above example, the synchronization sequence is equal to "1". The state machine 418 determines whether there was recorded the same data signal, by determining whether the reset output 426 RS-flip-flop 428. The output 426 of the RS-flip-flop 428 is controlled by a logic circuit 424 comparison data, which reveals the absence of coincidence, and in this case produces a positive signal on its output 430. In that case, if all inputs 421-423 logic circuit 424 cravedi reset RS flip-flop. Logic circuit 424 comparison data strobiles using the delayed clock signal 411 I/o, and thus the output signal at the output of the logic circuit 430 424 comparison-based data capture circuits-latches 412-414. An example implementation of the logic circuit 424 comparing the data corresponding to the positive logic is to use the logical NOT function for signals at the inputs 421-423 and the gate signal generated based on the delayed clock signal 411. In an alternative embodiment, with negative logic can be used logical function OR for inputs 421-423 and the gate signal generated based on the complement of the delayed clock signal 411. Such an implementation option will meet the above additional synchronizing sequence.

Statistical variations when setting delay line devices 406-408 and 410 delays can be reduced by receiving a synchronizing sequence for a large number of cycles of the delayed clock signal 411 input/output. The delayed clock signal 411 I/o calls increment the counter 432. what drove 411 I/o, after the transfer trigger 432. The output 434 of the counter 432 is connected to the input 436 reset RS-flip-flop 428, resulting in a reset output 426. Can be performed in the next clock sequence / sequence identify discrepancies. If for any cycle control will detect a mismatch, it will be set to RS-flip-flop 428.

Fig. 5B: if during the control period, determined by the value of the integer K, for all inputs 421-423 logic circuit 424 comparison data is one data signal, then in step 514 is executed branch "Yes", and for the method 500 will be passed to step 504. For this case will act shown in Fig.5V timing diagram for which have not yet been specified delay line devices 406-408 delay. The clock signal 236 I/o is delayed using the line device 410 delays on the value of Tdand the front t1hits the window the validity of the data defined by the time interval TW.

Initially, the delay time Tdmay be zero, while the front T0outside the window the validity of the data, and on the front of the T0fixing the values "1" to one of the schemes-W is the fall. This displays the signal on the output of the logic circuit 430 424 comparison data, and the signal on the output 426 of the RS-flip-flop 428. As a result, the step 514 of Fig.5B is used, the branch "No". In step 516 the state machine 418 increases the delay time for the device line 410 delays.

The delay increases by the state machine 418 via the signal "Up" in the direction of the count 438 reversible counter 440. The counter 440 is increased in the case of filing a counter 432 of the signal at the output 434 of what is happening in the case that the counter 432 end of the interval of summation specified by the value of the integer K. Readings reversible counter 440 is sent in block 442, the control delay. Block 442 control delay decodes the counter and sends a corresponding control signal 444 in-line device 410 delays, resulting in a line device 410 delay increases the time delay Tdby a preset amount of time. (Programmable line device 410 delays, which can be used in the invention described in the simultaneously filed by the applicant in the application for U.S. patent entitled "Programmable Delay Loccked Loop" ("Device software is eriki clock signal input/output returns to step 514.

If at step 514 the increased value of Tdwill be enough to put the front t1the validity of the data, then in step 514 will use the branch "Yes", as described above. Otherwise, the delay line device 410 delays will be raised again in step 516 and step 502 delays the clock signal input/output is cyclically repeated at steps 514 and 516 as long as the front t1do not fall into the window of validity of the data. After that, the state machine 418 goes to step 504, which is the alignment of data.

Step 504 data alignment is described in detail using Fig. 5G. In step 504 is programming multiple lines of devices 406 - 408 delays. In step 518 to perform programming selects the first delay line, corresponding to the first data signal. (This may correspond to the initialization of the index j for the first value, and this index may be zero). In step 520 compares the data. Comparison of the data in step 520 is exactly the same as the comparison data in step 514 of Fig. 5B, and the poet is and 522 will be set to increment the delay for the j-th delay line, the corresponding j-th data signal. Originally due to step 502 to adjust the clock signal I / o for step 520 will use the branch "Yes". After increment delay in step 522 is executed again step 520 comparison data. Then step 504 alignment data will be cyclically repeated between steps 520 and 522, until synchronization is lost data and at step 520 will not be executed branch "No", in which in step 524, the delay of the j-th data signal will be reduced by one increment delay. Thus, it can be made in the alignment phase of the j-th signal data clock signal I/o.

For clarity it should again refer to Fig.5V. If for example first be assumed that in steps 520 and 522 j-th data signal is a data signal from the most recent time of arrival data 304, then the addition of the first increment of delay for the delay line will lead to such offset data 304 that their front t2will arrive after the front t1the delayed clock signal 411 input/output. Then, when performing the comparison data at step 520, the comparison will be made by the branches "No" to step the signal from the most recent time of arrival will not add additional delay. It is desirable to perform step 504 alignment data, as the signal from the most recent time of arrival can be used as a reference signal to align all other data signals.

Now for the example considered, the steps 520 and 522 for data signal, which data signal with the earliest arrival time - data 306 in Fig.5V. For signal data with the earliest arrival time is a multiple increment delay for the corresponding programmable delay line by repeating steps 520 and 522 as long as the front t3this signal will not come later front t1the delayed clock signal 411 input/output. After that, as described earlier for data 304 to step 520 comparison data is executed branch "No" to step 524, where the programmable delay will be deducted one increment of delay, and the front t3will be aligned at the front of the t1the delayed clock signal 411 I/o.

After alignment of the j-th data signal at step 526 step 504 data alignment is determined whether all programmed delay of the data signals. If not, then at step 527, and Sha is the programme of all delay lines all the data signals are aligned at the front of the t1the delayed clock signal 411 I/o, as schematically shown in the timing chart of Fig.5D, and from step 504 alignment shifts to step 506 of method 500.

In step 506 adjustment point of the reception clock signal front t1the delayed clock signal 411 I/o can be shifted to the center of the window, the reliability of the data. Although the front of the clock signal may be centered at startup, however, the receiver can occur at the clock skew caused by differences timeout ways, noises and so on, Step 506 adjusting the position of the reception point aligns the clock signal. Next, at step 528 compares the data (Fig.5E).

Originally due to step 506 data alignment for step 526 comparison is the branch "Yes" to step 540, in step 530 increments of delay time programmed for the line device 410 delays, by one increment. After step 506 adjustment point of the reception clock signal returns to step 528, which again compares the data. Then for step 506 adjustment point of the reception clock signal is a cyclic repetition of steps 528 and 530 until rannego clock signal 411, denoted by t1'that went on the late side of the t1Windows reliability of the data, Fig.G. Then for step 528 comparison data is the branch "No" in step 532 retain the value counted by the counter 440.

Then at step 506 the adjustment point of the reception clock signal is determined by the early side of the window is the reliability of the data. In step 534 for one increment value increases the delay line device 410 delays. Then in step 536, the system compares the data. Due to the fact that at step 534 the front t1' was again shifted in the window of validity of the data, then step 536 comparison data is the branch "Yes" and the delay programmed for the line device 410 delays, additional decreases by one increment value. After step 506 adjustment point control clock signal cyclically repeated steps 536 and 538, while in step 536 comparison data will not be identified discrepancy. This indicates that the front of the t1the delayed clock signal 411 I/o in Fig.I received before the early part of teopen the validity of the data. This transition of the delayed clock signal 411 I/o is denoted by t1". Then for the us.

In step 542 to the phase of the delayed clock signal 411 I/o is set to the average value for the fronts of the early and late sides of the validity of the data. In Fig.J this corresponds to the solid part of the curve of the delayed clock signal 411 I/o and front t1"'. After step 506 adjustment of the point of reception of the delayed clock signal occurs a transition to step 508, and the method 500 ends the mode of BEERS.

The device and methods illustrated in the above example embodiments of the invention allow to obtain a dynamic wave-pipelined interface. For many coming into the interface data signals are aligned relative to one another to compensate the difference of the synchronization of data signals, the difference of paths between a clock signal input/output and data signals, as well as constructive tolerances for data signals, for example, for connecting the wires to the chip module and the circuit Board. As a result of this increased width region of the data signal. The interface also adjusts the clock signal to be centered at the point of reception in the middle of the window the validity of the data, the result can be Compi Board.


Claims

1. Interface with lots of delay devices, each of which serves to receive a respective data signal and has a pre-selected delay period, and outputs the data signal after a preselected delay period, and a circuit connected with many devices delay and is used to specify each pre-selected delay period based on the time of receipt, with the specified scheme, designed to set each pre-selected delay period, has a logical comparison circuit data intended for the reception of a specified subset of data signals and to output the first set value of the output signal, when the specified subset of data signals includes the first set of values, and to output the second set value of the output signal when a subset of data signals includes a second specified set of values, and, depending on the time of receipt of a specified subset of data signals includes one of the first and second predetermined sets of values, and it also has a scheme, prednaznachennoi output signal.

2. Interface under item 1, in which the first data signals is a clock signal.

3. Interface under item 1, in which the first specified set of values is a set of values, where all values are equal, and the second set of values is a set of values in which the first and second elements have different values.

4. Interface under item 1, in which the scheme is intended to change the pre-selected periods of delay, has a state machine to change the pre-selected periods of delay depending on the first and second values of the output signal.

5. The interface on p. 4, in which the scheme is designed to change the specified delay periods, also has a counter that is designed to receive a signal direction from the state machine and the output count to determine the number of increments of the delay period to change the pre-selected periods of delay, with an increment of delay time has the specified value.

6. Interface under item 5, in which the scheme is intended to change the pre-selected periods of delay, also has a control circuit delay intended DM control signal is used to change the pre-selected periods of delay.

7. Interface under item 1, in which the scheme is intended to change the pre-selected periods of delay depending on the first and second set of signals has a storage device, an input connected to the logical comparison circuit and the logic state of which is determined upon receipt of the first predetermined signal and is reset upon receipt of the second predetermined signal, a counter which is connected to that storage device and is used to reset upon reaching the counting some specified value, and scheme to determine the logical state storage device and to change the pre-selected periods of delay, based on a specified logical condition.

8. The method of performing dynamic wave pipelining interface with many devices delay and a circuit connected with many of these devices delay, namely, that admit using these delay devices, each of which has a pre-selected delay period corresponding data signal and the output of the data signal after a preselected period sady of these pre-selected periods of delay set on the basis of the time of receipt, while this circuit has a logic circuit comparing the data intended for the reception of a specified subset of data signals and to output the first set value of the output signal when a specified subset of data signals includes the first set of values, and to output the second set value of the output signal when a subset of data signals includes a second specified set of values, and, depending on the time of receipt of a specified subset of data signals includes one of the first and second predetermined sets of values, and it also has a scheme, designed to change the pre-selected periods of delay depending on the first and second set values of the output signal.

9. The method according to p. 8, in which the first data signals is a clock signal.

10. The method according to p. 8, in which the first specified set of values is a set of values, where all values are equal, and the second set of values is a set of values in which the first and second elements have different values.

11. The method according to p. 8, in which the scheme is intended to change the pre-vibraphonist from the first and second values of the output signal.

12. The method according to p. 11, in which the scheme is designed to change the specified delay periods, also has a counter that is designed to receive a signal direction from the state machine and the output count to determine the number of increments of the delay period to change the pre-selected periods of delay, with an increment of delay time has the specified value.

13. The method according to p. 12, in which the scheme is intended to change the pre-selected periods of delay, also has a control circuit delay, which is designed to receive a signal count and transmitting a control signal to each of multiple devices with a delay, while the control signal is used to change the pre-selected periods of delay.

14. The method according to p. 8, in which the scheme is intended to change the pre-selected periods of delay depending on the first and second set of signals has a storage device, an input connected to the logical comparison circuit and the logic state of which is determined upon receipt of the first predetermined signal and is reset upon receipt of the second predetermined signal, the counter that aedilician, and scheme to determine the logical state storage device and to change the pre-selected periods of delay, based on a specified logical condition.

15. A data processing system to interface with a Central processing unit (CPU) and the receiving device, which is connected with this CPU and is designed to receive at least one data signal from the CPU and which has a block of data reception interface according to any one of paragraphs.1-7.

 

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2 cl, 2 dwg

FIELD: computer engineering, namely, local computer networks, in particular, home networks based on universal serial buses.

SUBSTANCE: device for data transmission contains a cable with signal lines, power buses, microchip of computer controller which generates commands which determine operation of peripheral device, microchip of device controller which control directions of streams of data being transmitted, positioned in a peripheral device, two microchips of transformers of signal levels from contacts of control microchips, four circuits for correction of transfer characteristic of signal lines of cable, four matched loads, two stabilizer circuits and four filters meant for reduction of power noise.

EFFECT: removed limitation on length of used cable, possible usage of various types of cables without necessity to develop expensive microchips for repeaters each time, which have functions of double purpose: matching of impedance of cable and controllers and transformation of levels of signals from outputs of controller microchips.

5 dwg

FIELD: information technologies.

SUBSTANCE: for assessment of data in data formats incapable of direct assessment, which are transmitted between geodesic instruments, reference catalogues or data catalogues are used. Specified catalogues are preferably transmitted together with transmission of data and assessed data fields are indicated in data formats. If geodesic instrument accepts data format incapable of direct processing, then by means of reference catalogue (10) assessed data fields may be found, and with the help of data catalogue data fields incapable of assessment may be used.

EFFECT: method improvement.

17 cl, 17 dwg

FIELD: physics, communication.

SUBSTANCE: invention concerns resorts of maintenance of infrastructure of message transfer which during performance abstracts operations of parcel and reception for exchange of messages with terminal point of the partner. Message infrastructure accepts commands from the appendix the message transfers setting guarantees of through delivery; uses mechanisms of transportation for satisfaction of requirements of the given guarantees of delivery, and creates communication between the application of message transfer and mechanisms of transportation for use at an exchange of conferrings. Storage of a state of a session can be supported in connected storehouse which can be, for example, storehouse of a database of the long-term storage or storehouse of storage of the application.

EFFECT: improvement of availability and scalability of the message transmission application by means of improvement of availability and scalability of underlying mechanisms of messages transportation.

71 cl, 4 dwg

FIELD: physics, computer equipment.

SUBSTANCE: invention concerns systems of a priority of applications. In the method and system carry out reception of the inquiry requesting allocation of the most appreciable resource to the requesting application, and determination of that such most appreciable resource is oozed to the possessing application; associative interlinking of the information on the owner with the information on a requester to generate inquiry of arbitration; performance of arbitration of inquiry of arbitration for development of the arbitral award which specifies, that the most appreciable resource should be oozed to the requesting application if the information on the owner specifies, that the owning application is exclusive, and the identifier which identifies the requesting application, contains in the voiding list, is associative related to the information on the owner.

EFFECT: maintenance of dynamic allocation of the most appreciable resource of the device.

24 cl, 7 dwg, 1 ex

FIELD: physics, computer facilities.

SUBSTANCE: invention concerns computer facilities, namely to field of local computer networks. The device contains the computer, signal lines (SL1, SL2), four cables, a microcircuit of the controller of the computer, a microcircuit of controllers of remote terminal units, microcircuits of controllers of hubs (H1, H2) and the universal serial busbar, the optimum loads (OL1, ..., OL10), voltage regulators (VR1, VR2), filters (F1, ..., F5), intended for noise reduction on supply, compensation circuits (CC1, ..., CC4) of transitive performance of the cable signal lines, the shared bus (SB1), the supply busbar (SBB1), the power supply (PS1), and also N data links DL1, ..., DLM.

EFFECT: increase of the peak speed of data transmission between the computer and remote terminal units to 480 Mbit/with at simultaneous magnification of quantity of data links with connected remote terminal units and lengths of a used cable on which packages of the numeral information including with high speed can be transmitted.

2 cl, 6 dwg

FIELD: physics, communication.

SUBSTANCE: invention is related to the field of communication realisation between master and slave devices with application of bus interface. According to one aspect, outlet or outlets of three-wire interface are selected in the first mode, and outlet of one or several single-wire interfaces is selected in the second mode. According to the other aspect, converter addresses single-wire bus and generates signals in compliance with three-wire interface. According to another aspect, completion signal is inserted into single-wire interface signal, which facilitates conversion of this signal and connection to three-wire interface. According to the next aspect, in response to detected initial symbol strobe signal and/or clock signal are generated. According to another aspect, strobe signal and/or clock signal are deactivated in response to detected completion symbol.

EFFECT: provision of compatibility between existing serial bus interfaces and single-wire bus interface.

32 cl, 35 dwg, 5 tbl

FIELD: digital data transferring technologies.

SUBSTANCE: digital serial transfer of information through interface between electronic device and accumulator connected to it is a transfer of bytes consisting of row of bits. Each bit is determined by one of levels, high level or low level, and first bit of each byte is a first level of said high and low levels. Method includes stage of transfer of other level from said low and high levels during first time span immediately before said first bit.

EFFECT: higher efficiency.

3 cl, 4 dwg

FIELD: electronics.

SUBSTANCE: method includes generation of first strobe signal and second strobe signal, presetting of one of said first or second strobe signals prior to first data transfer, post-setting of said preset signal, determining which of said first and second signals is to be post-set, and presetting of one of said first or second strobe-signals before second data transfer.

EFFECT: higher speed of data transfer.

3 cl, 5 dwg

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