Semiconductor memory device with non-volatile memory cells two transistors

 

The invention relates to a semiconductor memory device. The technical result is error-free programming a semiconductor memory device. The device contains at least one cell of former residence, including selective transistor with a channel of n-type memory transistor with a channel of type n, the transition of the transistor with a channel of type p, the vertical and horizontal bus. 5 C.p. f-crystals, 2 ill., table 2.

The invention relates to a semiconductor memory device, at least one, in particular, non-volatile memory cell, which has the following distinctive features: - a selective transistor with a channel of type n, and a storage transistor with a channel type n - selective transistor with channel n has a selective output of the shutter, and two selective channel output, and the selective output of the gate is connected with leading to the memory cell horizontal bus - a memory transistor with a channel of type n has a storage output of the gate or the control gate, and two memory channel output, the second storage channel output and the first election of kanalni the capacity output is connected with leading to the memory cell vertical bus, moreover, the semiconductor storage device has at least one transition effect transistor with the first and second transition duct conclusions, and the first transition channel output is connected with a memory output gate.

When a standard semiconductor memory devices separate transistors made according to the technology field-effect transistors (FET) on a single semiconductor substrate. While the memory transistor has a floating gate (floating gate), so he by supplying appropriate voltages to channel the findings and conclusion of the shutter can be programmed so that it is permanently or non-volatile can take the desired state.

For reading the memory cells of the memory channel output and selective channel output can be interconnected and another available storage channel output or another free election channel output connected to leading to the memory cell of the vertical bus. This selective transistor is controlled so that it conducts. If then, when a voltage is applied to the corresponding vertical bus current flows, then the memory transistor in the previous step was programmed to "conductive" or recorded. , what about the memory transistor in the previous step was programmed to "non-conductive" or erased.

In EP 0317443 A1 shows a memory cell with two transistors, which includes the selective transistor and the transistor with a floating gate. The gate of the transistor with a floating gate to control is loaded in a special voltage.

With standard storage devices particularly problematic is the fact that necessary for the programming voltage must be high technological costs. Moreover, when programming memory cells often errors occur in other memory cells, which at this time was not made application for programming.

Therefore, the object of the invention is the manufacture of the memory cell, and standard semiconductor memory device which can accurately be programmed with little technological effort.

This problem is solved due to the fact that the transition of the transistor is designed as a transition-effect transistor with a channel of type R, and the second transition channel output is not connected, as at the present level of technology, with external voltage control satva what about when the standard regimen must overcome the loss of the threshold voltage in the transition transistor, so it should provide a higher voltage transition of the shutter. This problem can be solved due to the fact that the transition of the transistor is performed as a transistor with a reduced threshold voltage, which, however, should pay off in increased process costs.

When executed in accordance with the invention and incorrect inclusion of the transition of the transistor for programming the memory transistor is no longer necessary to overcome the threshold voltage of the transition of the shutter, so maybe reliable programming with little technological effort.

The invention is based further on the knowledge that the voltage of the control gate on the basis of specific wrong turn on transition of the transistor in the prior art with modern unmanaged memory cells "floats" in an uncertain free course that can lead to capacitive relations above the critical voltage programming. Such capacitive coupling above the critical have no more space in memory cells of a semiconductor memory device in accordance with the invention, as when programming a semiconductor memory device ka the aqueous transistor when executed in accordance with the invention can be loaded changed to a high voltage logic signal. More efficient to use a logical signal which also controls the corresponding state of programming of the memory cell. Through the execution of the transition of the transistor as the transition of the transistor with a channel of type R. this eliminates the need for expensive for manufacturing the inverter to control the output transition of the shutter, as the transition effect transistor with a channel type p then locked, if controlled by the shutter, and Vice versa. In principle, the transition effect transistor with such an inverter yet can also run as a transition-effect transistor with a channel of type n.

With the help of the device in accordance with the invention, the full programming voltage can be made without loss or other special events through the channel of the transition of the transistor on the findings of the storage gates.

Incidentally, it is worth mentioning that the invention also can be implemented by a storage device in which storage and selective transistors are implemented as transistors with channel type p, if the transition of the transistor in this case is performed as a transistor with a channel of n-type. Such a device is still rather uncommon, however may prevacid.

The improvement of the invention the control circuit has a discharge transistor with a channel of type n, which is the output of the discharge gate, and first and second discharge channel conclusions, and the first discharge channel output connects to the output of the memory gate and the second discharge channel output is connected to the mass and the output of the discharge gate is connected to the control bus through which is controlled by the transition of the transistor.

Such a discharge transistor during programming of the memory cell ensures that the output storage gate during the programming process is at a certain potential, in particular when the potential of the mass. Just when locked transitional transistor due to this, it is guaranteed that the output of the memory gate is definitely at a potential of 0 Century.

The semiconductor memory device in accordance with the invention arranged in rows and columns and within rows conclusions selective gates and conclusions of storage gates multiple memory cells connected in parallel and within the columns of the first memory channel conclusions or second election cojet especially simply be grouped into rows and columns.

Provides at least one column control circuit which is included correctly in accordance with the invention, the transition of the transistor. The control circuit may further have one transistor selection unit channel type p o shutter unit selection, as well as two channel terminals of the selection unit, and the first channel output selection unit connected with leading to the memory cell horizontal bus and the second channel output selection unit connected to the first transitional channel output. Due to this semiconductor memory device for programming memory cells may be divided into separate blocks, which is particularly preferable, because it is no longer necessary to program certain conditions for the entire row of a semiconductor storage device, but only to selected from this line of block. Due to this, in particular, it is also possible to erase single block. This includes the management bus selection block, which connects to the terminals of the gates of the selection unit so that the transistors of the selection blocks can be managed via a management bus selection block.

From the military's wrong, as mentioned above, the transitional transistor.

The invention is described in more detail below with reference to the drawings by means of two examples of execution.

Fig. 1 shows a schematic diagram of the first semiconductor memory device in accordance with the invention.

Fig. 2 shows a schematic diagram of the second semiconductor memory device in accordance with the invention.

In Fig.1 is a schematic diagram of the first semiconductor memory device in accordance with the invention, which is performed on a single semiconductor substrate. In Fig.1 shows only a subregion of the semiconductor memory device, which has four memory cells Z1, Z2, Z3 and Z4. Memory cells Z1, Z2, Z3 and Z4 can be controlled in two horizontal tire AG1, AG2 and two vertical buses SP1, SP2.

To control the memory cells Z1, Z2, Z3, and Z4 is the control scheme, which has a transition transistor TT, the discharge transistor AT, transitional transistor TT and the discharging transistor AT, which are controlled via the signal bus write SchrX. On the signal bus write SchrX served the modified high voltage signal, which is generated from the logs is prepared as transistors with channel type p according to the technology field-effect transistors, while the discharge transistor AT and the discharge transistor AT implemented as transistors with channel type n technology field-effect transistors.

The memory cell Z1 has a selective transistor AT and the storage transistor ST1. Selective transistor AT made as a normal transistor with a channel type n technology field-effect transistors, while the memory transistor ST1 is designed as a transistor with a channel of type n with the so-called "floating gate". The first selective channel output electoral transistor AT connects with a vertical bus SP1, while the second selective channel output electoral transistor T connected to the first storage channel output memory transistor ST1. The second storage channel output memory transistor ST1 connected to the common bus, the origins of the SOURCE.

The output election gate electoral transistor T connected to horizontal bus AG1. Also the second transition channel output transition of the transistor T connected to the horizontal bus AG1. The first transition channel output transition of the transistor T connected to the output of the memory gate KG1 storage transistor ST1. Prinadlejy "floating gate".

Conclusion the transition of the shutter of the transition of the transistor T connected to the signal bus write SchrX. Conclusion the discharge gate of the discharge transistor AT is also connected to the signal bus write SchrX. The first discharge channel output discharge transistor IT connected to the memory output shutter KG1, while the second discharge channel output discharge transistor AT directly wound on a lot.

The memory cell Z3 relative to the horizontal bus AG1 is connected in parallel to the memory cell Z1. The memory cell Z3 has the same polling transistor AT, which is made by the conventional methods of field-effect transistors as the transistor with a channel of type n, and the storage transistor ST3, which is designed as a transistor with a channel of type p with a "floating gate". The first selective channel output electoral transistor ATZ is connected to the vertical bus SP2, while the second selective channel output electoral transistor ATZ connected to the first storage channel output memory transistor ST3. The second channel output storage device storage transistor ST3 is connected to common bus, the origins of the SOURCE. The output spiralingorbits AT and connected to the horizontal bus AG1.

Conclusion storage gate storage transistor ST3 is connected in parallel to the output storage gate storage transistor ST1 and connects with the second transitional channel output transition of the transistor TT. As a consequence, the output of the memory gate storage transistor ST3 is also connected with the first discharge channel output discharge transistor AT.

The memory cell Z2 is the selective transistor AT and the storage transistor ST2. Selective transistor AT made as a normal transistor with a channel type n technology field-effect transistors, while the memory transistor ST2 is designed as a transistor with a channel of type n with the so-called "floating gate". The first selective channel output electoral transistor AT connects with a vertical bus SP2, while the second selective channel output electoral transistor T connected to the first storage channel output memory transistor ST2. The second storage channel output memory transistor ST2 is connected to common bus, the origins of the SOURCE.

The output election gate electoral transistor T connected to horizontal bus AG2. Also vodnoy channel output transition of the transistor T connected to the output of the memory gate KG2 storage transistor ST2. Belonging to the output storage shutter KG2 gate storage transistor ST2 is made as a so-called "floating gate".

Conclusion the transition of the shutter of the transition of the transistor T and the output of the discharge gate of the discharge transistor AT connected to the signal bus write SchrX. The first discharge channel output is connected to the output of the memory gate KG2, while the second discharge channel output directly wound on the mass. The memory cell Z4 relative to the horizontal bus AG2 is in parallel with the memory cell Z2. The memory cell Z4 has, moreover, the selective transistor AT4, which is made by the conventional methods of field-effect transistors as the transistor with a channel of type n, and the storage transistor ST4, which is designed as a transistor with a channel of the n type floating gate". The first selective channel output electoral transistor AT4 is connected to the vertical bus SP2, while the second selective channel output electoral transistor AT4 connected to the first storage channel output memory transistor ST4. The second storage channel output memory transistor ST4 is connected with the common bus, the origins of the SOURCE. In the RA electoral transistor AT and connected to the horizontal bus AG2. Conclusion storage gate storage transistor ST4 connected in parallel to the output storage gate storage transistor ST2 and connects with the second transitional channel output transition of the transistor TT. As a consequence, the output of the memory gate storage transistor ST4 is also connected with the first discharge channel output discharge transistor AT.

Relative to the vertical bus SP1 memory cells Z1, Z2 are connected in parallel, while the memory cell Z3, Z4 relative to the vertical bus SP2 connected in parallel.

Below explains the three States: "erase", "write" and "read" to the memory cell Z1. In the "erase" signal is not transmitted on the vertical bus SP1, as it this is not necessary. Only when writing and when reading the content of the memory cell Z1 vertical bus SP1 loaded signal. It is not presented in more detail because it is associated with the essence of the invention.

Table 1 presents the status of the horizontal busbar AG1, AG2, conclusions of storage gates KG1, KG2 and signal bus write SchrX for individual functional modes.

The voltage "Up" refers to the programming voltage (for example the e value of the threshold voltage of the transistor with a channel of the type p (about 1 In).

As clearly seen from the table, when erasing a line storage device in which the memory cell Z1, on the horizontal bus AG1 voltage programming Up. Due to this, the first intermediate channel output transition of the transistor T is also when the voltage level of programming Up. To the signal bus write SchrX applied voltage of 0 V, so that the transition transistor T is in a conducting state, as it is designed as a transistor with a channel of type R. In contrast, the discharge transistor AT designed as a transistor with channel n, so coming to the conclusion of the discharge gate of the discharge transistor AT signal 0 signal bus write SchrX puts it in a locked state. As a result, the output of the memory gate KG1 receives the programming voltage Up, what causes floating gate storage transistor ST1 to go to the "erased" state.

The memory cell Z2 remains independent from processes on the horizontal bus AG1, as well as on the signal bus write SchrX, when the output of the memory gate KG2 is constantly in accordance with the potential of the horizontal bus AG2 in a certain state at 0 In+Utp.

is neither behave according to these memory cells Z1 and Z2. Here in the "erase" erases all the memory cells that are sampled horizontal bus AG1.

Erasing memory cells Z2 and memory cell Z4 is respectively erasing memory cells Z1 and Z3.

When you write a value to a memory cell Z1 horizontal bus AG1 and signal bus write SchrX loaded value Up. On the basis of a status signal bus write SchrX discharge transistor AT channel type n holds, while the transition transistor TT channel type p locked. Due to this, the output storage shutter KG1 is potential mass, namely 0 C. by supplying an appropriate signal to the vertical bus SP1 is written to the memory transistor ST1, because the selective transistor AT based appended to the output election gate signal Up is in a conducting state.

It should be noted that the memory cell Z2 remains independent of the processes in the memory cell Z1, since the output of the memory gate KG2 constantly in accordance with the potential connected through the discharge transistor AT mass retains a certain value of 0 Century.

When reading values from the memory cells Z1 to horizontal bus AG1 is value UI, while Delano when potential UI while the selective transistor AT is in a conducting state. By supplying the proper voltage on the vertical bus SP1 then you may read the state of the memory transistor ST1.

By supplying the proper voltage on the vertical bus SP2 in this functional mode may read the stored state of the memory transistor ST3 memory cell Z3 as a selective transistor ATZ is also in a conducting state. Memory cells Z2 and Z4 are independent from the state of the memory cells Z1 and Z3, when the output of the memory gate KG2 is always in a certain state at 0 In+Utp, as the output from the memory gate KG2 constantly in accordance with the potential connected through the discharge transistor mass retains a certain value of 0 In+Dtp.

Vertical bus SP1 and SP2, both when writing and when reading, are bridged their default values.

In Fig.2 is a schematic diagram of another semiconductor memory device in accordance with the invention, which is performed on a single semiconductor substrate. In Fig.2 presents only a subregion of the semiconductor memory device, which we AG1, AG2 and two vertical buses SP1, SP2.

To control the memory cells Z11, Z12, Z13 and Z14 is the control scheme, which has a transition transistor TT, the discharge transistor ET11, transitional transistor TT and the discharging transistor AT, which are controlled via the signal bus write SchrX. On the signal bus write SchrX receives the modified high voltage signal, which is generated from the logical signal that controls the recording process. The control circuit includes a further transistor unit selection VT, and the selection transistor block WT. The output of the gate selection block selection transistor block VT and the output gate unit selection transistor selecting unit WT connected to the signal bus selection block BLKN. On the signal bus selection block BLKN receives the modified high voltage signal, which is generated from another logic signal, the control unit programming.

Insert the transfer transistors TT and TT and transistors selection unit WT and WT manufactured as conventional transistors with channel type p according to the technology field-effect transistors.

The memory cell Z11 has a selective transistor AT and the storage transistor ST11. Election Tr as a mass storage transistor ST11 is designed as a transistor with a channel of type n with the so-called "floating gate". The first selective channel output electoral transistor AT connects with a vertical bus SP1, while the second selective channel output electoral transistor AT11 connected to the first storage channel output memory transistor ST11. The second storage channel output memory transistor ST11 is connected with the common bus, the origins of the SOURCE.

The output election gate electoral transistor AT11 connected to horizontal bus AG1. A second channel output selection block selection transistor block VT connected to the horizontal bus AG1. The second transition channel output transition of the transistor T connected to the first channel output selection block selection transistor block VT and the first intermediate channel output of the first transition of the transistor T connected to the output of the memory gate KG11 storage transistor ST11. Belonging to the output storage shutter KG11 gate storage transistor ST11 is made as a so-called "floating gate". Conclusion the transition of the shutter of the transition of the transistor T connected to the signal bus write SchrX.

Conclusion the discharge gate of the discharge transistor AT connected with signals is me as a second discharge channel output directly wound on a lot.

The memory cell Z13 relative to the horizontal bus AG1 is in parallel with the memory cell Z11. The memory cell Z13 is besides the selective transistor AT, which is made by the conventional methods of field-effect transistors as the transistor with a channel of type n, and the storage transistor ST13, which is designed as a transistor with a channel of the n type floating gate". The first selective channel output electoral transistor AT connects with a vertical bus SP2, while the second selective channel output electoral transistor T connected to the first storage channel output memory transistor ST13. The second storage channel output memory transistor ST13 connected to the common bus, the origins of the SOURCE. The output election gate electoral transistor AT 13 connected in parallel to the output election gate electoral transistor AT and connected to the horizontal bus AG1. Conclusion storage gate storage transistor ST13 connected in parallel to the output storage gate storage transistor ST11 and connects with the second transitional channel output transition of the transistor TT. As a consequence, the output storage shutter remember the Sabbath.

The memory cell Z12 has a selective transistor AT and the storage transistor ST12. Selective transistor AT made as a normal transistor with a channel type n technology field-effect transistors, while the memory transistor ST12 is executed as a transistor with a channel of type n with the so-called "floating gate". The first selective channel output electoral transistor AT connects with a vertical bus SP2, while the second selective channel output electoral transistor T connected to the first storage channel output memory transistor ST12. The second storage channel output memory transistor ST12 connected to the common bus, the origins of the SOURCE.

The output election gate electoral transistor T connected to horizontal bus AG12. A second channel output selection block selection transistor block VT connected to the horizontal bus AG2. The second transition channel output transition of the transistor T connected to the first channel output selection block selection transistor block VT and the first intermediate channel output transition of the transistor T connected to the output of the memory gate KG12 storage transistor ST12. The principle is called "floating gate".

Conclusion the transition of the shutter of the transition of the transistor T connected to the signal bus write SchrX. The output of the gate selection block selection transistor block VT connected to the signal bus selection block BLKN.

Conclusion the discharge gate of the discharge transistor AT connected to the signal bus write SchrX. The first discharge channel output is connected to the output of the memory gate KG12, while the second discharge channel output directly wound on a lot.

The memory cell Z14 relative to the horizontal bus AG2 is in parallel with the memory cell Z12. The memory cell Z14 is besides the selective transistor AT, which is made according to the technology field-effect transistors as the transistor with a channel of type n, and the storage transistor ST14, which is designed as a transistor with a channel of the n type floating gate". The first selective channel output electoral transistor AT connects with a vertical bus SP2, while the second selective channel output electoral transistor T connected to the first storage channel output memory transistor ST14. The second storage channel output memory transistor ST14 connected to the common bus, the origins SOURC the creators of the electoral transistor AT and connected to the horizontal bus AG2. Conclusion storage gate storage transistor ST14 connected in parallel to the output storage gate storage transistor ST12 and connects with the second transitional channel output transition of the transistor TT. As a consequence, the output of the memory gate storage transistor ST14 also connected with the first discharge channel output discharge transistor AT.

Relative to the vertical bus SP1 memory cell Z11, Z12 is connected in parallel, while the memory cell Z13, Z14 connected in parallel relative to the vertical bus SP2.

Here are three States "erase", "write" and "read" to the memory cell Z11. In the "erase" signal is not transmitted on the vertical bus SP1, as it this is not necessary. Only when writing and when reading the content of the memory cell Z11 vertical bus SP1 loaded signal. It is still not represented here in detail, since it does not matter affecting the essence of the invention.

Table 2 presents the status of the horizontal busbar AG1, AG2, conclusions of storage gates KG11, KG12 and signal bus write SchrX for individual functional modes.

The signal selection block BLKN in accordance with vermaat voltage 0 V ("selected") or Up ("not selected").

The voltage "Up" refers to the programming voltage (for example, 18 V), the voltage "UI" refers to the voltage read voltage "Upt" denotes the positive absolute value of the threshold voltage of the transistor with a channel of the type p (about 1 In).

For the following description of the operation principle of the semiconductor memory device is assumed that the signal BLKN is constantly at 0 V, so that the channels of the transistors of the selection blocks are in a conducting state and the signals on the horizontal tyres transmitted on the channels of transient transistors TT and TT.

As clearly seen from the table, when erasing a line storage device in which the memory cell Z11, on the horizontal bus AG1 voltage programming Up. Due to this, the first intermediate channel output transition of the transistor T is also on the voltage level of programming Up. On the signal bus write SchrX voltage is 0 V, so that the transition transistor T is in a conducting state, as it is designed as a transistor with a channel of type R. In contrast, the discharge transistor AT designed as a transistor with channel n, so coming to the conclusion RA is th state. As a result, the output of the memory gate KG1 receives the programming voltage Up, what causes floating gate storage transistor ST11 go to the "erased" state.

The memory cell Z12 remains independent from processes on the horizontal bus AG1, as well as on the signal bus write SchrX, when the output of the storage gate 12 KG continuously in accordance with the potential of the horizontal bus AG2 is in a certain state at 0 In+Utp.

Since the memory cell Z13 and Z14 relative to the horizontal busbar AG1, AG2 connected in parallel to the memory cells Z11 and Z12, they behave according to these memory cells Z11 and Z12. Hence, when the "erase" erases all the memory cells that are sampled horizontal bus AG1.

Erasing the memory cell Z12 and memory Z14 is respectively erasing memory cells Z11 and Z13. When you write a value to a memory cell Z11 horizontal bus AG1 and signal bus write SchrX loaded value Up. On the basis of a status signal bus write SchrX discharge transistor AT channel type n holds, while the transition transistor TT channel type p locked. Due to this, the output storage shutter KG11 is potential mass and imaac selective transistor AT based appended to the output election gate signal Up is in a conducting state. It should be noted that the memory cell Z12 remains independent of the processes in the memory cell Z11, as the output from the storage gate 12 KG continuously in accordance with the potential connected through the discharge transistor AT mass retains a certain value of 0 C. When reading values from the memory cell Z11 on the horizontal bus AG1 is value UI, while the signal bus write SchrX loaded with signal 0. Due to this, the output of the memory gate KG11 is definitely when the potential of the UI, while the selective transistor AT is in a conducting state. By supplying the proper voltage on the vertical bus SP1 in this case, you may read the state of the memory transistor ST11. By supplying a suitable voltage to the vertical bus SP2 in this functional mode may read the stored state of the memory transistor ST13 memory cell Z13, as a selective transistor AT also is in a conducting state. Memory cell Z12 and Z14 remain independent from the state of the memory cells Z11 and Z13, when the output of the memory gate KG12 is always in a certain state at 0 In + Dtp, namely on the basis connected through rashimi standard values.

Claims

1. Semiconductor storage device with at least one memory cell containing a selective transistor with a channel type n (AT1, AT2; AT11, AT12), with the output election gate, and two selective channel output, and the output election gate connected to leading to the memory cell (Z1, Z2; Z11, Z12) horizontal bus (AG1), a storage transistor with a channel of n-type (ST1, ST2; ST11, ST12), with the output memory button (KG1, KG2; KG11, KG12), as well as two memory channel output, and the first storage channel output memory transistor ST1 connected to the second selective channel output electoral transistor AT1, the first selective channel output electoral transistor AT1 is connected to the vertical bus (SP1), the second storage channel output memory transistor ST1 connected to the common bus, the origins of the SOURCE, and the semiconductor storage device has at least one transition transistor (TT, TT; TT, TT) with the first and second transition duct conclusions, the first transition channel output transition of the transistor is connected with the output of the storage gate (KG1, KG2; KG11, KG12) storage transitt), and the second transition channel output connected to leading to the memory cell (Z1, Z2; Z11, Z12) horizontal bus (AG1, AG2; AG11, AG12).

2. The semiconductor device according to p. 1, characterized in that it includes a control bus (SchrX), connected to the output transition of the shutter with the ability to control the transition transistor (TT, TT; TT, TT) specified through the control bus.

3. The semiconductor device according to p. 2, characterized in that there is a discharge transistor with a channel type n (ET, ET; ET, ET), which is the output of the discharge gate, and first and second discharge channel conclusions, and the first discharge channel output is connected to the output memory button (KG1, KG2; KG11, KG12), the second discharge channel output is connected, in particular, by weight, and the output of the discharge gate is connected to the control bus (SchrX).

4. The semiconductor device according to one of paragraphs. 1-3, characterized in that it is oriented in rows and columns, and rows conclusions electoral paddles multiple memory cells (Z1, Z3; Z2, Z4; Z11, Z13; Z12, Z14) connected in parallel and conclusions of storage gates multiple memory cells (Z1, Z3; Z2, Z4; Z11, Z13; Z12, Z14) connected in parallel, and in the columns of the first zapomina the first storage device p. 4, characterized in that at least one column includes a control circuit having at least one transistor of choice block of memory cells with channel p(VT, VT)with the output of the gate selection unit memory cells, as well as two channel terminals of the choice of unit memory cells, and the first channel output selection block of memory cells connected to leading to the memory cell horizontal bus (AG1, AG2), and the second channel output selection block of memory cells connected to the first transitional channel output.

6. Semiconductor storage device according to p. 5, characterized in that provided for the management bus selection block of memory cells (BLKN), which is connected with the conclusions of the shutter unit selection memory cells so that the selection transistors of the block of memory cells (WT, WT) can be controlled through the control bus selection block of memory cells (BLKN).

 

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