Shaper signals multi-frequency telegraphy

 

The invention relates to the field of radio communications and can be used for the transmission of multi-frequency signals of frequency telegraphy. The technical result is to implement the formation of the multi-frequency signal frequency telegraphy under arbitrary combinations of its components. The technical result is achieved in that the forming device signal frequency telegraphy contains accumulating adder phases, a persistent storage device (ROM) harmonic oscillations, digital to analog Converter (DAC), a lowpass filter (LPF), characterized in that additionally introduced timer, driver frequencies, the full adder phase switch, accumulating adder components, counter, ROM initial phases connected by N-bit bus decoder and multiplexer. 5 Il.

The invention relates to the field of radio communications and can be used for the transmission of multi-frequency signals of frequency telegraphy.

A device containing reference generator accumulating adder, a buffer register, a reversible counter, a binary adder, the unit's permanent memory, digital to analog Converter, a low pass filter (authors is a device for generating signals dual and four-photon telegraphy, containing serially connected reference generator and multi-tap frequency divider, connected in series encoder, driver code sequence, the second memory block, accumulating adder and the first block of memory sequentially connected to analog Converter and a low pass filter, while the clock input is accumulating adder and shaper code sequence is connected to the outputs of the multi-tap frequency divider and multiplexer, a control input which receives an external command, connected in series, the third memory block and the first multiplier, connected in series to the fourth memory block and the second multiplier, the adder, the inputs of which are connected to the outputs of the multipliers, the address counter, the fifth and sixth memory blocks whose inputs are connected to the output of the address counter, and outputs connected to the second inputs of multipliers, and the inputs of the third and fourth memory blocks connected to the output of the accumulating adder, the outputs of the adder and the first memory block is connected to the first and second inputs of the multiplexer, respectively, the output of the multiplexer is connected to the input of the digital to analogue Converter, and the beat is 6 H 04 L 27/12, publ. 10.09.99 year). However, the known device has limited capabilities when forming multi-frequency signals, relative to the number of its components and their combination.

The task to be solved by the invention, is to implement the formation of the multi-frequency signal frequency telegraphy under arbitrary combinations of its components.

The solution is achieved by the fact that in the known device a signal-frequency telegraphy containing successively United accumulating adder phases, a persistent storage device (ROM) harmonic oscillations, digital to analog Converter (DAC) and a low pass filter (LPF), the output of which is the first (main) output device, connected in series introduced the timer, the first input of which is the first (information) input device, and driver frequencies, the output of which is connected to the first input of accumulating adder phases, introduced the full adder phases, the first input connected to the output of the accumulating adder phases, and the output is connected to the input of ROM harmonic oscillations entered serially connected switch, the first input of which is the group of "0", and accumulating adder components, the output of which is connected to the input of the DAC and is the second (additional) output devices, and entered the counter and ROM the initial phases, the output of which is connected to the second input of the adder full phase, connected in series introduced on N-bit bus decoder and multiplexer, the output of which is connected with the third (Manager) the input switch and the first output of the counter, the first input of the ROM initial phases, the second inputs of the former (frequencies and accumulating adder phases and (N+1)-th (control) input multiplexer connected together, moreover, the second output of the counter, the second (clock) input of the timer and the second input (input initialization) accumulating adder components connected together, and the first counter input and the third (clock) inputs accumulating adder phase and accumulating adder components are combined to form the second (clock) input of the device, and the second output of the timer is connected to a second input (reset input) counter, and the fourth (control) input is accumulating adder components, the second input of the ROM initial phases and the input of the decoder are combined to form the third (control) input device, and N the introduction of significant distinguishing features is the novelty and allows as will be shown below, to solve the problem.

In Fig.1 shows a structural diagram of the device.

The device has connected in series timer 1, shaper frequencies 2, accumulating adder phase 3, the adder full phase 4, the ROM harmonic oscillations 5, switch 6, to the second input of which receives the digital signal value "0", accumulating adder components 7, the DAC 8, low-pass filter 9, and includes a counter 10, a ROM initial phase 11, the output of which is connected to the second input of the full adder of 4 phases, and connected in series by N-bit bus, the decoder 12 and the multiplexer 13, the output of which is connected with the third (Manager) the input of the switch 6, the first input of the timer 1 is the first (information) input device, the output of the LPF 9 is the first (main) output, and the output of the accumulating adder components 7 is the second (optional) output, the first output of the counter 10, the first input of the ROM initial phase 11, the second inputs of the former (frequencies 2 and accumulating adder phases 3 and (N+1)-th (control) input of the multiplexer 13 is interconnected, while the second output of the counter 10, the second (s) whoppi first input of the counter 10 and the third (clock) inputs accumulating adder phases 3 and accumulating adder components 7 are combined to form the second (clock) input of the device, and the second input (reset input) of the counter 10 is connected to a second output of timer 1, while the fourth (control) input is accumulating adder components 7, the second input of the ROM initial phases 11 and the input of the decoder 12 are combined to form the third (control) input device, and N is the number of components of the multifrequency signal.

Denote the number of components of the multi-frequency signal as N. All components, each of which represents a single-frequency signal of frequency telegraphy, manipulated the same Telegraph signal, which may be in one of the States, "parcel" or "pause". For each i-th component of the multi-frequency signal of the i-th component of the multi-frequency signal, where i[0,N -1], depending on the sign of the original Telegraph signal current frequency component has extreme valuesoicorresponding to "pause", and F1icorresponding to "sending".

To reduce levels of out-of-band radiation, after changing the sign of the Telegraph signal current frequency of each component of the multi-frequency signal passes do not jump from one extreme value to another, and for some intervalchanges and intervalits value becomes equal to F0ior F1idepending on the sign of the current cable package. Durationselected shorter than the duration t of the basic cable package. The specific value ofintermediate frequencies and their number are chosen in such a way that meets the requirements to the level of out-of-band radiation for the components of the multifrequency signal.

In General, the current frequency for any i-th component of the multi-frequency signal can be represented as the sum of Fi=FC+F, (1) wherethe Central frequency of the i-th component of the multi-frequency signal;F is the deviation of the current frequency Fifrom the Central frequency FCat the current time.

As relative value,F does not depend on the number of the i component of the multi-frequency signal, and for any i-th component can take, in addition to the extreme values of F0i- FCcorresponding to "pause", and F1i- FCcorresponding to the "sending", certain intermediate values during the time. The Fli-FCdenote N. In order to reduce the crest factor of a multi-band signal for each of the i-th component is set to a certain initial phase of the fi. Then for multi-band signal s(t) we can write the following expression:where Aithe amplitude of the i-th component of the multi-frequency signal.

In General, in multi-frequency signal some components of the number N may be absent, i.e., their amplitudes are set to 0, unlike other components, the amplitude of which is equal to 1. This changes the composition of the spectrum of the resulting signal. Therefore, to minimize the crest factor for each combination of the amplitudes Aithe components of the multifrequency signal must meet certain combination of initial phases fi.

Denote the number of possible combinations that can be used when forming the multi-frequency signal as the Nto. Hence, for each i-th component of the multi-frequency signal included in the k-th combination of components, where i[0,N-1] and k[0,Nto-1] must be defined amplitude Andikand the initial value is the operation of the device as a whole, let's make some clarifications regarding the implementation and functioning of the individual blocks.

The counter 10 it pulses received at its first input with a frequency Ft, and has a conversion factor of N, where N is the number of components of the multifrequency signal. The second input (reset input) of the counter 10 is used to set to 0. The first output of the counter 10 is formed of the i-th component of the multi-frequency signal, in the absence of a reset signal on the second input, cyclically varying from 0 to N-1. On the second output pulse is formed when the counter 10 is set to 0 by the signal on the second input, or when the counter 10 changes the state with N-1 to 0. The pulse frequency (sampling rate) on the second output of the counter 10
At the first input of timer 1 goes Telegraph signal and the second input is used as a clock. With the change of sign of the input telegraphic signal timer 1 generates a pulse at the second output and runs in the intervalconsistently with frequency Fdsetting the first output digital code, the value of which lies in the interval [0,N-1]. This digital code is with the src="https://img.russianpatents.com/chr/916.gif" align="TOP">-1]. At the end of the intervaland until the next front Telegraph signal j has a constant value of 0 or N-1, depending on the sign of the current parcel.

For example, if the Telegraph signal "pause" corresponds to the value j=0, Telegraph signal "parcel" - value j =-1, then change the sign of the Telegraph parcels of "pause" to "package" the value of j in the intervalwith frequency Fdtakes successive values 1, ...,N2 and, after the intervalset in N-1, maintaining this value until the next front Telegraph signal. Similarly, when the change of sign of the Telegraph parcel "parcel" to "pause" the value of j in the intervalwith frequency Fdtakes successive values of N-2,...,1 and, after the intervalset to 0 to keep this value until the next front Telegraph signal. Fig.2 illustrates the described conditions and Ntiming functions of the form cos x or sin x. We denote this number of samples as Nr. In accordance with the address of the first entrance ROM harmonic oscillations 5 at its output appears in the content addressable cells, representing the values of the harmonic function, analogous to the phase which is the input address. If the ROM harmonic oscillations 5 contains timing functions of the form cos x will be a fair ratio (2) and (3). If this is a function of the form sin x, the relation (2) and (3) must be adjusted:


Shaper frequencies 2 is received at the first input and the i-th component of the multi-frequency signal fed to the second input, generates an integer Miis directly proportional to the current value of frequency Fi.


In accordance with (1) the value of Mican be represented as the sum of:

where


On this basis, the shaper frequencies 1 can be implemented as a set of ROM offset values, 14, ROM the Central values of 15 who/916.gif" align="TOP">
cells and contains the values of M. In accordance with the state at the first input of the shaper frequencies from 1 ROM Delta values 14 retrieves the content addressable cells and is supplied to the first input of the adder values 16.

ROM the Central values 15 has a volume of N cells and contains the values of MC. In accordance with the i-th component at the second input of the shaper frequencies 1, the ROM is Central values 15 retrieves the contents of the i-th cell and supplied to the second input of the adder values 16.

The adder values 16 adds the input values, resulting in the output of the shaper frequencies 1 receives a value of Miwhich, as already mentioned, corresponds to the value of the current frequency for the i-th component of the multi-frequency signal in the current time.

Accumulating adder phase 3 produces a continuous accumulation of values received on its first input. The accumulation is performed individually for each of the i-th component of the multi-frequency signal in accordance with the number i received at a second input of the accumulating adder phase 3, and with a frequency Ftthe pulses received on the third (clock) input. Cromakalim conditions at any time t for the i-th component of the multi-frequency signal is output accumulating adder phase 3 is the sum modulo Ngall values that are received at the first input from the initial moment to moment t. The initial moment of time, here and below, we assume the moment of switching on the device or changing the state on the third (control) input device.

Accumulating adder phase 3 can be implemented as a set of random access memory (RAM) of the current phase 17, the adder current phases 18 and register the current phases 19, as shown in Fig.4.

RAM current phase 17 has a volume of N cells. In the initial moment of time the contents of the RAM cells of the current phase 17 is set to zero. In each i-th cell contains the current sum modulo Ngvalues that are received at the first input of accumulating adder phase 3. RAM current phase 17 has the first (information) input, the second (address) input and output. In accordance with the number i received at a second input of the accumulating adder phase 3, the address input of RAM current phase 17 selects the i-th cell. The first (information) input current RAM phases 17 is used to record selected by the second input cell. The output of RAM current phase 17 is used to retrieve the contents of the selected cells.

The current adder phases 18 performs the addition modulo NgRAM current phase 17.

Register current phase 19 has the first (information) input and the second (clock) input. Register current phase 19 it is the pulses coming from the third (clock) input is accumulating adder phases 3 and having a frequency Ftsequence, and the first input writes the values coming from the output of the adder current phase 18. The output of register current phase 19 is the output of the accumulating adder phase 3.

In each clock cycle the contents of the selected RAM cell current phase 17 is folded modulo Ngwith the value received at the first input of accumulating adder phase 3, and the result of the addition is written to the register of current phases 19, the output of which is then placed in the same cell RAM current phase 17.

The full adder phase 4 performs the addition modulo Ngvalues received at its first and second inputs.

The switch 6 has a first input, a second input, which is constantly set to "0", and the third input, which is used to control. If the third input is set to logic 1, the output switch 6 receives is from his first entrance, and if set to logical 0, then enters the value "0" from the second course.

Nakaplivalos is operating at its first input with a frequency Ftand rationing their sum. The second input (input initialization) accumulating adder components 7 is used to set its output the next value of the sum of the elapsed period of accumulation and subsequent initialization of the internal content of the accumulating adder components 7. The third entrance is accumulating adder components 7 is used as a clock. The fourth input is accumulating adder components 7 is used to select the value of the normalizing factor. The value of the normalizing factor is defined as 1/Nawhere Na- the number of components of the multi-frequency signal, the amplitude Andikwhich is different from zero. In the General case, each number k combinations of components corresponds to a value of Nand[1,N].

Accumulating adder components 7 can be implemented as a set of current adder counts 20, register of current samples 21, a case full of samples 22, normalizing multiplier 23 and ROM normalizing coefficients 24, as shown in Fig.5.

The current adder counts 20 carries out the addition of the values received from the first entrance is accumulating adder components 7, and values, the ion) input, the second input (reset input) and third (clock) input. Register current times, 21 it is the pulses coming from the third (clock) input is accumulating adder components 7 and having a frequency Ftsequence, and writes the values coming from the output of the adder current times 20. The reset signal received from the second entrance is accumulating adder components 7, the contents of register current times, 21 is set to 0.

A case full of samples 22 has the first (information) input and the second (clock) input. A case full of samples 22 it is the pulses coming from the second entrance is accumulating adder components 7 and has a frequency ofdsequence, and writes the values coming from the output of register current times, 21.

ROM normalizing coefficients 24 contains Ntovalues that represent the normalizing coefficients for each k-th combination of the components of the multi-frequency signal, where k[0,Nto-1]. In accordance with the number of k-combinations of the components of the multi-frequency signal is set at the fourth input is accumulating adder components 7, the ROM normalizing coaffee multiplication values, received at its first input, and the values of the normalizing factor that is installed on the second input. The output of the normalizing multiplier 23 is the output of the accumulating adder components 7.

In each clock cycle having a duration frequency Ftthe current adder counts 20 adds the value received from the first input is accumulating adder components 7, and the value of the output register of the current samples 21, and the result of the addition is written to the register of current times, 21. For each pulse received from the second entrance is accumulating adder components 7 with frequency Fdfollowing, occurs the entry in the register is full of samples 22 and reset to 0 the contents of register current times, 21. Normalizing multiplier 23 calculates the product of the output register is full of samples 22 and exit ROM normalizing coefficients 24.

Thus, the output of the accumulating adder components 7 at any time t is a normalized sum of values received at the first input during the elapsed period of the frequency Fd.

DAC 8 converts the input digital value in its analog form.

Low-pass filter 9 performs the suppression of high-frequency sub>to, cells, and as the first index when the cell is selected, use the value received at the first input of the ROM initial phases 11, and as the second index value that is supplied to the second input. In each ik-th cell of the ROM initial phases 11, where i[0,N-1] and k[0, Nto-1] contains the value Toikrepresenting the digital analogue of the initial phase of the i-th component of the multi-frequency signal having the k-th combination of components:

The first input of the ROM initial phase 11 is used to set the number of the i component of the multi-frequency signal and a second input for setting the number k of combinations of constituents. At the output of ROM initial phase 11 is set to the contents of the ik-th cell.

The decoder 12 converts the input value into an N-bit number. The state of the i-th bit output is identical to the value of amplitude aikwhen used k-I the combination of the components of the multifrequency signal. The state of the logical 0 of the discharge indicates that the amplitude of the corresponding component is equal to 0, and the state of the logical 1 - to the fact that the amplitude component equal to 1. The state at the input of the decoder 12 is the number k combination. The output of the multiplexer 13 is set to the state of the logic inputs, whose number is the value at the control input of the multiplexer 13.

Consider the operation of the device.

Telegraph signal from the first input device is fed to the first input of timer 1 timed pulses with a frequency Fd. Depending on the sign of the Telegraph parcel timer 1 generates a first output corresponding number of allowed deviation from the Central frequency for any component of the multi-frequency signal.

With the change of sign of the Telegraph parcel on the second output of timer 1, a signal is generated which resets the counter 10 to 0. And the first output timer 1 number of permitted deviation is progressively change with frequency Fdso at the end of the intervalto accept the new value corresponding to the sign of the current Telegraph signal.

Clocked coming from the second input device pulses with a frequency Ftthe counter 10 at the first output generates number component of the multi-frequency signal and the second output pulses with a frequency Fdsequence.

The number from the first output of timer 1 is supplied to the first input of the influencers number component of the multi-frequency signal. In accordance with the state of the input shaper frequencies 2 sets the output value, which is the digital equivalent of the current rate of this component of the multi-frequency signal.

Value from the output of the shaper frequencies 2 is supplied to the first input of the accumulating adder phase 3, to a second input which sets the i-th component of the multi-frequency signal. Clocked pulses with a frequency ofd, accumulating adder phase 3 performs the accumulation of the values of Miarriving at his first entrance, individually for each of the i-th component of the multi-frequency signal. Thus, at the output of the accumulating adder phase 3 for each component is formed by a digital analogue of the current phase.

In accordance with the i-th component of the multi-frequency signal at the first input of the ROM initial phases 11 and state k at the control input of the device and the ROM initial phases 11 retrieves the digital analogue of the initial phase for the i-th component.

The full adder phases 4 and the output values of the accumulating adder phases 3 and ROM initial phases 11 forms for the i-th component of the multi-frequency address signal, which is used to extract the ROM is harmonic to the STV decoder 12 generates the N-bit code, determining values of the amplitudes of the k-th combination of the components of the multifrequency signal. Depending on the number of the i component of the multiplexer 13 sets on the exit level of the i-th digit code received by the first N inputs. Thus, at the output of the multiplexer 13 is set to a logic level 0 if this element is missing in the resulting multi-frequency signal, or a logic level 1 if the component is part of the multifrequency signal.

The output of the ROM harmonic oscillations 5 is supplied to the first input of the switch 6. The second input of the switch 6 is constantly set to "0".

Controlled by a logic signal from the output of the multiplexer 13, the switch 6 turns on the first input is accumulating adder components 7 value output from the ROM harmonic oscillations 5, if the component with the current number is included in the multi-frequency signal, or a value of 0, if the component should be missing. As a result, the first input is accumulating adder components 7 are samples only those components of the multi-frequency signal, the amplitude of which is different from 0.

Accumulating adder components 7 adds up the input samples within ltat addition is fed to the input of the DAC 8 and the second (additional) output device, which can be used for subsequent digital signal processing.

DAC 8 converts the input digital signal in analog form. With the DAC output 8 signal received at the input of low-pass filter 9, which allocates a useful part of the spectrum of the signal and in this form submits it to the first (main) output device.

Thus, the proposed device allows you to create multi-frequency signal frequency telegraphy, the number and combination of components which in the process can change. In addition, the proposed device can be implemented programmatically based on the signal processor.


Claims

The device forming the signal frequency telegraphy containing successively United accumulating adder phases, a persistent storage device (ROM) harmonic oscillations, digital to analog Converter (DAC), and a lowpass filter (LPF), the output of which is the first (main) output device, characterized in that the input connected in series timer, the first input of which is the first (information) input device, and driver frequencies, the output of which is connected to the output of the accumulating adder phases, and the output is connected to the input of ROM harmonic oscillations entered serially connected switch, the first input connected to the output of the ROM harmonic oscillations and to the second input of which is fed a digital signal value "0", and accumulating adder components, the output of which is connected to the input of the DAC and is the second (additional) output devices, and entered the counter and ROM the initial phases, the output of which is connected to the second input of the adder full phase, connected in series introduced on N-bit bus decoder and multiplexer, the output of which is connected with the third (Manager) input switch, the first output of the counter, the first input of the ROM initial phases, the second inputs of the former (frequencies and accumulating adder phases in the (N+1)-th (managing) the multiplexer input is interconnected with the second output of the counter, the second (clock) input of the timer, and the second input (input initialization) accumulating adder components connected together, and the first counter input and the third (clock) inputs accumulating adder phase and accumulating adder components are combined to form the second (clock) input of the device, and the second output timefor components, second input of the ROM initial phases and the input of the decoder are combined to form the third (control) input device, and N is the number of components of the multifrequency signal.

 

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