The device search signal delay with pseudorandom change the operating frequency

 

The device searches for the delay relates to electrical engineering and can be used in communication systems with pseudorandom change the operating frequency. Technical result achieved is a significant reduction in the search time of the signals in comparison with the prototype. The device consists of a multiplier (1), bandpass filter (2), the amplitude detector (5), block of comparison with a threshold (7), clock frequency (10), tunable frequency synthesizer (9), two switches (3, 8), limiter (4), drive (6), the input clock divider (11). 6 Il.

The invention relates to electrical engineering and can be used in communication systems with pseudorandom change the operating frequency.

The known device search signal delay with pseudorandom change the working frequency, are described in the monograph by R. K. Dixon "Broadband system." Moscow, Communication, 1979, pp. 191-192, Fig.6.9, and in the monograph by C. I. Borisov and other "noise Immunity of radio communication systems with expansion of the range of signals, the method of pseudo-random adjustment of the operating frequency, Moscow, "Radio communications", 2000., p. 229, Fig. 6.12, the lack of which is a great time of the search.

The closest technicality complex signals", Moscow, "Sov. radio", 1977, page 326, Fig.7.2 century.

The structural scheme of the device of the prototype is shown in Fig.1, showing: 1 - multiplier (mixer); 2 - band-pass filter; 3 - amplitude detector; 4 - block comparison with a threshold; 5 - clock pulse generator; 6 - block rejectee clock pulses; 7 - tunable frequency synthesizer (code generator); 8 - count; 9 - control unit;
10 - switch.

The device prototype has the following functional relationships: connected in series multiplier 1, the first signal input which is the input of the bandpass filter 2, the amplitude detector 3 and the power comparison threshold 4, the output of which is connected with the third managing the switch input 10; serially connected clock pulse generator 5, a block rejectee clock 6, the switch 10 and the tunable frequency synthesizer (code generator) 7, the output of which is connected to a second reference input of the multiplier 1; in addition, the generator output clock frequency 5 is connected to a second signal input of the switch 10 and connected in series with the counter 8 and the control unit 9, the output of which is connected to a second input of block rejectee clock pulses 6.

The device is a prototype of the servant of the surveillance capacity of the counter 8, it generates a command which is supplied to the unit 9. This command block 9 together with the block 6 or rejective (Blanquet) a specified number of clock pulses generated by the block 5 and acting on the block 7 through the block 10. This ensures the change of the delay reference signal generated by the block 7, with respect to the input signal.

The result of the multiplication of the input and reference signals from the output of the block 1 is supplied to the unit 2, where it is filtered. Accumulated in unit 2, the voltage is detected in block 3, the selected envelope is compared with a threshold in block 4. In case of exceeding the threshold unit 4 sends the command "1" to the block 10, according to this command to the output unit 10 (unit 7) is connected to the output unit 5, and the output unit 6 is disconnected from the first input unit 10. In this case, the unit 7 receives the clock pulses directly from block 5, the search mode the delay ends and, starting from this moment, the reference signal is in synchronism with the input signal.

The disadvantage of the prototype is a great time searching for the delay.

To eliminate this drawback in the device search signal delay with pseudorandom change the operating frequency in a device that contains one United paramn the detector, the power comparison threshold, the clock frequency and tunable frequency synthesizer, the output of which is connected to the second reference input of the multiplier entered serially connected first switch, the first signal input connected to the output of the bandpass filter, and a limiter, the output of which is connected to the input of the amplitude detector. Put the drive and connected in series divider clock frequency and the second switch, the first signal input connected to the generator output clock frequency and the input clock frequency divider. Thus the output of the amplitude detector via the drive is connected to the input of the comparison with the threshold, the output of which is connected to the second control inputs of the first and second switches. In addition, the output of the second switch is connected to the input of the tunable frequency synthesizer, and the second signal output of the first switch is an output device.

The structural scheme of the device is shown in Fig.2, where indicated:
1 is a multiplier (mixer);
2 - band-pass filter;
3 is a first switch;
4 - limiter;
5 - amplitude detector;
6 - drive;
7 is a block comparison with a threshold;

The proposed device has the following functional relationships: connected in series multiplier 1, the first signal input which is the input of the bandpass filter 2, the first switch 3, the stopper 4, the amplitude detector 5, a memory 6, a block comparison with the threshold is 7, the output of which is connected to the second control inputs of the first switch 3 and the second switch 8, the first signal input connected to the generator output clock frequency 10 and to the input of the clock frequency divider 11, the output of which is connected to the third signal input of the second switch 8, the output of which through the tunable frequency synthesizer 9 is connected to a second reference input of the multiplier 1; in addition, the second signal output of the first switch 3 is the output device.

The device shown in Fig.2, operates as follows.

On the signal input unit I, which is the input of the signal from the software operating frequency tuning, representing a periodic sequence of N radio pulses duration0, frequency fields which are changed in accordance with a given program realignment (code). In which the action scene from the input signal by the shift of all frequencies restructuring program on the value of fCRequal to the intermediate frequency of the receiver.

In the original operation mode when the device is not included in synchronism with the input signal, the output unit 7 is formed by the command "0". On this team, coming on the second control inputs of the blocks 3 and 8, the output unit 2 through the block 3 is connected with the input unit 4 and to the input of block 9 through the block 8 is connected to the output unit 11, resulting in unit 9 serves clock pulses from unit 11 whose frequency fT1in the (N+1) times lower than the clock frequency ft0generated by the block 10, which is achieved by dividing the clock frequency of the block 10 in the (N+1) times in the block 11.

Due to the feed block 9 clock frequencyft0=ftwhere ftis the clock used to generate the input signal, the device search mode the delay at which the block 9 is on each of the N frequencies of the restructuring program during the time1= (N+1)0. During1the input signal is time to adjust for all N frequencies of the program of perestroika, the output unit 1 to the result of multiplying the input and reference signals at each of the N times what elnett0occupying the same temporary positionsince the change of frequency. i(1=2...i...N) is determined by the mutual delay (phase) of the input and reference signals.

The time interval between pulses of the signal emitted at the output of block 1 adjacent frequencies equal to1= (N+1)0and the temporal position of the pulse signal in the interval1relative change (jump) frequency carries information about the initial phase (delay) of the input signal relative to the reference.

Said illustrated in Fig.3, where Fig.3A presents the input signal with pseudorandom change the operating frequency, while the numbers indicate the sequence number of frequencies in the program of reconstruction of the input signal. With the purpose of clarity in Fig.3 taken N=5.

In Fig. 3G shows the adjustment program reference signal with a duration of standing on each of the N frequencies equal to1= (N+1)0when Atomoxetine pulses matches the input and reference signals, in Fig. 3D, e shows that the temporal position of the pulse matches the input and reference signals at each frequency position specifies the delay (phase) of the input signal relative to the reference. It is evident from Fig.3D also shows that the duration of the reference signal at each of the N frequency positions equal to1there is an opportunity of entering into synchronism with the input signal, that is, determine its initial phase the results of the accumulation of M pulses matches the input and reference signals M<<N. This feature is determined by the fact that each selected pulse signal at each of the N time intervalscarries information about the phase of the input signal.

This property provides the possibility of reducing the search time signals with software frequency due to the accumulation not all N pulses restructuring program, but only part of their M<1= (N+1)0,F on block 4, where is the regulation voltage level due to the restrictions. C unit output 4 voltage is applied to the block 5, where due to amplitude detection are highlighted envelopes of the pulse signal, which accumulate in the block 6. The accumulated voltage is compared with a threshold in block 7. The command "I" indicating that the threshold is exceeded, is fed to the second control inputs of the blocks 3 and 8.

When receiving this command, the block 8 disconnects from the input unit 9, the output of block 11 and connects to it the output of block 10. Since then, the unit 9 is transferred from work with a clock frequency ft/(N+1) to work with a clock frequency ftequal to and synchronous with a clock frequency used to generate the input signal. Said illustrated in Fig.3E. At the same time the unit 3 turns off the output of block 2 from the input unit 4 and connects it to the output device. The search procedure is complete and the receiving device, which includes the inventive device, enters the tracking mode for delay and receiving information.

Structural block circuit 3 shown in Fig.4, where indicated:
31, 32, the first and second keys;
33 - inverter.

Block 3 contains the first key 31 and the second key 32, first United signalname outputs of block 3, respectively. The second control input unit 3 is connected with the control input key 32 directly, and with a control input key 31 through the inverter 33.

Unit 3 operates as follows. When there is a command "0" to the second control input unit 3 key 32 is closed, and the switch 31 is open, as at its control input the command "I", formed from the team of "0" due to its inversion in block 33. In this case, the first signal input unit 3 is connected with its first signal output. When there is a command "I" on the second control input unit 3, the first signal input through the public key 32 is connected with the second signal output unit 3, the key 31 in this mode locked.

Structural block circuit 8 shown in Fig.5, where indicated:
81, 82, the first and second keys;
83 - inverter.

Unit 8 contains the first key 81, the second key 82, and an inverter 83, the first signal input unit 8 is connected to the signal input of the key 81, and the third signal input unit 8 is connected to the signal input of the key 82, the output of which is combined with the output of the block 81 is a signal output unit 8, the second control input connected with the control input of the key 82 directly, and with the control input of the key 81 through the inverter 83.

Nl, the key 82 is closed, while the signal output unit 8 is connected to its first signal input. When the second control, the input unit 8 commands "I" key 81 is locked, and the key 82 is unlocked, while the signal output unit 8 is connected to its third input.

The block 11 is a divisor clock frequency generated by the unit 10, and can be made in the form of a counter as outlined in the monograph "Digital radio systems", Handbook Ed. by M. I. of Adissage, Moscow, Radio and communications, 1990., page 46, Fig.2.8.

Unit 9 may be performed as shown in Fig.6, where indicated:
91 - grid generator frequencies;
92 digital switch;
93 - the pseudo-random sequence generator.

Block 9 contains connected in series grid generator frequency 91 and digital switch 92, and the pseudo-random sequence generator 93, the inlet of which is combined with the input unit 91 and an input unit 9, and the output unit 93 is connected with the control input of the block 92, the output of which is the output of the block 9.

The clock pulses received at the input unit 9, determine the frequency of the clock generator numeric sequence 93, which may be made on the basis of the shift register and the flip-flops of the shift register. For the shift register produces a sequence of maximal length, there are N States, N=2n-1, where n is the number determined by the bit width of the register, which gives a number from 1 to N. Unit 91 generates the grid harmonic signals.

All signals of the grid frequency from the outputs of the block 91 are received at the signal input unit 92, the control input of which is fed a digital code output unit 93. Unit 92 corresponds to each of N pseudo-random numbers generated by the block 93, a signal grid of frequencies, and only this signal passes to the output unit 9 within a single clock cycle. When you receive another tact at the output of block 9, you receive another signal grid of frequencies, etc.

The duration of the transmission to the output unit 9 of each of the signal grid of frequencies defines the length of the standing of each frequency at the output of block 9.

When using the prototype in the search mode, the delay is provided by the sliding of the reference signal relative to the input and their periodic coincidence.

Search time delay (T), defined as the time required for the convergence time of the input and reference signals, for a device of the prototype depends on the delay between the input and the s when using device-prototype (TCR) is: TCR= N(N+1)0; when N=5 TCR= 5(5+1)0= 300.

For device-prototype on the time interval T = N(N+1)0the coincidence of input and reference signals is observed only in the interval N0. Therefore, the tendency to reduce the search time by reducing the number of accumulated pulses of the signal M<N for device-prototype inefficient. Indeed, for a device prototype, as seen in Fig.3b, for the maximum value of the time search have: TCR= N(N+1)0-(N-M), when N=5, M=3 have TCR= 3(5+1)0-20= 280(1).

In the inventive device for any value of the delay between the input and reference signals is provided by the selection pulse signal duration0on each of the N time intervals, duration1= (N+1)0corresponding to N frequency reference signal.

When the number of accumulated pulses of the signal rd is determined by the ratio: TCM(N+1)0when N=5, M=3, TC= 3(5+1)0= 180(2)
From the comparison of (1) and (2) see T3TCR.

Thus, the proposed device provides a substantial reduction in search time delay for signals with pseudorandom change the operating frequency in comparison with the prototype.


Claims

The device search signal delay with pseudorandom change the operating frequency, containing connected in series multiplier, the first signal input which is the input device, and a band-pass filter and amplitude detector, the unit of comparison with a threshold, the clock frequency and tunable frequency synthesizer, the output of which is connected to the second reference input of the multiplier, wherein the introduced sequentially connected to the first switch, the first signal input connected to the output of the bandpass filter, and a limiter, the output of which is connected to the input of the amplitude detector, put the drive and connected in series divider clock cestocidal divider clock frequency, thus the output of the amplitude detector via the drive is connected to the input of the comparison with the threshold, the output of which is connected to the second control inputs of the first and second switches, in addition, the output of the second switch is connected to the input of the tunable frequency synthesizer, and the second signal output of the first switch is an output device.

 

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SUBSTANCE: proposed device depends for its operation on comparison of read-out signal with two thresholds, probability of exceeding these thresholds being enhanced during search interval with the result that search is continued. This broadband signal search device has linear part 1, matched filter 2, clock generator 19, channel selection control unit 13, inverter 12, fourth adder 15, two detectors 8, 17, two threshold comparison units 9, 18, NOT gates 16, as well as AND gate 14. Matched filter has pre-filter 3, delay line 4, n attenuators, n phase shifters, and three adders 7, 10, 11.

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1 cl, 3 dwg

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