Circuit emulation short packets

 

The invention relates to the field of telecommunications. Technical result achieved - better use of bandwidth when the data transport circuit emulation through connection for asynchronous transfer mode (ARP). The data transport circuit emulation with a low bit rate asynchronous transfer mode is improved by packaging data in short packets in accordance with the timing of the packaging, which is produced depending on the timing of the formation of the parcels of the BDA. Short packets multiplexer, is transported into the receiving module, where isolated and sent to the appropriate connection circuit emulation with the appropriate service frequency that restores based on the characteristics of the connection of the BDA. 5 C. and 47 C.p. f-crystals, 10 ill.

The technical field to which the invention relates the Present invention relates to telecommunication systems that use asynchronous transfer mode (ARP) for transporting data, voice type, as well as other types of data such as video data and management data. In particular, the present invention relates to a telecommunication system in which the BDA is used for the CSO or more compounds of circuit emulation (i.e. data sources, circuit emulation).

The prior art ADF is a standard Protocol that is commonly used to transfer asynchronous data telecommunication the telecommunication system with various applications. The BDA is based on the transmission of data packets of a fixed size, known as parcel of the BDA. The Protocol for each parcel of the BDA the same, according to which each parcel of the BDA contains 48 octets of payload and 5 octets of header. In General, the BDA is well known to specialists in this field of technology.

Data telecommunication, specific to each application, initially are in the format of sending data specific to the application. If for transporting data should be used ARP, characteristic for this application the data format is adapted so that it was compatible with the Protocol ARP. This is the level of adaptation of the BDA (UAA) 101, as shown in Fig. 1. Please refer to Fig. 1, where the application layer 102 is data telecommunication coming from a particular application system, which is the source of data telecommunication. As mentioned above, the task of WA 101 is reformatting the data so that they become compatible with the Protocol ARP. To the Dul.

One of the most well-known levels of OIA is the level UAA. For packaging of synchronous data (i.e. data circuit emulation) is typically used UAA, and the data itself, in turn, can be structured or unstructured. Structured data arranged in the sequence of data blocks, where is the boundary for each block of data is determined by the index structured data (RDM). DCU are specially used for alignment (i.e. recovery) of data in the receiving module. Unstructured data refers to the raw data, which do not contain information about the formation of frames.

WA is divided into two main functional sublayer, as shown in Fig. 1: sublayer 104 segmentation and rebuild (SIP) and sublayer 105 convergence. Sublayer 104 SIP pattisue incoming data into data blocks having a length of 47 bytes. Then sublayer 104 CIP adds 1 byte sequence number and 1 bit data type identifier (to identify the incoming data as structured or as unstructured). For example, if the bit of the data type identifier is installed in the unit, the first byte in the block contains the DCU. Sublayer convergence to support the Board of error.

With UAA associated with a number of fatal problems. First of all, it is too much delay, the necessary UAA for the preparation of the data block 47 bytes. For example, a typical service speed (i.e. the speed of incoming data) data for circuit emulation is 64 Kbits per second. The corresponding time delay for WA will be approximately 6 milliseconds (47 bytes/8 Kbytes). In addition, the transportation of the data from the transmitting module to the receiving module includes usually several transitions: therefore, already excessive delay of each transition is compounded. In addition, if we are talking about data with a low bit rate, it often happens that data to fill each parcel ARP is not enough. According to the Protocol parcels ARP UAA need to fill the remaining portion of each parcel ARP insignificant bits. This, in turn, leads to poor use of bandwidth. Since many applications, such as voice data, are very sensitive to delays in transportation data and because bandwidth is expensive, there is a real need to develop a more efficient method of transportation daggum commonly used UAA is UAA, sometimes referred to as WAM. UAE is typically used for sending asynchronous data with a low bit rate, for example speech data provider. In particular, WA splits the data streams with a low bit rate for small packets of data, which is often referred to as miniotelyami or micropolymer. Then these small data packets from a particular source asynchronous data with a low bit rate multiplexer together with small packets from other data sources for the formation of packages of the BDA. By dividing the data into smaller data packets and variable size and multiplexing these small packets from multiple data sources, reduce the delay in the transportation of data and improves the use of the band. In addition, delays in transportation can be further reduced, and further improve the use of the band, if we allow for the possibility of overlapping small packets of data for neighboring parcels ARP, as shown in Fig. 2.

The present invention improves performance of the BDA data for circuit emulation, using the functionality associated with WA. TAC as the level adaptation circuit emulation. According Fig. 3 in the present invention provided with the replacement WA 101 shown in Fig. 1, at level 305 adaptation circuit emulation and level 310 multiplexing of short packets, where the last level is functionally similar or identical to the above level UAA.

Accordingly, the present invention is batching data circuit emulation with a low bit rate before transporting these data through the connection of the BDA.

Another objective of the present invention is the improved use of bandwidth when the data transport circuit emulation through the connection of the BDA.

According to one aspect of the invention the above and other objectives are achieved by providing a device, system and/or method of data transport circuit emulation. They include data conversion emulation in the sequence of data packets circuit emulation, and then the insertion of a sequence of data packets circuit emulation in the parcel data. Then the parcel data is transported to the receiving module, depending on the timing of the formation of the parcel data. In addition, depending on the timing of the formation passerpromenade and other objectives are achieved by providing a device system and/or method of data transport circuit emulation. They include data conversion circuit emulation in a sequence of data packets circuit emulation and the insertion of a sequence of data packets circuit emulation in the parcel data. Then the parcel data is transported to the receiving module. Here, the length of the data packet is adjusted depending on the frequency of the service clock.

A brief description of the drawings the Objectives and advantages of the present invention are evident from the following detailed description, given with reference to the drawings, in which: Fig. 1 - level adaptation (UAA) asynchronous transfer mode (ADF) according to the prior art; Fig. 2 - multiplexing of short packets in the sending ARP according to the prior art; Fig. 3 UAA according to the present invention; Fig. 4 - short package contains the header and side information; Fig. 5A and 5B functional layers in accordance with the present invention, in the transmitting block;
Fig. 6 is a functional layers in accordance with the present invention in the receiving module;
Fig. 7A and 7B is a flowchart of the method of data transport circuit emulation with low speed Peretz> Detailed description of the invention
The present invention provides more efficient data transport circuit emulation with a low bit rate (i.e. synchronous data from the transmitting module to the receiving module via the connection of the BDA. In General, in the present invention this is accomplished by packaging the incoming data circuit emulation in one or more short packets, for example, a short packet 405, which contains several bytes of data, including the last byte of the data 410, as shown in Fig. 4. Since the length of each short packet is usually much shorter than the length of the payload of one parcel of the BDA, the sequence of short packets containing data circuit emulation, the specific connection of circuit emulation (i.e. data source) can be placed at the place of the payload of one parcel of the BDA. Quite often it happens that several short packets in the sequence generated by specific connection circuit emulation, not completely fill the payload of the current parcel of the BDA. To ensure maximum efficient use of bandwidth and reduce latency when transporting data in the present invention, in which her short packets, each sequence of short packets corresponds to the particular different type of traffic (for example, the control signals data, the encoded speech).

This does not mean that the present invention completely eliminates the use of insignificant bits. However, if insignificant bits required in the present invention they are used only to fill the remaining part of the short packet, for example, the last byte 410 data in a short package 405, as shown in Fig. 4. Also, if you are using non-significant bits, specialists in the art it is obvious that the counter 415 acknowledge bit (NSS) can be included in the device so that the receiving module could identify them correctly and discard. For example, the NSS contains 3 digits A0, A1, and A2. Accordingly, the NSS can define up to 8 acknowledge bit.

In Fig. 5A shows a functional levels and elements of the illustrative version 500 of the implementation of the present invention, as applied to the transmitting module of the telecommunication system. Three functional levels represent the level 505 ARP, 510 short packets and the level 515 adaptation circuit emulation. As mentioned earlier, in astutely option 500 operates as follows. Data 520 circuit emulation specific connection 525 circuit emulation synchronized in the input buffer 530, located in level 515 adaptation circuit emulation by means of a generator 535 official clock GN SL SI). The input buffer 530 is a hardware component that contains multiple shift registers which convert sequential code in parallel.

GN SL SI running at a certain frequency and can be supplemented by a generator HR clock (not shown), if the data circuit emulation are structured. The purpose of the generator HR clock - to identify the beginning of each data frame. Therefore, the frequency generator HR clock will be derived from the frequency generator service signal.

Level 515 adaptation circuit emulation also includes a clock generator for packaging. In particular, it includes the synchronization signal 540 packaging. In one embodiment, the synchronization signal 540 packaging create by using divider 545 frequency with respect to the signal generated by the generator 550 clock generation parcels ARP, which is provided in the level 505 ARP. As a display, which sets the operator. Therefore, the operator can adjust the trigger period of the packaging, setting the value of K. Since the length of the short packets depends on the trigger period of the packaging, the operator can adjust the length of the short packets retrieved from the input buffer 530. Note that the length of the short packet also depends on the frequency of the service clock. For example, if the trigger period of the packaging will increase, the same thing will happen with the length of the short packet. Similarly, if you increase the service frequency, the same thing will happen with the length of the short packet.

In the second embodiment, as shown in Fig. 5B, the synchronization signal 540 packaging is obtained by using the K-factor applied to the signal produced by the generator 535 of the service signal. Again, the operator can adjust the trigger period 540 packaging, adjusting the value of K.

If the data circuit emulation are structured, the sequence of short packets will come from the input buffer 530 module 555 generation RDM. The generation module DCU DCU generates, which, as explained earlier, is used to maintain alignment kanost short packets will come from the input buffer 530 in the module 560 generation title. Then, the generation module generates header header 420 for each short packet 405. The header may contain, for example, DCU (if required), the counter sequences, the data type identifier and the connection identifier circuit emulation.

Then a sequence of short packets is supplied to the multiplexer 565 short packets. The short multiplexer multiplexes packets sequence of short packets containing data circuit emulation, connection 525 circuit emulation thread parcels ARP with short packets containing data from other connections (not shown), including compounds of circuit emulation and/or connections with other types of traffic (for example, control signals and densified speech). Because the multiplexer 565 short multiplexes packets, short packets from a large number of compounds, each of which can send short packets simultaneously, the order in which the multiplexer 565 short multiplexes packets, short packets is determined by the programmed priorities table that specifies for each short packet its relative priority of transmission. Thanks to the data multiplexing circuit emuladores transfer and more efficient utilization of bandwidth.

Specialists in the art it is well known that the level 505 ARP can support several different types of allocation of frequency bands, or categories of traffic, for example services with a constant bit rate (POST. SC), services with variable bit rate (PER.SC), available bit rate (HON. IC) and services with an arbitrary bit rate (PRODUCTION.IC). In accordance with a preferred embodiment of the present invention dispatching parcels ARP is carried out from the transmitting module, and the destination is a constant, the peak frequency of the parcels is performed by the generator 550, clock generation parcels ARP. Since the synchronization signal 540 packaging comes directly from the generator 550 clock generation parcels of the BDA, the likelihood of mutual interference in the generation of short packets and generating parcels ARP small.

If the generator clock generation parcels BDA points that must be made to transport parcels BDA module 570 generate header level 505 ARP adds the standard header sending ARP to the payload of the current parcel of the BDA. Then the header and the transport obviously, sending ARP may pass through several switches ARP before it will be required in the receiving object. Each of these switches ARP introduces additional delays in the process of transportation, regardless of the present invention.

In Fig. 6 shows the functional layers according to the present invention as applied to a receiving module in accordance with an illustrative option 600 implementation. As in the case with the transmitting module, functional levels represent the level 605 ARP, level 610 short packets and 615 adaptation circuit emulation. Similarly, the present invention replaces WA 101 level 610 short packets and 615 adaptation circuit emulation.

Illustrative option 600 implementation works as follows. Level 605 ARP accepts incoming parcel ARP from the transmitting module, where module 620 remove header ARP removes the header sending ARP from the current incoming payload sending ARP, and then delivers the payload to the demultiplexer 625 short packets located in the level 610 of short packets. The demultiplexer 625 short packets divides the sequence of short packets according matched with what you're going to the appropriate level of adaptation. Short packets containing data circuit emulation, are on the level adaptation circuit emulation, for example the level 615 adaptation circuit emulation.

For 615 adaptation circuit emulation module 630 remove the heading of short packets, removes the header from each short packet. Module 630 remove header is also responsible for the allocation of the DCU, if the corresponding sequence of short packets contains structured data. Then the module 630 remove header sends short packets and RDM, if short packets contain structured data in the output buffer 635. The output buffer 635 uses RDM for segmentation of data blocks and generating signals of frequency blocks. For example, if emulated standard line PDH/SDH (plesiochronous digital hierarchy network/synchronous digital hierarchy network), the DCU will be used to identify boundaries 0,125-microsecond frame. The output buffer 635 is a hardware component that contains the number of shift registers which convert data from parallel to serial.

Module 630 remove header is also responsible for momentum transfer initiating recovery synchronization nestrukturirovannye data. Regardless of whether it contains a sequence of short packets structured or unstructured data, the recovery module synchronization, in turn, regulates the speed at which data is transmitted from the output buffer 635 in connection 645 circuit emulation. To accomplish this, the module 640 recovery synchronization regenerates (i.e. restores) the frequency 535 office clock, so that the data circuit emulation transmitted to the corresponding connection 645 circuit emulation with the required data rate. The recovery module synchronization can recover the frequency of the service clock in several different ways.

In a preferred embodiment of the present invention block 640 recovery synchronization recovers the frequency of the service clock, highlighting the frequency of the service clock from the stream ARP depending on the distribution of frequency of receipt of parcels ARP, where the distribution of frequency of receipt of parcels ARP directly reflects the frequency generator 550 clock generation parcels ARP. Then the module 640 recovery synchronization can use the frequency distribution of revenues Pasila is possible synchronization determines the frequency of the service clock according to the following ratio;
SVCCLK=NVAR*PCLK=NVAR*SHCLK(1)
where SVCCLKthe frequency of the service clock, RCLK- sampling clock batching SCLKthe sampling clock generation and NVAR- the size of short packets. Since NVARmay change due to fluctuations in the frequency of the service clock and the frequency of the timing of the formation of SHLKthe assessment of the utility of the synchronization signal is smoothed by the low pass filter, thereby reducing the variation in packet size.

With regard to structured data, the frequency unit of service is obtained in accordance with the following ratio:
SVCBLK=NVAR/NBLK=NVAR/NBLKSHCLK(2)
The block size of NBLKobtained in accordance with the DCU, which is allocated by the module 630 remove the header, as explained above. Frequency blocks is also not dependent on the block size, and it is assumed that the number of time intervals (slots) for standard circuit emulation connection PDH/SDH can be changed without significant resynchronization service clock frequency blocks. The above-described method of recovering synchronization Keitele on layer properties 605 ARP, already adapted to the variations of the delay caused by multiplexing of short packets. Accordingly, the module 640 recovery synchronization can be more accurately calculate the frequency of the service clock.

However, the module 640 recovery synchronization can to restore the service signal in accordance with any known method, in particular ways, most commonly used with UAA. In accordance with one way to restore synchronization utility restore sync signals from the sync signal external network. This method does not require the restoration of internal synchronization. Another known way to restore service signals is a method of adaptive restore synchronization. This method involves measuring the average level of the output buffer, and then use the measurement results to adjust the phase diagram synchronization (SPS) module 640 restore synchronization. Another known way to restore service signals is a differential method of synchronous time stamps. This method includes the measurement of the difference between a stable system synchros the FS. These methods are well known to specialists in this field of technology.

Although recovery synchronization can be applied to any of the above known methods, the implementation of the present invention are obtained smaller deviation of latency. This is due to the fact that at least one of the above options synchronization signal 540 batching get from the generator signals forming packages of the BDA. Therefore, the characteristics of the recovery process synchronization depends mainly on the transmission characteristics at the level of 103 ARP, and not from the working characteristics of OIA.

In Fig.7 presents a flowchart illustrating the steps of the method of data transport circuit emulation with a low bit rate from the transmitting module to the receiving module in accordance with a preferred embodiment of the present invention. As shown in block 705, the data 520 circuit emulation first shift in the input buffer 530-level 515 adaptation data circuit emulation speed, which is specified service clock 535. Then the data 520 circuit emulation segment, if necessary, and is stacked in one or more useful n is to be added insignificant bits. Segmentation and, consequently, the size of the payload short packet regulate the clock 540 packaging, which is obtained from the generator 550 clock generation parcels ARP level 505 ARP or from the service clock 535.

The next step depends on whether the data 520 circuit emulation structured or unstructured, as shown in block 715 decision. If the data 520 circuit emulation are structured in accordance with the branch "Yes" out of the unit 715 decision-making at the level of 515 adaptation circuit emulation generate DCU, as shown in block 720, and use RDM in the receiving module to maintain alignment of the block of data and/or data frame. Then, at the level 515 adaptation circuit emulation generate the header for one or more short packets, in accordance with block 725. If the data 520 circuit emulation are unstructured, in accordance with the branch "No" out of the unit 715 decision-making at the level adaptation circuit emulation simply generate the header, as shown in block 725, without the prior generation RDM.

Generation RDM depends on whether the data circuit emulation structured the relationship between packet size and data block size of data. If such a correlation does not exist, then generate DCU, as explained above and as shown in Fig. 7B (blocks 750 and 760). However, if the data packet size and data block size has a fixed ratio, then it may be made a function RDM by installing team system configuration, for example, through the application of controls, as shown in Fig. 7B (blocks 750 and 755). Due to the absence of the generation and transport of DCU are very valuable bandwidth is saved for data and/or other important additional service information.

Once generated headers for one or more short packets, the header and the packaged data is sent to the level 510 short packets, where the packaged data multiplexer together with short packets generated by other compounds, as shown in block 730. As mentioned above, the order in which short packets from each connection multiplexers in the flow of the BDA will depend on a predetermined priority tables. Then form the premises of the BDA, dispatching them into the desired receiving module perform depending on generator clock generation parcels ARP in with the om module and highlight data circuit emulation with a low bit rate of the sequence of short packets, so that they can be properly directed in connection 645 circuit emulation, according to a preferred variant implementation of the present invention.

The method shown in Fig. 8, is implemented as follows. In accordance with block 805 sending ARP accept-level 605 ARP, where eliminate the header sending ARP and payload sending ARP is sent to the level 610 of short packets. Then a short packets demultiplexer the demultiplexer 625 short packets in accordance with their connections, circuit emulation, as shown in block 810. Then the demultiplexer 625 short packets sends each sequence of short packets in the appropriate level 615 adaptation circuit emulation, where the removal of the headers of each short packet in accordance with block 815. Then the corresponding payload short packets are sent to the output buffer 635, as shown in block 820, and give the signal to start the restore synchronization to initiate the recovery process service clock (that is, the regeneration frequency of the service clock, as shown in block 825). Once restored service trigger level 615 adaptation circuit EMU the existing service frequency according to block 830. It should be noted that internal synchronization signal can be recovered according to any one of those disclosed above in various ways. However, in the preferred embodiment of the present invention utility emit a synchronization signal depending on the characteristics of the level of the BDA, as disclosed above.

The present invention has been described with references to preferred implementation. However, for professionals in the art it is obvious that the invention can be implemented in specific forms other than those described preferred option for implementation. This can be done without departing from the scope of the invention. The preferred implementation is illustrative, and should not be construed as a limitation of any kind. The scope of protection of the invention defined by the attached claims, and assumes that all modifications and equivalents that fall within the scope of the claims, it is covered.


Claims

1. Device for data transport circuit emulation containing means for generating data packets for packaging data circuit emulation of posledovatelnuju data circuit emulation in the parcel data, means for transporting the parcel data in the receiving module depending on clock generator clock generation parcel data, and means for generating data packets adjusts the length of the data packet depending on clock generator clock generation parcel data.

2. The device under item 1, in which the means of multiplexing data includes means for multiplexing data packets from multiple connections in the parcel data in accordance with the table of priorities transmission.

3. The device under item 1, in which the means for generating the packet contains an input buffer for receiving data circuit emulation disconnecting circuit emulation and generator clock input buffer for adjusting the length of each data packet circuit emulation, and the input buffer responsive to the oscillator clock input buffer.

4. The device according to p. 3, in which the generator clock input buffer includes means for receiving clock generator clock generation parcel data, and the means of the frequency divider for dividing the frequency of the clock generation parcel data.

6. The device under item 1, in which the data circuit emulation are structured data.

7. The device according to p. 6, in which means for generating data packets includes means for input of block structured data circuit emulation from a data connection, circuit emulation, and means for generating a structured data pointer, if there is no fixed ratio between the length of the data block and the length of the Covenant of the data.

8. The device according to p. 6, in which means for generating data packets includes means for entering data block circuit emulation from a data connection, circuit emulation, and means for generating configuration commands, reflecting a fixed ratio between the length of the data block and the length of the data packet.

9. The device under item 1, in which the data circuit emulation is unstructured data.

10. Device for data transport circuit emulation containing the input tool data transfer circuit emulation connection from circuit emulation in the above-mentioned device in accordance with the frequency of the signal generator service clock, means for generating data packets for packaging data circuit emulation in a sequence of packets demnos emulation in the parcel data and the means for transporting the parcel data in the receiving module, and means for generating data packets adjusts the length of the data packet depending on the frequency of the service clock.

11. The device according to p. 10, in which the means generating the data packet contains an input buffer for receiving data circuit emulation connection from circuit emulation and generator clock input buffer for adjusting the length of each data packet circuit emulation, and the input buffer responsive to a signal generator clock input buffer.

12. The device according to p. 11, in which the generator clock input buffer includes means for receiving the synchronization signal from generator service clock and the means of the frequency divider for dividing the frequency of the signal generator service clock.

13. The device according to p. 10, in which the means of multiplexing data includes means for multiplexing data packets from multiple connections, the message for forwarding data in accordance with the table of priorities transmission.

14. The device according to p. 13 in which the parcel data is sending asynchronous mode transfer (ARP).

15. The system for transporting data circuit emulation in a telecommunications network containing an input buffer for PR is and, connected to the input buffer to generate a packaging signal, which controls the data conversion circuit emulation at least one data packet circuit emulation, the multiplexer of the data packet for multiplexing at least one data packet circuit emulation in a stream of data packets comprising the data packet is associated with at least one other connection, the clock generator units for generating timing of the formation of the parcel data, which manages the allocation of a payload of the parcel data from the stream of data packets and the transmission medium for data transport payload sending data to the receiving module, moreover, the generator clock input buffer generates a signal jamming and controls the length of the data packet circuit emulation depending on the timing of the formation of the parcel data.

16. The system under item 15, in which the generator clock input buffer contains a frequency divider, responsive to the synchronization signal of the formation of the parcel data.

17. The system under item 16, in which the frequency divider divides the signal formation parcel data Ketov data multiplexes at least one data packet circuit emulation in a stream of data packets in accordance with the table of priorities transmission.

19. The system under item 15, in which the payload of the parcel data is part of the parcel asynchronous transfer mode (arm).

20. The system under item 15, in which the data circuit emulation are structured data.

21. System on p. 20, further containing a means for input of block structured data circuit emulation from a data connection, circuit emulation, and means for generating a structured data pointer, if there is no fixed ratio between the length of the data block and the length of the data packet.

22. System on p. 20, further containing a means for entering data block circuit emulation from a data connection, circuit emulation, and means for generating configuration commands, reflecting a fixed ratio between the length of the data block and the length of the data packet.

23. The system under item 15, in which the data circuit emulation is unstructured data.

24. The system under item 15, further containing a means of input for receiving payload parcel data transfer tool for demuxing connected to the input means, for selecting at least one data packet circuit emulation, the output buffer for selecting data from the second connection circuit emulation depending on the speed of the data transfer circuit emulation and restore synchronization, connected to the output buffer, for receiving speed data transfer circuit emulation based on the frequency of receipt of the parcel data.

25. System on p. 24, in which the frequency of incoming data depends on the timing of the formation of the parcel data.

26. System on p. 24 in which the means of restoring synchronization includes means for measuring the distribution of frequency of receipt of the parcel data and the tool to install speed data transfer circuit emulation depending on the distribution of frequency of receipt of the parcel data and the variable To a custom operator.

27. System on p. 24, in which the payload of the parcel data is part of the parcel asynchronous transfer mode (arm).

28. The system under item 15, in which the means for transferring data includes a tool to support multiple classes of service traffic.

29. System on p. 28, in which many categories of service traffic includes a constant bit rate.

30. System on p. 28, in which many categories of service traffic includes services with variable bit rate.

31. System p. itov.

32. System on p. 28, in which many categories of service traffic includes services with an arbitrary bit rate.

33. The method of data transport circuit emulation connection from circuit emulation in the receptacle, which carry out the shift data circuit emulation in the input buffer from the first connection circuit emulation, batching data circuit emulation at least one data packet circuit emulation in accordance with the timing of the packaging, the multiplexing at least one data packet circuit emulation in the parcel data transfer and transportation of parcel data in the receiving module in accordance with the timing of the formation of the parcel data, and the packaging signal derived from the timing of the formation of the parcel data.

34. The method according to p. 33, which additionally carry out multiplexing at least one data packet in the parcel data from compounds other than the above-mentioned connection circuit emulation.

35. The method according to p. 34, which additionally provide the installation of the priority data for each connection and multiplexing by the Mei from the said connection circuit emulation in the parcel data in accordance with the priority data.

36. The method according to p. 33, which additionally carry out the division of the frequency of the timing of the formation of sending data to a variable To receive the timing of the packaging.

37. The method according to p. 33, whereby the transportation of parcel data in the receiving module includes transportation of multiple classes of traffic.

38. The method according to p. 37, in which many categories of service traffic includes a constant bit rate.

39. The method according to p. 37, in which many categories of service traffic includes services with variable bit rate.

40. The method according to p. 37, in which many categories of service traffic includes services with the available bit rate.

41. The method according to p. 37, in which many categories of service traffic includes services with an arbitrary bit rate.

42. The method according to p. 33, on which the parcel data is sending asynchronous transfer mode (arm).

43. The method according to p. 33, on which the data circuit emulation are structured data.

44. The method according to p. 33, on which the data circuit emulation are restructurize circuit emulation in a telecommunications network, at which carry out the shift data circuit emulation in the input buffer, depending on the frequency of the service clock, batching data circuit emulation at least one data packet circuit emulation, having a length defined by the sampling clock batching multiplexing at least one data packet circuit emulation in the parcel data transfer and transportation of parcel data in the receiving module in accordance with the sampling clock generation parcel data, and the sampling clock packaging is produced from the frequency of the timing of the formation of the parcel data, and sending data to the receiving module, allocating at least one data packet circuit emulation of parcel data recovery frequency of the service clock and the data transfer circuit emulation contained in at least one data packet circuit emulation, the second data connection circuit emulation in accordance with the recovered frequency of the service clock.

46. The method according to p. 45, by which the restoration of the frequency of the service clock includes restoring frequency sync service is being parcel data depends on the frequency of the clock generation parcel data.

47. The method according to p. 46, by which the restoration of the frequency of the service clock involves measuring the distribution of frequency of receipt of the parcel data and restore the frequency of the service clock based on the measured distribution of the frequency of receipt of the parcel data and the variable To a custom operator.

48. The method according to p. 45, by which the restoration of the frequency of the service clock includes the restoration of the frequency of the service clock signals from the external network.

49. The method according to p. 45, by which the restoration of the frequency of the service clock includes the restoration of the frequency of service adaptive clock recovery method for synchronization.

50. The method according to p. 45, by which the restoration of the frequency of the synchronization signal includes the restoration of the frequency of the service clock by way of a differential synchronous timestamp.

51. The method according to p. 45, which additionally carry out the generation of the index structured data, if the data circuit emulation are structured data and if there is no fixed ratio between the length of the block and the length of the data packet.

52. The method according to p. 45,the ratio between the length of the block and the length of the data packet, if the data circuit emulation are structured.

 

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The invention relates to communication systems, spread spectrum

FIELD: radio communications.

SUBSTANCE: proposed method intended for single-ended radio communications between mobile objects whose routes have common initial center involves radio communications with aid of low-power intermediate transceiving stations equipped with non-directional antennas and dropped from mobile object, these intermediate transceiving drop stations being produced in advance on mentioned mobile objects and destroyed upon completion of radio communications. Proposed radio communication system is characterized in reduced space requirement which enhances its effectiveness in joint functioning of several radio communication systems.

EFFECT: reduced mass and size of transceiver stations, enhanced noise immunity and electromagnetic safety of personnel.

1 cl, 7 dwg, 1 tbl

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