Fault-tolerant memory device

 

The invention relates to the field of automation and computing. The technical result is to increase functionality. The device contains two coding devices, the computing unit syndrome, concealer, ten items OR block elements And RS-flip-flop, register, four block elements disparities, two decoder, the element is NOT, the storage unit of the amendments, the computing unit characteristic of the amendment, the original and redundant computing channels. 2 Il.

The invention relates to computer technology and can be used to provide fault tolerance RAM.

Known self-correcting device [1], contains the original combinational logic block, the redundant combinational logic block. the computing unit of the syndrome decoder of the error and the offset, the input devices are connected to the inputs of the original combinational logic block and the redundant inputs combinational logic block, the information outputs of which are connected to the inputs of the computing unit of the syndrome, the outputs of which are connected to the inputs of the syndrome decoder errors, the outputs of which are connected to the inputs of the source is the terrain correction of multiple errors.

The closest technical solution is samconnection device [2] , containing the source computing channel (random access memory), the encoder, the redundant computing channel (discharges a storage device for storing the values of the control bits), the unit for computing the syndrome decoder, concealer, input devices are connected to the inputs of the original scheme and to the inputs of encoder whose outputs are connected to first inputs of the computing unit of the syndrome, the outputs of the source computing channel connected to the second inputs of the computing unit of the syndrome and to the first inputs of the offset, the outputs of the computing unit of the syndrome are connected to the inputs of the decoder, United by their outputs, with the second inputs of the offset, the outputs of the corrector are the outputs of the device.

The disadvantage of this device is the lack of error correction arbitrary multiplicity in the information bits.

The aim of the invention is to expand the functional capabilities of the device by providing error correction of arbitrary multiplicities that occur in the information bits.

This objective is achieved in that the device containing the comprehension syndrome, the first decoder, concealer, further comprises a second encoder, from the first to the tenth elements OR first to fourth delay elements, the element I. the block elements And RS-flip-flop, a register, first to fourth blocks of elements disparities, the second decoder, the element is NOT, the storage unit of the amendments, the computing unit sign amendments, and address inputs connected to the first inputs of the source computing channel information input through the first and second elements OR connected to the second inputs of the source computing channel and to the first inputs of the first encoding device, connected by their outputs through the third and fourth elements OR to the first inputs of excess computing channel, the input set to the initial state through the fifth element OR is connected to the zero inputs of the register and RS-trigger input "reading" is connected to the input of the "write register", through the seventh element OR to the third input of the source computing channel to the second input of excess computing channel and through the first delay element to a single input of the RS flip-flop input record through to the sixth element OR connected to the fourth input of the source computing channel, the third the passages of the register, to the first inputs of the computing unit of the syndrome and to the first inputs of the first block of elements disparities, the outputs of the redundant computing channel connected to the second inputs of the computing unit of the syndrome, to the third inputs of the register and to the first inputs of the second block elements disparities, the outputs of the computing unit syndrome is connected to the fourth inputs of the register, single output RS-flip-flop connected to the input of the read register, via a second delay element to the first input of the corrector, through the third delay element to the second input of the fifth element OR through the fourth delay element to the second input of the seventh element OR the first group of outputs of the register is connected to the second inputs of the first to fourth elements OR the second group of outputs of the register is connected to the second inputs of the first block of elements disparities and to second inputs of the offset, the third and fourth group of output registers connected respectively to the second inputs of the second block elements disparities and to the first inputs of the third block elements disparities, the output of the first block of elements disparities to the inputs of the second coding device, to the input element And to the inputs of the ninth element OR to the first whdi eighth element OR the ninth element OR element And is connected to the input of the first decoder, the first outlet through which the element is NOT connected to the first input of the block elements And the second group of outputs connected to the inputs of the tenth element OR the outputs of the third block elements disparities are connected to the inputs of the second decoder, connected by their outputs to the inputs of the storage unit of the amendments, the outputs of which are connected to the second inputs of the computing unit characteristic of the amendments connected to their outputs, with the second inputs of the fourth block elements disparities, the outputs of the fourth block elements disparities through the block And is connected to a third input of the corrector, the outputs of which are information output device, the output of the tenth element OR an output signal "Failure".

Currently, the error correction storage devices that are generally used codes correcting single errors. At the same time, there is a need for error correction of arbitrary multiplicity, i.e., there is a need to develop methods of correction of multiple errors.

However, the implementation of multiple-error correction based on linear freezing information that not only allows to increase the reliability and validity of the failover operation of the transmitter, but also reduces these indicators.

The basic idea is to eliminate this contradiction lies in the a posteriori error correction, which is that for the detection of errors is used correcting linear code that can correct a single error (requiring minimal hardware cost), and the configuration definition (erroneous discharge) is a multiple of the error and its correction are performed on the results of the analysis of responses received on the basis of filing a single impact test (requiring a minimum of time).

Basic concepts and definitions. Let the error correction code set is based on correcting linear code that can correct a single error.

Each work input set XNcorresponds to the code set Y={y1,y2, ..., yk,rk+1,rk+2, ..., rn}, (1) where yithe values of signals in the information bits; rjthe values of signals in the control bits.

Vector control bits R is a function of the information bits and is determined by the rule kovrovaja messages regarding information bits of the re-formed vector control bits RPand define the syndrome of the error EC= RRP. (3) Each work input set XNproviding a specific value of the signals in the information and check bits Yk={I1,2,...,yk,rk+1, rk+2, . . .rn}, put under test kitgenerating the inverse value of signals in the information and check bits.

Definition 1. The inverse value of the summation of the values of information and control bits Yk={I1,2,...,yk,rk+1,rk+2,...rn} received on start input information and control bits YTobtained on the test set, we assume the test vector errors:If there are no errors, the test vector errors accepts null values.

Definition 2. Hidden will be called error, which is not shown on the input working set.

Example. Option of single values in the information bits of the Hamming code (r1, r2, y2, r3, y1) corresponds to error-free code set 01111. When nalichii 01111+(the sign "+" is marked erroneous discharge), which is not different from error-free code set.

Definition 3. Wrong code set will be called "correct", if it does not contain hidden errors and "incorrect" otherwise.

Approval 1. Fix "incorrect" error code set based on the test vector error leads to pseudocircles.

Proof. When applying test stimuli, providing the opposite value of the information bits detected any errors. In this case, the test vector errors indicates the number of erroneous information bits, including bits that contain hidden errors. Since the values of hidden errors to match the operating input set, the correction based on the test vector errors, in turn, will lead to an error in the corrected code set.

Corollary 1. A posteriori correction of multiple errors is possible if you identify hidden errors (formation amendments to the test vector errors).

Based on the above concepts and definitions the objective of identifying the configuration of multiple errors on the results of algebraic operations with the values of the syndrome error>The rules of formation values of the error vector. The procedure for determining the error vector based on the following theoretical propositions.

Encoding the information bits of the test vector error according to the rules of the considered code gives error code test bits Eand=f(Band). (5)
In the result of summation of the syndrome of the error and the error code of the test bits of the receive address code amendments on hidden error
EK= ECEAnd. (6)
Based on the obtained values of EWithEAndand ETothe decision on the correction of errors in the information bits in the condition that the number of errors in the information bits dk-1.

In this case, the decoding strategy includes the following provisions:
correction is possible if the bits of the test vector errors, the corresponding control bits have values of zero;
permitted transfer of information bits without correction, if the test the error vector contains a zero value in the information bits and the singular values (errors) in the control bits;
correction prohibited (a signal is generated "Failure") if all bits of the or in the presence of singular values of signals simultaneously in the information and check bits of the test vector errors;
upon the occurrence of a latent error is the error vector is formed by adding amendments to the test vector errors.

The rules of formation values of the amendment upon the occurrence of latent errors. To determine amendments to the test vector errors will build the decision table (correction for each latent error).

In this case, the number of amendments makes a lot of power |SM| = 2k.
Each hidden error will deliver in compliance with the correction value and the corresponding address code amendments.

This set can be written as the defining matrix

where Cij- the values of the bits of the vector of corrections 0=0, 1, 2,...,2k-line number; j= 0, 1, 2,... k is the column number); eijvalues of bits of the code address of the amendment.

Property 1. Each code addresses amendments (right group of elements defining matrix) corresponds to the direct and the inverse of the bits of the vector of corrections

where Cj- direct value of the category of vector errors;- the inverse value of the category of the error vector.

This property follows from the denition of the dual erroneous code set (opposite snakeeye matrix (7) those lines in which the number (binary equivalent) values of the vector of corrections corresponds to 2i(i=1, 2,..., k), and build a table of amendments:

Table properties of amendments.

Property 2. To select values of the amendment is necessary to form the basis of amendments-V (direct or inverse values of the bits of the amendments with respect to this code addresses amendments).

Thus, the correction of multiple errors of the proposed method is based on the values of the information bits of the test vector errors and value adjustments for hidden error, i.e. the error is:

where- the value of the category of vector amendments (forward or reverse).

Property 3. The amendment has the opposite value if all values of the bits of the vector amendments coincide with the values of the respective information bits of the test vector errors and direct otherwise.

Example. We will build correcting code A(n, k) with a posteriori correction of multiple errors on the example threshold coding And(5, 3): (r1= y1y2; r2= y1yROM table of amendments:

Suppose you want to encode the message
In this case, the check bits have values of r1r201. Thus, the code set is transmitted in the form YK=00101.

If no error occurred, the syndrome of the error EChas a zero value. By submission of test stimuli, providing the opposite value of the information bits, obtain a test vector errors=00000, i.e. error code test bits FAnd=00, ETo=00 and the value of control bits of the test vector RbP= 00. Since the reverse correction value C=111, the received code addresses amendments ETo=00, does not coincide with the values of the information bits of the vector In, then the direct adjustment value C=000. Thus, the error vector is equal to: E = BC = 000.
May the message transmission error occurred in the first and second information bits: Y*to=1*1*1 01. Using the expression for this case are:
In=11000; EAnd=01; FWith=01; EK=00; C=000; E=110. The vector error is equal to the test vector error, which indicates an error in the first and second information is e and the latent error in the second informational category Y*to=1*0+01, then:
B=11000: EAnd=01; EC=11; EK=10; C=010; E=100.

Since the reverse correction value C=101 (obtained from table amendments to the code addresses amendments EK=10) does not match the value of the third information discharge test of the error vector, then the direct adjustment value C=010. Then E=100, i.e., the corrected first data bit.

In Fig.1 presents a block diagram of the fault tolerant storage device. Failover storage device contains the source computing channel 1, the redundant computing channel 2, the first encoder 3, the second encoder 4, the computing unit syndrome 5, corrector 6, from the first to the tenth 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 the elements OR first to fourth 17, 18, 19, 20 delay elements, a 21-item, block 22 items And RS-flip-flop 23, a register 24, the first to fourth 25, 26, 27, 28 blocks of elements disparities, the first 29 and second 30 decoders, 31-item does NOT, the unit 32 storing amendments, block 33 calculation of sign amendments, the inputs 34, 35 are input unit 33 to calculate the sign of the amendments, the output 36 is the output of block 33 calculation of the sign of amendments, entry 37 "Entry", entry 38 "Reading", entry 39 "Reset", the address inputs of Oia signal "Failure".

In Fig.2 shows the block circuit 33 calculation of the sign of the amendments It contains a group of 44 members, 45-item, items 46 equivalence, 47-item does NOT, the group of elements 48 disparities.

Address input 40 is connected to the first inputs of the source computing channel 1, the information input 41 through the first 7 and second 8 elements OR connected to the second inputs of the source computing channel 1 and to the first inputs of the first coding device 3, connected by their outputs through the third 9 and fourth 10 items OR to the first inputs of excess computing channel 2, input 39 "reset" through fifth 11-element OR is connected to the zero inputs of the register 24 and RS-flip-flop 23, entry 38 "reading" is connected to the input of the write register 24, through the seventh of the 11-element OR to the third input of the source computing channel 1 to the second input of excess computing channel 2 and through the first delay element 17 to a single input of the RS flip-flop 23, entry 37 "record" through sixth 12-element OR connected to the fourth input of the source computing channel 1, the third input of the redundant computing channel 2, the outputs of the source computing channel 1 is connected to the second inputs of the register 24 to the first input unit 5 vitiligo channel 2 is connected to the second inputs of the block 5 calculation of the syndrome, to the third input register 24 and to the first inputs of the second unit 26 items disparities, the outputs of block 5 calculation of the syndrome is connected to the fourth inputs of the register 24, a single output RS-flip-flop 23 is connected to the input of the "reading" of the register 24, through the second delay element 18 to the first input of the corrector 6, through the third delay element 19 to the second input of the fifth 11-element OR through the fourth delay element 20 to the second input of the seventh 13-element OR the first group of outputs of the register 24 is connected to the second inputs with the first 7 on the fourth 10 items OR the second group of outputs of the register 24 is connected to the second inputs of the first unit 25 items disparities and to second inputs of the offset 6, the third and fourth groups of outputs of the register 24 are connected respectively to the second inputs of the second unit 26 items disparities and to the first inputs of the third block 27 elements disparities, the output of the first block of 25 items disparities are connected to the inputs of the second coding device 4, to the inputs 21-item And, to the inputs of the ninth 15-element OR to the first inputs of the fourth block 28 items disparities and to the first inputs of the block 33 calculation of sign amendments, the outputs of the eighth 14-item OR ninth 15-leidlichen to the first input unit 22 elements And, and the second group of outputs connected to the inputs of the tenth 16-element OR the outputs of the third block 27 elements disparities are connected to the inputs of the second decoder 30 that are connected by their outputs to the inputs of the block 32 storage of the amendments, the outputs of which are connected to the second input unit 33 to calculate the sign of the amendments connected to their outputs, with the second inputs of the fourth block 28 items disparities, the outputs of the fourth block 28 items disparities through the block 22 elements And connected to a third input of the corrector 6, the outputs of which are informational outputs 42 of the device, exit ten 16-element OR an output 43 of the signal "Failure".

The source computing channel 1 represents a semiconductor RAM memory containing, for example, a three-digit memory (each memory cell includes three trigger) capacity M memory cells.

Redundant computing channel 2 is a memory device for storing values of the control bits.

The first encoder 3 (relative to the three information bits) has two outputs r1, r2, which sold �="https://img.russianpatents.com/chr/8853.gif">y3; (9)
The second encoder 4 performs functions similar to the first codereuse device 3 relative to the information bits of the test vector errors:
d1= b1b2; d2= b1b3.
Unit 5 the calculation of the syndrome performs an operation of re-coding the data read from the source computing channel 1(r11= y11y12; r12= y11y13); and calculating the syndrome of the error EC:

Corrector 6 is intended to correct errors by adding information bits with error:

From the first 7 on the seventh of 13 members, OR are designed to provide functional linkages between blocks of the device, the eighth of 14-and the ninth element OR 15-item OR are intended, respectively, for detection of single values of the signals in the control bits (failure of elements of the redundant computing channel 2) and the information bits of the test vector errors (failure elements Exod output 21-item) or the simultaneous occurrence of errors in the information and check bits (signals at the outputs 14 eighth and ninth 15 items OR get a tenth of the 16-element OR a signal is generated "Failure". From the first 17 by fourth 20 delay elements provide synchronization of block devices.

When the error occurs only in the control bits (the presence of a single output eighth 14-element OR the zero value of the signal at the output of the ninth 15-item OR output of the first decoder 29, a signal is generated, through which the element 31 is NOT, block 22 items And prohibits the correction of information bits.

RS-trigger 23 in conjunction with elements of the delay controls the blocks of the device.

The register 24 is designed for temporary storage of code set:
YCRvalues of the signals of information bits; RCRvalues of the signals of the control bits; FWithvalues of the signals syndrome errors; yinv- inverse (test) values of the information signals and Rinvcontrol bits.

The first block of 25 items disparities is designed to generate a test vector errors by adding the direct values of the information bits YCR(read with direct output register 24 information bits YTread from the source computing channel 1 after feeding him test the influence of the anosagnosia is designed to generate signals in the control bits of the test vector errors by adding direct value of the control bits RCR(read with direct output register 24) with the values of control bits RTread with excess computing channel 2 after feeding him test the impact of Rinv(values of signals that are read from the inverted output of the register 24).

The third block 27 elements disparities is designed to generate code addresses amendments EKby adding the values of the error code test bits FAndand values of the syndrome of the error EWith.

The fourth block 28 items disparities is designed to generate the error vector E by adding the information bits of the test vector errors adjusted With.

The second decoder 30 is used to select the amendments of the unit 32 storing amendments to the code addresses amendments ETo.

Block 32 storage of amendments is designed to store information represented by the matrix amendments (8).

Unit 33 the calculation of the sign of amendments is intended for selecting the forward or reverse correction values and works as follows (see Fig.2). The meaning of the code addresses amendments ETofrom block 32 storing amended to read feedback correction value (containing for this error is the maximum number a single is 44 And, group elements 46 equivalence and group elements 48 disparities. The values of the information bits of the test vector errors arrive at the inputs of block 34 33 calculation of the characteristic of the amendment.

In this case, open the elements And groups of elements 44 And having at its input a single value signals of the amendments and the information bits of the test vector errors. If the value of the signals coming from the outputs of the elements And match the adjustment value, the outputs of all elements of the group elements 46 equivalence appear singular values of the signals (open item 45). In this case, the signal at the output of element 47 has a value of zero, so the outputs of the elements 48 disparities removed feedback correction value. If the correction value does not coincide with the values of signals of the test vector error (signal at the output of the element 45 And has a zero value), the signal coming from the output of the element 47 is NOT on the inputs of the elements 48 disparities, provides the inversion of the values of the signals amendment (formed direct adjustment value).

The device operates as follows. Before working on the entrance 39 signal Reset, which is a fifth element 11 OR the s memory to the inputs 40 in the selected cell information is recorded, at the input 41. At the same time supplied information is encoded by the first encoder 3, and the value of control bits are written in the redundant computing channel 2.

Upon receipt of the signal "Read" to the selected address signal from input 38 through the seventh element 13 OR fed to the input of read the source computing channel 1 and redundant computing channel 2.

Information read from the source computing channel 1 and redundant computing channel 2, is supplied to the calculation unit 5 syndrome, where it is re-encoded and compared with the values of control bits, i.e., calculates the syndrome of the error. In addition, the signal from input 38, permitted the recording of information bits and the values of the syndrome of the error in the register 24.

Over time, defined by the first delay element 17, the RS-flip-flop 23 is translated into a single state and a single signal enables reading data from the register 24.

The information read from the inverted output of the register 24 (the test stimulus), through the first 7, second 8, the third 9 and fourth 10 items OR arrives at the inputs of the source computing channel 1 and redundant computing channel 2.

Received response information (YT, RTcompared with the original data (YCR, RCRrespectively the first block of 25 items disparities and the second block 26 items disparities, i.e., the test vector error Century.

The resulting value of the information bits of the test vector errors is encoded by the second encoder 4 (raises an error code test bits FAnd) and then compared with the value of the syndrome of the error EWithon the third block 27 elements disparities (formed is code addresses amendments ETo).

If there are no errors, then the bits of the test vector errors have zero values, respectively address code amendments ETohas a zero value. In this case, unit 32 storing amended to read feedback correction value whose bits are all one. As this correction value does not coincide with the values of the information bits of the test vector errors, the block 33 calculation of the sign of amendments selected direct adjustment value, i.e., the zero correction values. As a result of addition of values of the amendment and the values of the information bits of the test vector error (imetum 18 delay, corrector 6 receives the signal, allowing the correction. Since the error vector E is zero, the information bits are received at the output without change. After a time determined by the third delay element 19, the trigger 23 and the register 24 is transferred in its original state.

If an error occurs, all information bits (the appearance of the signal at the output of the element 21 or the simultaneous occurrence of errors in the information and check bits (the appearance of signals at the output 14 eighth and ninth elements OR the output of the tenth element 16 OR a signal is generated "Failure".

When the error occurs only in the control bits (the presence of a single value of the output signal of the eighth element 14 OR) and no errors in the information bits (the presence of the zero value of the signal at the output of the ninth element 15 OR the output of the first decoder 29 of a signal, which through the element 31 is NOT, block 22 items And prohibits the flow of signals of the error vector E corrector 6.

With the emergence of latent errors the third block 27 disparities generated address code amendments EToon which the second decoder 30 selects the feedback correction value from asratov test vector of the error block 33 calculation of the sign of amendments selected forward or reverse adjustment value. As a result of addition of values of information bits of the test vector of errors with the selected adjustment value of the fourth block 28 items disparities generated the error vector E.

Fix error corrector 6 is carried out by adding information bits YCRcontaining the error, the error vector E.

The proposed device allows to provide:
to discover the correct and hidden errors of any multiplicity;
to correct errors in the information bits of multiplicity dk-1;
the minimum equipment costs for the protection of information in comparison with the structural methods of booking and traditional methods of detection and correction of multiple errors on the basis of linear codes, which constitute 20-40% of the original equipment and commensurate with the cost code that can correct a single error;
the definition of configuration errors on the results of instant control (by filing a single test stimuli, which can be submitted only when an error occurs), i.e. practically without reducing the performance of the source device.

Sources of information
1. USSR author's certificate 1716521, CL G 06 F 11/18le="text-align:center; margin-top:2mm;">
Claims

Fault-tolerant memory device containing the source computing channel, redundant computing the channel, the first encoder, the unit for computing the syndrome, the first decoder, the address input device, information input device, the input write input read, corrector, the outputs of which are informational outputs of the device, characterized in that it further comprises a second encoder, from the first to the tenth elements OR first to fourth elements of the delay element And the unit element And RS-flip-flop, a register, first to fourth blocks of elements disparities, the second decoder, the element is NOT, the storage unit of the amendments, the computing unit sign amendments, input Reset, and the address inputs connected to the first inputs of the source computing channel information input through the first and second elements OR connected to the second inputs of the source computing channel and to the first inputs of the first encoding device connected with their outputs through the third and fourth elements OR to the first inputs of excess computing channel, the input "Reset" through the fifth element OR connected cent OR to the third input of the source computing channel to the second input of excess computing channel and through the first delay element to a single input of the RS flip-flop input Record through the sixth element OR connected to the fourth input of the source computing channel, the third input of the redundant computing channel, the outputs of the source computing channel connected to the second inputs of the register, to the first inputs of the computing unit of the syndrome and to the first inputs of the first block of elements disparities, the outputs of the redundant computing channel connected to the second inputs of the computing unit of the syndrome, to the third inputs of the register and to the first inputs of the second block elements disparities, the outputs of the computing unit syndrome is connected to the fourth inputs of the register, single output RS-flip-flop connected to the input of the Read register, via a second delay element to the first input of the corrector, through the third delay element to the second input of the fifth element OR through the fourth delay element to the second input of the seventh element, OR the first group of outputs of the register is connected to the second inputs of the first to fourth elements OR the second group of outputs of the register is connected to the second inputs of the first block is obtained according to the second inputs of the second block elements disparities and to the first inputs of the third block elements disparities, the output of the first block of elements disparities to the inputs of the second coding device, to the input element And to the inputs of the ninth element OR to the first inputs of the fourth block elements disparities and to the first inputs of the computing unit sign amendments, the outputs of the second block elements disparities are connected to the inputs of the eighth element OR the outputs of the eighth element OR the ninth element OR element And is connected to the input of the first decoder, the first outlet through which the element is NOT connected to the first input of the block elements And the second group of outputs connected to the inputs of the tenth element OR the outputs of the third block elements disparities are connected to the inputs of the second decoder, connected by their outputs to the inputs of the storage unit of the amendments, the outputs of which are connected to the second inputs of the computing unit characteristic of the amendments connected to their outputs, with the second inputs of the fourth block elements disparities, the outputs of the fourth block elements disparities through the block And is connected to a third input of the corrector, the outputs of which are information output device, the output of the tenth element OR an output signal "Failure condition

 

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FIELD: information technology.

SUBSTANCE: device has an input (1) for starting up the device, a group of shift registers (2), synchronisation unit (3), an output (4) of the device, a group of units (5) for calculating orthogonal bases, units (6) for three-input AND elements, a half adder (7), a group of data inputs (8), a group of control inputs (9) of the device, a group of clock inputs (10), a group of control inputs (11), where the group of units for calculating orthogonal bases has a first memory unit (12), a multiplier (13), a second memory unit (14), a multiplier (15), a register (16) and an output register (17).

EFFECT: broader functionalities owing to possibility of calculating values of orthogonal bases in case of failure of computing channels and their exclusion from the process of converting the modular code of a polynomial system of residue classes into a binary position code.

2 dwg, 2 tbl

FIELD: information technology.

SUBSTANCE: disclosed is a method for recognition of interruption-interruption interrelationships, involving: automatic recognition of interrelationships between interruptions and presentation of the final model, which includes an interruption-interruption intersection curve and one interruption which is cut off on the curve, an interpreter with display of interrelationships between interruptions. During interpretation, background simulation processes, which are 'automatically recognisable interrelationships between interruptions' are applied. These background processes (examined once more in this claim later) automatically form the surface of the interruptions during interpretation and their relative proximity is detected.

EFFECT: improved method in which the structure of interruptions in a formation is simulated as a built-in part of interpreting interruption.

28 cl, 26 dwg

FIELD: information technology.

SUBSTANCE: fault-tolerant processor includes two basic devices: a master node and an operating node. The master node includes an operation code decoder, a clock pulse generator, a control unit, an instruction counter, an address register and a correlation unit. The operating node includes a shift counter, a number register, an accumulator register, an extra register, an extra code register, an adder and a control unit. The technical result is achieved by including a correlation unit for detecting and correcting errors of the processor control memory, as well as by including a control unit which enables to detect and correct errors of the arithmetic logic unit when performing arithmetic and logic operations.

EFFECT: high failure-tolerance of the processor due to detection and correction of errors.

8 cl, 8 dwg

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