Method of adaptive frame synchronization code
The invention relates to the transmission of discrete information and can be used for frame synchronization in systems robust protection using corrective, in particular concatenated codes. The technical result - increased robustness frame synchronization when operating in non-stationary communication channels with variable parameters and a high level of interference. The technical result is achieved by the fact that the number of matches numbering and timing sequences, which determine the presence of frame synchronization, takes into account the quality of the communication channel. The quality of the communication channel is estimated the total reliability of the received code words with matching numbering and timing sequences. In turn, the reliability of the received code words are determined based on scales, the magnitude of which depends on the ratio of corrected code word errors. 1 Il. The invention relates to a method of transmitting digital data and can be used for frame synchronization in systems of error-correcting information security, which are corrective, in particular concatenated codes.Spasenija, the transmitted sequence of words cyclic error-correcting code. Adaptation in the proposed method will be called automatically and purposeful change of code frame synchronization in order to achieve optimal performance under changing conditions of reception of messages. When the coded frame synchronization clock characteristics are passed on words of error-correcting code. For synchronization does not require the transmission of additional special characters, and uses the redundancy of the error correcting code. After establishing synchronization signs synchronization subtracted from the error-correcting code, not reducing correcting ability of the code.The most effective use of adaptive coded frame synchronization in noise-tolerant cascade codes. In this case, synchronization is provided by repetition of signs synchronization in different words internal code cascade code.The main task is to increase the noise immunity of the frame synchronization when operating in non-stationary communication channels with variable parameters and a high level of noise.The known method cyclic synchronize the synchronization sequence, multiplied by the check polynomial error-correcting code as a result providing the synchronization sequence. Upon detection of a certain combination of the selected synchronization sequence shall take the decision on whether frame synchronization [1].However, this method is insufficient immunity.Closest to the proposed method is a method (prototype) code frame synchronization, namely, that the accepted input sequence representing the sum modulo two words cyclic, error-correcting code, numbering and timing sequences, multiplied by the check polynomial of the code. Resulting allocate a sum numbering and timing sequences. Next, the sequence is multiplied by the check polynomial numbering sequence, followed by detection of the synchronizing sequence, and then allocate numbering sequence. Next, define the error vector and carry out the correction of errors in the numbering sequence. Then compare numbering and synchronizing sequence with previously adopted and as a result of comparison oprey synchronizing sequences previously received code words, moreover, if the result of comparison of the number of matches with the threshold value will be exceeded by the number of matches some predetermined threshold value, make a decision about the presence of frame synchronization at the current time. Next, subtract numbering and synchronizing sequence of code words and then perform the decoding code words with the detection and correction of errors [2].The disadvantage of this method is the low immunity due to the fact that in non-stationary channels with a high level of noise will be present a large number of corrupted code words. The reliability of such code words when correcting errors is low. Consideration of these code words in determining whether frame synchronization along with undistorted code words reduces the immunity frame synchronization.The purpose of the invention to increase the noise immunity of the frame synchronization messages due to the fact that the presence of frame synchronization is determined taking into account the quality of the communication channel.To achieve the goal proposed method adaptive code frame synchronization, namely, that the accepted input sequence before the th sequences, multiplied by the check polynomial error-correcting code. As a result, there sum numbering and timing sequences. Next, the sequence is multiplied by the check polynomial numbering sequence, followed by detection of the synchronizing sequence, and then allocate numbering sequence. Next, define the error vector and carry out the correction of errors in the numbering sequence. Then compare numbering and synchronizing sequence with previously adopted and as a result of the comparison determines the number of matches numbering and timing sequences with appropriate numbering and synchronizing sequences previously received code words, and, if the result of comparison of the number of matches with a threshold will be exceeded by the number of hits a certain threshold of matches, take the decision on whether frame synchronization in the current time. Next, subtract numbering and synchronizing sequence of code words and then perform the decoding code words with the detection and correction of errors. What's new is that the number of matches numbering and sinhroniziruete to estimate the total reliability of received code words with matching numbering and timing sequences. In turn, preferably the reliability of the received code words to identify the given weights, the magnitude of which depends on the ratio of corrected code word errors.The implementation of the method of adaptive coded frame synchronization consider the example of synchronization of the cascade code.On the transmission side form input sequence. For this purpose, the transmitting side of the original message volume1m-ary (m >1) characters at the beginning encode m-ary error-correcting code, such as m-ary error-correcting code is a reed-Solomon. A reed-Solomon code is the outer code or code first-stage robust cascade code.In the encoding information is a code word reed-Solomon code (n1, k1), the information length is equal to k1and block - n1characters.Further information code binary code, such as binary Bose - Roy-Chaudhury - Hocquenghem (BCH codes) with the check polynomial h1(x). Code BCH is an internal code or code of the second stage of error-correcting cascade code. Code BCH has parameters: n - block code length, k is the information length of the code.The source information for each slo is the result of the encoding code BCH receive n1binary words BCH code (n, k) or a binary sequence with1.Then perform addition modulo two characters BCH code with symbols numbering sequence2. As the numbering sequence select binary code with block length n and information long2for example code, reed-Muller (RM) 1-th order (sequence maximum period) with the check polynomial h2(x). Between the numbers of words in concatenated BCH code and an information part numbering sequence (code RM) is one-to-one correspondence. The first word BCH is folded sequence obtained by encoding the binary combination corresponding to binary 1, the code of the Republic of Moldova, the second in the encoding code RM - 2, and so on, Such an addition is performed with all the words BCH code. If the check polynomials summable codes h1(x) and h2(x) are coprime and are divisors of binomial xn+1, this will result in n1words cyclic BCH code with block length n and information - k+k2. This code will be quite certain guaranteed minimum code distance and possess the particular BCH, will be constant for all words in the sequence of length n bits that violate the cyclical properties of BCH code. Such a sequence may be any sequence that is not a code word BCH code, for example, a sequence of 10000...000.At the receiving side input sequence, formed as the sum of the three sequences used for adaptive coded frame synchronization.The drawing shows the sequence of operations that illustrates the processing of the input sequence at the receiving side.At the receiving side first carry out a reception of the input sequence.Next, the input sequence is multiplied by the check polynomial error-correcting code h1(x), and then multiply the sequence on the check polynomial numbering sequence - h2(x). Thus, compute the syndrome BCH code or a sequence with1and code of the Republic of Moldova, or a sequence with2.When entering the infallible word syndrome code is zero and the result of the calculation of the syndrome is obtained n-k-k2bit binary combination of the d0corresponding to the converted synchronization posledovatelnyi input words with errors will be calculated combination of some set { di}, i













Claims
Method of adaptive coded frame synchronization, namely, that the accepted input sequence representing the sum modulo two words cyclic error-correcting code, numbering and timing sequences, multiplied by the check polynomial error-correcting code, as a result, allocate a sum numbering and timing sequences, then the sequence is multiplied by the check polynomial numbering sequence, followed by detection of the synchronizing sequence, and then allocate numbering Polke this compare numbering and synchronizing sequence with previously adopted and as a result of the comparison determines the number of matches numbering and timing sequences with appropriate numbering and synchronizing sequences previously received code words, moreover, if the result of comparison of the number of matches with the threshold value will be exceeded by the number of hits a certain threshold, take the decision on whether frame synchronization in the current time and then subtract numbering and synchronizing sequence of code words, wherein the number of matches numbering and timing sequences determined based on the quality of the communication channel, which estimate the total reliability of the received code words with matching numbering and synchronizing sequences, and the reliability of the received code words are determined based on scales, the magnitude of which depends on the ratio of corrected code word errors.
FIELD: digital communications.
SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.
EFFECT: higher reliability, higher effectiveness, higher interference resistance.
1 cl, 3 dwg
FIELD: communications.
SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.
EFFECT: higher trustworthiness.
1 dwg
FIELD: digital communications;
SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.
EFFECT: enlarged functional capabilities.
1 cl, 2 dwg
FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.
SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.
EFFECT: enhanced noise immunity.
1 cl, 1 dwg
FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.
SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.
EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.
1 dwg
FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.
SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.
EFFECT: increased interference resistance of device for cyclic synchronization.
4 dwg
FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.
SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.
EFFECT: expanded functional capabilities of device for cyclic synchronization.
2 cl, 3 dwg
FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.
SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.
EFFECT: increased interference resistance of cyclic synchronization.
2 cl
FIELD: data processing in broadband radio communications and radio navigation.
SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.
EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.
2 cl, 9 dwg
FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.
SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.
EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.
1 cl, 9 dwg