The method of forming electrically conductive and/or three-dimensional semiconductor structures, the method of destruction of these structures and the generator/modulator electric field for use in the method of formation

 

The invention relates to microelectronic technology, in particular to a technology for thin-film electronic circuits. Developed methods of forming electrically conducting and/or semiconducting two-dimensional or three-dimensional structures and their destruction. Designed generator/modulator electric field for use in the method of formation of these structures. The technical result of the invention is the provision of low cost flexible mass production of electrical connections in thin-film structures electronic circuits. 3 S. and 12 C.p. f-crystals, 12 ill.

The invention relates to a method of forming electrically conducting and/or semiconducting two-dimensional or three-dimensional structures in a composite matrix containing one or more materials in a spatially separate and homogenous material structures, and materials in response to the flow of energy can undergo specific physical and/or chemical state changes that cause the transition from electrically non-conductive state to an electrically conducting and/or semiconducting state or Vice versa, or a change in the mode of the electrical conductivity of the material, and each structure is chicheste conducting and/or semiconducting two-dimensional or three-dimensional structures, formed in the composite matrix containing two or more materials in a spatially separate and homogenous structures, materials, materials in response to the flow of energy can undergo specific physical and/or chemical state changes that cause the transition from electrically non-conductive state to an electrically conducting and/or semiconducting state or Vice versa, or a change in the mode of the electrical conductivity of the material, and each material structure made in the form of a thin layer.

In addition, the invention relates to a generator/modulator electric field (GMAP) for structuring and formation of electrically conducting and/or semiconducting two-dimensional or three-dimensional structures in the composite matrix, and the matrix contains two or more materials in a spatially separate and homogenous structural materials, materials in response to the flow of energy can undergo specific physical and/or chemical state changes that cause the transition from electrically non-conductive state to an electrically conducting and/or semiconducting state or Vice versa, or a change in the electric mode provodimostei the invention relates to the production of two-dimensional and three-dimensional insulating, resistive, conductive and/or semi-conductor configurations and structures for use in electronic circuits, which consist of one or more layers of thin films.

The development of microelectronic technology shows a stable trend towards smaller sizes and lower cost devices. It is quite reasonable forecast shows that the performance will improve, while the price of the unit or device will be reduced. However, the current microelectronic technology is based essentially on crystalline silicon and exhibits an increasing tendency to reduce recoil, mainly due to limitations associated with the complexity of the super-resolution lithography and increasing demands for processing materials. Extrapolation of existing technologies based on crystalline silicon, may not presage a dramatic breakthroughs in both the characteristics and rates, and future improvements will require very capital-intensive production facilities and production equipment.

On the other hand, with high probability we can assume that microelectronics technology-based thin films in the near future will ensure the establishment clause is istoricheskikh inorganic semiconductors to microcrystalline, polycrystalline or amorphous inorganic or organic semiconductors introduces a completely new boundary conditions for microelectronic technologies, and in particular, due to the possibility of using blanks, with coefficients of the form corresponding to large areas, i.e., the substrate can be a large plate instead of plates cut from blanks of limited size, as well as greater flexibility in the architecture, which can be a significant factor in the expected development of modern electronic technology. In the present invention, particular emphasis will be placed on the use of organic materials due to the ease of processing due to the possibility of using a large area and multi-layer boards with well-controlled thickness, as well as due to their great potential for creating chemical methods materials with desired properties.

In particular, before the use of electronics-based amorphous materials, will be able to realize its expected potential, additional improvements in certain areas. In recent years, efforts have been made to improve semiconductor properties the characteristics of the transistor to the extent when transistors based on organic can compete with transistors based on amorphous silicon (see, for example, Y. Y. Lin, D. J. Gundlach, S. F. Nelson, and T. N. Jackson, "Pentacene-Based Organic Thin Film Transistors", IEEE Transactions on Electron Devices, August 1997). Other developments aimed at creating methods for applying thin-film coatings in order to create semiconductors made of organic material or an amorphous silicon at low temperatures, having compatibility with a wide range of organic and inorganic substrate materials. This has led to the development of very cheap electronic devices with large squares-based methods for large-scale production.

Despite this technology is still not fully satisfactory solution which would allow to adapt the production technology for providing low-cost flexible large-scale production of electrical connections in thin-film structures, forming an electronic circuit. Currently, thin-film devices based on amorphous silicon and executed with conductive tracks and guides, made according to the pattern of traditional methods such as lithography and vacuum metallic and organic basis (see for example, A. R. Brown & al. "Logic gates made from polymer transistors and their use of ring oscillators". Science 270:972-974 (1995)). An alternative used screen printing with a conductive ink for the manufacture of transistors on flexible polymeric substrates (see, for example, F. Garnier & al., "All-polymer field-effect transistor realized by printing techniques". Science 265:1884-1886 (1994). Although lithography can provide high resolution, it is relatively complex and usually includes a liquid chemical processing, which is undesirable in large-scale production of multi-layer organic thin-film structures. Screen printing ink is also far from ideal because it provides the resolution of minor to moderate with all the disadvantages of liquid chemical processing.

As an example, a known method may be mentioned U.S. patent 5043251, which describes the way a three-dimensional lithography amorphous polymers to create short-permanent structure in the polymer material, comprising the steps of providing doped noncrystalline layers or films of a polymer in a stable amorphous state in the terms of use of manual operations. In the production structures of the film is masked optical and POCs, so in the film formed a distinct three-dimensional imprint. This method, among others, have been proposed for use in the manufacture of the optical disk for data storage. In addition, the U.S. patent 5378916 known photosensitive device in the form of a single-crystal structure in which different parts of the structure can have a different composition. In particular, this structure forms a two-dimensional array, and the first photosensitive site contains material, which creates electron-hole pairs when exposed to light within a predetermined first wavelength range, while the other photosensitive area contains material that provides for the creation of electron-hole pairs when exposed to light in a different wavelength range, sufficiently different from the first wavelength range. In addition, the U.S. patent 5677041, which naiblizhajshee analogous to the claimed invention, known transistor device is fabricated by forming a doped layer sensitive to radiation of the material on the substrate. Sensitive to radiation material can be, among others, a polyimide, a polymer, an organic insulator, conductor or palliated. Neutral or non-alloy layer other sensitive to radiation material is formed on the doped layer. The first and the second region of the source/drain are then formed in the neutral layer and extend to the top of the doped layer. The area of the shutter is formed in the upper part of the neutral layer between the first region of the source/drain and the second source/drain so that the channel region in the doped layer is provided below the shutter. The electrodes of the source/drain and gate are formed by irradiation of the upper neutral layer through the mask, which is structured in accordance with the desired structure of the electrode and implemented so that it modulates the intensity of the radiation. In addition, the mask may be implemented as a phase-shifting mask.

Known field MOS transistor (field effect transistor metal-insulator-semiconductor), fully implemented in the polymer and polymeric materials, which given the desired electrical properties by exposure to ultraviolet (UV) irradiation (see "Polymeric integrated circuits and light-emitting diodes", D. M. de Leeuw & al., IEDM, pages 331-336 (1997)). Used in the production of photochemical structuring doped electrastar, then to the solution is added photoinitiator, which was deposited on an appropriate substrate, such as polyimide film. By subsequent deep exposure PANI film to UV radiation through a mask initially conductive polyaniline converted in the irradiated areas in a non-conductive leucoemeraldine form. The starting point here is, respectively, conductive polymer material, the surface resistance of which is initially equal to 1 kOhm/square, but after the exposure of its surface resistance is more than 1013Ohms/square. Thus can be created in the dielectric structure in the matrices, which otherwise are conductive. Fig.1 shows a field MOS transistor described in the work Leeuw & al., containing polyimide substrate 1 with PANI thin film, which after exposure to UV radiation through the respective mask forms an insulating structure 6 in the thin-film material 3, which otherwise is conductive. The remaining conductive region 3 in the PANI film is determined correspondingly to the electrodes of the source and drain of the field MPD transistor. On top of the PANI film is deposited additional layer 4 in the form of a thin film of politionele electrical field MPD transistor. Film 5 from polyvinyldene (PVP), which forms the gate insulator of the transistor and impervious to UV radiation and visible light, is deposited on PTV film 4. Another PANI film is again deposited on top of the PTV film 5 and exposed to UV radiation through a pattern for forming isolation structures 6. The remaining electrically conductive region 2 forms a gate electrode structure field MPD transistor.

If several of the aforementioned type transistors should be combined in integrated circuits, made in the form of multilayer film structures, you should use vertical conductive paths, for example, between the electrodes of the source and drain of one transistor and the gate electrode in the other transistor. Such vertical conductive paths can be implemented mechanically, for example by deposition of a metallic film on top of the vertically etched steps in the structure. Another similar solution is to use plated through holes in circuit boards for the implementation of vertical connections between conductive paths on the upper and lower side of the circuit Board.

The present invention is si microelectronic devices with large surfaces on flexible substrates, using processes that are characterized by large-scale production at low cost. In particular, the present invention is the creation of methods of manufacturing multilayer physical devices, for example in the form of a large number of adjacent superimposed one upon the other thin-film layers forming a three-dimensional structure of the schemes. The present invention thus provides flexibility and efficiency, and at the same time simple and high precision manufacturing devices such as a flat display, logic circuits, memory devices, etc.,

Also the present invention is to provide a method for destruction of such a three-dimensional circuit structures, so that the material in the structures were transformed back to the initial state, after which it by means of a suitable method can be reconfigured in the form of electrically conductive and/or three-dimensional semiconductor structures, but, for example, with a different configuration, different from the original.

The above features and advantages are realized according to the present invention, the manner in which the application to the individual layers of the electric field with a given field strength CIA in each case, the fields in space in accordance with a specific Protocol, representing the predetermined configuration of the electrically conducting and/or semiconducting structures in the material structure, whereby the layers in accordance with the applied field energy generated two-dimensional electrically conducting and/or semiconducting structures with the configuration defined by the Protocol, and then additional ordering two or more layers by laying on each other to obtain a composite matrix formed separate adjacent layers of conductive and/or three-dimensional semiconductor structures.

In addition, in accordance with the invention advantageous that the electric field is preferably modulated spatially in a plane substantially parallel to the layer through the electrode device with structured electrodes, and the electrode device by selective supply voltage to the electrodes according to a specific Protocol generates electrical point or line potentials that form the electrically conducting and/or semiconducting structures.

In accordance with the invention, it is preferable that the multi-layer configuration formed by two or Bunyan in layered multilayer structure, which form an integral matrix with conductive and/or three-dimensional semiconductor structures.

In accordance with the invention, also preferred is the positioning of a multilayer structure formed by addition of two or more mutually supportive layers in the folded configuration. Layer after applying the neighboring layers are then preferably located such that the two or more two-dimensional electrically conducting and/or semiconducting structures in the first-mentioned layer according to the Protocol coincided with the one or more two-dimensional electrically conducting and/or semiconducting structures in the adjacent layers, which creates one or more vertical conductive and/or semiconductive channels, passing in the transverse direction through the layers.

In addition, in accordance with the invention, it is preferable that the electrically conductive and/or semiconductive structure forms a vertical channel through the layer according to the Protocol in conducting and/or semiconducting compound with one or more two-dimensional electrically conducting and/or semiconducting structures in this layer, each channel preferably is created with PR the IOM conductivity, which vary from layer to layer.

The way the complete destruction of patterns formed in accordance with the present invention differs in that it is a global application to matrix composite electric field with a given field strength and/or characteristics corresponding to the specific response of a material to the energy provided by the field up until the materials in the composite matrix in accordance with the energy, provided the field is not completely made of electrically non-conductive state.

Generator/modulator electric field according to the present invention differs in that it contains the first electrode means of parallel strip electrodes placed in the plane, the second electrode means of parallel strip electrodes placed at a distance from the first electrode means and imposed on him a second plane parallel to the first plane, so that the electrodes are substantially mutually orthogonal oriented in the matrix in such a configuration, the electrode means through the switching devices are connected to a controlled power source and the generator/modulator e is the Rial in the form of a discrete component or a continuous belt, without contact with the electrode means continuously or intermittently fed through the space with simultaneous positioning and alignment relative to the electrode means and between them in a plane substantially parallel to them, thanks to which can be formed from conductive and/or semi-conductor structure according to a specific Protocol and through a point, line, or plane potentials generated between the selected electrodes in the electrode means when the first switching devices is supplied electrical energy. Preferably the electrodes in each electrode means placed on the surface or surfaces of the respective substrates, facing each other, and/or the connection is preferably performed as part of the substrate, and forming conductive patterns in the substrate material.

In accordance with the invention, it is preferable that the distance between the electrode means may vary depending on the thickness of the thin-film material.

Also in accordance with the invention, it is preferable that the electrodes in each electrode means placed at a distance from each other from 0.1 to 1.0 μm, and that the electrodes in each of the I in the following examples of its implementation, illustrated by the drawings, which show the following: Fig. 1 - field MPD-transistor with electrodes formed from a material with the properties of the photoelectric conversion according to the prior art, Fig. 2A, b is a schematic representation in cross-section and top view of the generator/modulator electric field (GMAP) corresponding to the invention, and its use in the first stage of the formation method corresponding to the invention, Fig.2C, d is a schematic representation in cross-section and top-view GMAP in Fig. 2A, b, used in the second stage of the formation method corresponding to the invention, Fig.2E, f is a schematic representation in cross-section and top-view GMAP in Fig. 2A, b, used in the third stage of the formation method corresponding to the invention, Fig. 3 is a schematic illustration of the formation method corresponding to the invention, including the addition of the individual layers in a multilayer structure, Fig. 4 - section multi-layer structure with conductive and/or semiconductive structures created on the stages illustrated in Fig.2A-f, Fig. 5 is a cross - section composed of a multilayer structure, which includes conducting and/or semiconducting structures storeroom, relevant to the present invention, Fig. 7 is a cross - section structure of the MOS transistor formed in a way consistent with the present invention,
Fig. 8 is a cross - section of the logical structure of the inverter based on the structure of the MOSFET according to Fig.7, formed in a way consistent with the present invention,
Fig. 9 is an equivalent circuit logic And implemented in CMOS technology,
Fig. 10A-d is a top view of subsoil in the structure of the logic circuit And formed according to the invention, according to the equivalent circuit in Fig. 8 using the structures of the MOS transistor, as shown in Fig.7,
Fig. 11 - the structure of the logic circuit, And Fig.10 in a multilayer configuration, shown with division into separate subkey,
Fig.12 is another variation of the structure of the logic circuit, And Fig.10 and with individual structures of the MOS transistors mutually connected in a vertical configuration.

The following describes the basic principles of the method according to the present invention, with which three-dimensional structures with well-defined regime and the degree of electrical conductivity are formed by spatially controlled structure in place conversions is obratimym way under the action of irradiation, heating or electric fields. The method of formation of such structures in accordance with the present invention is based on the use of electric fields, or fields DC fields or alternating current. First three-dimensional electrically conducting and/or semiconducting structures can be created in the form of two-dimensional structures of this type by direct local impact of electric field on one layer, and then the three-dimensional structure is formed by combining the individual layers in a multilayer structure. Typically converted by the electric field of the material (PAPM) is an organic material, such as a molecule, oligomer or polymer, where the phase transition from a source state to a new second state occurs when the influence of an electric field, for example, a given field strength or frequency. As indicated below, it is assumed that the most important change occurring in the transition from the first to the second state, is the degree of electrical conductivity. The method of formation and destruction of electrically conducting and/or semiconducting structures by electric fields will be discussed below with reference to the drawings.

For Paulista in two States reach 1010. In this case relates to the conversion in place of one layer to be converted under the action of irradiation of the material from the conducting to a nonconducting condition for forming electrical connections in a single electronic circuit. Electrically conductive connection in doped polianilinovyh films (PANI films) are determined by exposure to deep UV radiation through a mask pattern.

Multi-layered set of different transform under the action of the electric field can be created on the substrate, which may be flexible or rigid, conductive or non-conductive. Convert field materials are made conductive, semi-conductive or insulating in desired configurations by affecting several single-layer transform the field of materials spatially controlled electric fields and with the subsequent combination of layers in a multilayer set. Multi-layered sets of converted field materials are of particular interest in connection with multilayer thin-film circuits where you want to create conductive lines, conductive paths connecting points or electrodes in several layers so that the conductive structures in a single layer of them is use or below. One example is a thin-film field-effect transistors (TPPT), in which the electrodes of the source and drain layer must be positioned correctly relative to the gate electrode and located between the insulating and semiconductor layers. Another example is the electrical connection between the layers, where traditional solutions in many cases are unsatisfactory, for example, through the implementation of several stages, such as the formation of open channels or through-interconnects between suitable points, which will then be electrically connected in various layers, with corresponding filling or coating of the channels of a conductive material so as it happens when using through-plated holes in the circuit boards for connection with the front to the back side of the circuit Board. A third example is the manufacture of capacitors by defining conductive regions, which are mutually aligned opposite each other in two layers separated by an insulating layer. Obviously that is not only well-conductive but resistive and insulating and semiconductor configuration in multilayer structures are of great importance. As will be explained in more adolescents and/or semiconductor structures or configurations according to the present invention. For clarity, first defined configuration and three-dimensional structures that are very good or very poor electrical conductors.

Multilayer structure, such as described here, are of particular interest when they are integrated with thin-film semiconductors to form the complete schema. Standard procedures currently used for the production of microelectronic circuits, which use semiconductor properties of ordinary silicon substrate, automatically limit the implemented architecture of such a form that provides access to the substrate for all active devices. If you have to create electrically conductive and/or three-dimensional semiconductor structures used method corresponding to the present invention, by being converted superimposed on each single layer, the device as a whole can be created in this way without any significant restrictions on the size or complexity, because the increase is simply by joining a set of additional layers. Because each layer can be made thin, for example with a size of about 10-100 nm, the resulting bulk density for structures schemes and realizowane hybrid architecture using layers, which include convertible field of the electronic structure, which are formed over traditional electronic circuits based on silicon and working together with them.

Main objective of the present invention is to provide a conductive, semiconductive, and/or resistive three-dimensional structures in multilayer material in a monolithic format using electric fields in the form of point, line, or surface potentials. The implementation of the declared method of formation using electric fields is described below with reference to Fig.2A-f.

Fig.2A shows a cross-section of the generator/modulator electric field, made according to the invention, functioning as the electric structure for converting the electric field of materials. Generator/modulator electric field is made so that it generates a field, and also modulates these fields of space, i.e. in the plane or in two dimensions, and creates a conducting and/or semiconducting structures with the desired configuration in this plane. Generator/modulator electric field (GMAP) 20 includes, as shown in Fig.2A in cross section and in Fig. 2b in the form of zverstva E2, far removed from the electrode means E1 in a plane parallel to him. Electrode means E2 similarly consists of thin parallel electrodes 22 that are installed so that they are oriented substantially orthogonal to the electrodes 21 in the electrode means E1. The electrode means E1, E2 are connected to a power source 23, shown in the form of a constant current source, but the power source 23 can also be a source of alternating current. The power source 23 is connected to the electrode 21, 22 in the electrode means E1, E2 through the respective switching devices 25, 24. The distance between the electrode means E1, E2 allow you to enter the thin film is converted by the electric field of the material (PEPM), shown in Fig.2A as SS1, between the electrode means E1, E2 without contact with them. The electrode means E1, E2 can be performed as a self-supported or supported thin films, in which the electrodes 21, 22 in each case introduced into the film material. It is also clear that the layer SS1 field convertible material may be a continuous strip, which is inserted into PAPM 20 between the electrode means E1, E2 with a substantially continuous movement. By application of the voltage, i.e. the second field, perpendicular to the layer SS1 in the intersection between the electrodes 21 and 22, and convert the material field SS1 can be converted from a non-conductive state to a conductive state in the areas that impact the field between the electrodes 21, 22. If the electrode 21 and the other electrode 22 are addressed electric, the intersection between them is formed approximately pitting potential. If, for example, addressed the electrode 21 in the electrode means E1 and all the electrodes 22 in the electrode means E2, the field is essentially in the form of linear potential along the considered electrode 21, and accordingly will be created linear, for example, electrically conductive structure in the layer SS1, which is located between the electrode means E1, E2. If addressed to multiple electrodes 21, which are located next to each other in the electrode means E1, and accordingly many of electrodes 22, which are located next to each other in the electrode means E2, the field that will be created between the intersections of the electrodes, to form a surface potential and will ensure the formation of surface patterns in the layer SS1. In Fig. 2A, 2b such conductive patterns created, for example, in the form of surface sciotti from how is the electric field.

Fig.2C and 2d show respectively in cross section and top view, as is GMAP 20 for forming, for example, conductive structures 9 in the second layer by appropriate addressing electrode means E1, E2 in GMAP 20. Accordingly, in Fig.2E, f in cross section and the top view shows GMAP 20 with the third layer SS3, which is structured with a semiconductor structures 10. As shown in Fig.2a-f, the structuring of the converted field of material takes place for each individual layer SS1, SS2, SS3, but these layers may, as mentioned above, to be presented in the form of a self-sustaining individual films from PAPM and arranged in a layered set, as schematically shown in Fig.3. The production of circuits formed electrically conducting and/or semiconducting structures in PAPM may be carried out using tapes from PEPM in continuous lines, as shown in the drawing. Appropriate tape or film shown in Fig.3 as three films PAPM, PAPM, PAPM. They are converted by the electric field with the formation of the desired spatial structure in a separate GMAP 20 for each line. Then it should build in a multilayer structure MCC, for example, by sleeve rhaesa the influence of an electric field, but it is entered in a multilayer structure on the same stage of manufacture. In each case the result is a flexible tape MSS, which can be either folded, or folded, or cut into segments, for example, for individual schemes. In Fig.3 convert the material field in the form of three tapes or films PAPM, PAPM, PAPM extracted from the respective rollers Raand sent on separate lines in the leveling rollersb1, Rb2, Rb3, Rb4in each line for tensioning and positioning of the tape in GMAP 20. Received structured film PAPM, PAPM, PAPM fed through a set of guide rollers Rcand perhaps after additional adjustment are in the stage of blending Rdand formed into a multilayer structure MCC. This multilayer structure can, as mentioned, to enable the substrate 1, which stretches from additional videoandin a separate line and is folded together with the material to be converted film PAPM on stage blending Rd. For three layers, which are added together in such a way and is converted, as shown in 2a-f, then, as schematically shown in cross section in Fig.4, can be obtained circuit structure on the substrate 1. Provencale in each of the layers SS1, SS2, SS3, as shown, and together form a three-dimensional structure in a desired configuration.

The electrode means E1, E2 in the oscillator/modulator electric field (GMAP 20), for example, shown in Fig.2A and Fig.2b, may be formed in the substrates or on substrates made of non-conductive material, and the electrodes 21, 22 can then be created on the opposite surfaces of the substrate or introduced into the substrate. They may also form
the conductive structures in the substrate material. The width of the electrode and the mutual distance between the electrodes 21, 22 in each electrode means E1, E2 will be determined taking into account the spatial resolution of the structuring of conducting and/or semiconducting structures and technologically achievable tracks. In accordance with modern semiconductor technology, the electrodes 21, 22 can be implemented with a width of from 0.1 to 1.0 μm and the corresponding mutual distances. Modern technology allows the width of the electrodes, for example, in thin films, created on the substrate, of about 0.1 μm or less by using nanotechnology methods, for example by a printing method, or chemical methods. Circuit configuration to be realized through GMAP 20 is but can be implemented using, for example, microlithography in circuit technology based on silicon. Depending on the material thickness of a thin film, which should be created by conducting and/or semiconducting structures, i.e., circuit configuration, the distance between the electrode means E1, E2 can be controlled for optimum determination of the potentials between the electrodes. Management can be performed through micromechanical tool servo (not shown), as known to experts in this field of technology. When creating a circuit structures, the space between the electrodes may be additionally filled with an insulating gas having a high dielectric strength to prevent breakdown between the electrodes.

As has been demonstrated when using materials with which it is possible to implement field induced transformation, the latter can be performed with a high degree of reproducibility when exactly a particular field strength. Typically, the field strength required for the implementation of the conversion will be about 5000000/m, creating a potential difference at the electrode means E1, E2 of the order of 3-6 volts of film thickness in the range of 200-300 nm and a gap between the electrode of the medium is applied essentially in the direction perpendicular thin film, although in principle it can be applied in other directions. The first option is preferable from the point of view of the required accuracy in the spatial resolution, as well as obtain precisely defined field strength.

The power source 23 in GMAP 20, for example, as shown in Fig.2A and 2b, may be either a DC source or an AC source. Preferably it is in the form of a controlled power source and supplying to the electrode means E1, E2 current with different modes and characteristics. To this end, the power source 23 and the tools 24, 25 switching connected to an external control device (not shown), which may be programmed accordingly to obtain the desired circuit patterns and the corresponding control formation of the desired electrically conducting and/or semiconducting structures in layered material or material of a thin film between the electrode means E1, E2. The protocols and the required software can be loaded into the control unit (not shown) from any external source and, thus, there is nothing that would prevent what are considered to be converted by the electric field materials which can be used in the method corresponding to the present invention, as well as technology that can be used when implementing the method. The basic principle of conversion field on site materials is to create a conducting and/or semiconducting structures by spatially modulated and/or modulated field strength electric fields. Transform can also be reversible or irreversible. Specific examples of this will be given below. It should be noted that PAPM are currently at an early stage of development and it is expected that the upcoming research and development in this area will significantly increase the number of available materials.

In the present invention is particularly preferably used PAPM that under the influence of electric fields retain their status until such time as they again will not be subjected to such a field, which puts the material back to its original state. This, among other things, takes place in a variety of organic macromolecules and other materials, which are known as molecular electronic materials (see, for example, "A new material for optical, e is integrated connection charge-transfer (M(TCNQ)), educated 7,7,8,8-tetracyanoquinodimethane C12H4N4which functions as a molecule acceptor of electrons with different metals as enriched electron donors. The metal may be Li, Na, K, BP, si, or Fe. M(TCNQ) may, at the application of electric fields, and when the flow of energy in the form of heat or light radiation, to pass from a state of high impedance to low impedance. In General, the reaction can be written as follows:
[M+(TCNQ)-]n_hv,E_Mx+(TCNQ)x+[M+(TCNQ)-]n-x.
The process is reversible, because the reverse reaction can be obtained by applying energyin the form of heat, electric field or photon irradiation. Reversible reaction leads to the fact that M(TCNQ) can be used to create a switching environment with two stable States, such as material erasable memory. In the method corresponding to the present invention uses only the electric field, but not the exposure. In thin layers, for example 100-200 nm, M(TCNQ) has a non-linear volt-ampere features the th purpose of a special interest, that M(TCNQ) provides a stable and reproducible controlled current electrical switch with two stable States. Electrically addressable memory, for example, the state of high impedance can be used to represent binary "1" and the condition of low impedance, a binary "0". The transition between two such States is less than 400 NS. Additional examples of suitable materials are described in the work of W. Xu & al., "Two new all-organic complexes with electrical bistable states", Appl. Phys. Lett. 67:2241-2242 (1995). The above-mentioned bistable materials and have clearly defined boundaries convert from a conducting state to a nonconducting state and Vice versa, using electric fields.

In certain transformed the field of materials, including TCNQ, the conversion from a non-conductive state to a conductive state can also occur under the influence of energy in the form of heat. Because field convertible material is typically a dielectric or has a large resistance, AC electric fields, which, by means of electrodes applied with appropriate frequency to the material, may generate heat capacity, and then in this area can occur lagravanese to act as a source of alternating current, and thermal conversion should be considered as a secondary effect, due to the electric field. To get a good spatial definition is made conductive and/or semiconductive structures, thermal field generated by the alternating current field in the material must be accurately controlled. Thermal field can propagate in the material and cause a temperature increase, which can affect the electrical properties of the material outside the scope of potential, which in the ideal case should define the spatial area of the framework. If the converted field material is treated as an infinite thin layer, the temperature rise will be felt, for example, on the distance from a point potential, which coincides with the point of intersection of the activated electrodes with a length of thermal diffusion, which is determined by the formula
= (k/fc)1/2, (1)
where k is thermal conductivity;
f= 1/the characteristic frequency, which is approximately equal to the inverse value of the pulse duration;
the density of the material;
you and get a clear spatial definition of the desired electrically conducting and/or semiconducting structures, should be used a pulse AC, which provides high field strength and a rapid temperature rise in capacity followed by rapid conversion of the material to be converted by the electric field. This can be achieved by combining a high intensity field with a high frequency field and using the converted field of materials in the form of thin films with a thickness of 100 nm. It is assumed that unwanted heat diffusion can be effectively avoided by the use of pulses of alternating current is not more than a few microseconds. In this regard, characteristics of the field must also be set to the required degree of conductivity in the areas of capacity building, which is theoretically generated by conducting and/or semiconducting structures.

Electrical connections between different layers in thin film materials or other types of electronic materials represent a major problem in the production of microelectronic components. The accurate positioning of the conductive paths in the plane of each layer in the perpendicular direction to the plane of paramount importance and typically includes the formation of end-to-end misued the molecular layers. Physical fabrication of holes according to known techniques is by drilling, punching or etching, and a conductive material is added to the mechanical filling, electrolytic deposition, etc., it is Clear that processes of this type are quite complex and expensive and, in addition, have limitations in accuracy.

In the present invention compounds, as well as active and passive devices, can be created in the same sequence processing, which determines the electrically conducting and/or semiconducting structures in each layer, i.e., with the same degree of spatial accuracy as the original structure, and without the use of additional and other stages of production. Fig.5 shows the basic principle for a particular case, the creation of one of the conductive paths between the part 9, for example, conductive patterns in the layer SS5 and part of another conductive patterns 9 in the layer SS8, remote from the first. By re-converting the small square in the same location of each of several adjacent layers between the endpoints of conducting and/or semiconducting structures, formed column 9' of conductive material, as shown in Fig. 5, and the electrical conductivity, polucha contains the second conductive structure. The cross-section of the column 9' can be freely defined by the selected template of the electric field. Several parallel conductive columns can be created by direct spread of this procedure, and columns can begin and end in different layers, as is clear from Fig.5. In this layer, which includes a conductive structure 9 in combination with one or more conductive bars vertical conductive structures 9', the latter shall be made together with other 9 conductive and/or semiconductive structures 10, which is structured in this layer, for example SS6 in Fig.5, i.e., without the need for other or different processing stages. Usually, the degree of conversion from non-conducting to the conducting state or Vice versa can be controlled using the field strength and/or temporal characteristics, and possibly the duration field. Thus, the column that connects the points in two different layers, can be formed so that it functions as a resistor in the circuit, by selecting the degree of conductivity in the segments from layer to layer along the column.

Method of destruction of electrically conductive and/or semiconductive technodrive patterns in separate layers can be selectively destroyed using GMAP 20, as shown in any of Fig.2A-f, and a suitable spectral modulation. After connection of the individual layers in a multilayer structure MCC destruction can only be done globally in the multi-layer structure, if the matrix as a whole is exposed to the electric field with the field strength and/or characteristics, and, perhaps, appropriate to the response of a material to the energy created field. The materials in the matrix can then be re-converted, while the matrix is not fully go into electrically non-conductive state if, for example, it is made from a material, such as M(TCNQ). Multilayer structure or matrix of the material M(TCNQ) can then be reconfigured to produce a new conductive and/or semi-conductor structure, but currently this is not possible using electric fields. However, it can be used in the formation method described in co-filed international application PCT/NR 99/00023 the same applicant.

As the formation method according to the present invention provides the possibility that suitable materials can be converted from insulating to semiconducting state is spent by local heating), this method can be applied in the production of, for example, diodes and transistors, which can be electrically connected to the resistors and capacitors for the formation of fully active electronic circuits. More specific examples of active components and circuits made from these elements, described in the following examples.

EXAMPLE 1
In Fig.6 shows a diode with pramosone P And the transition from conductive and/or semiconductive structures formed by the method according to the invention, and implemented by thin-film technology with four subclone SS1-SS4. Layers SS2 and SS3 contain active semiconductor material between the electrodes 11 in the respective sultload SS1 and SS4. The active material 10 in subtle SS2 represents doped donor impurity semiconductor, while the adjacent active material 10' subtle SS3 represents doped with an acceptor impurity semiconductor. The electrodes 11 in layers SS1 and SS4 are in contact with the horizontal conductive structures or conductive tracks 9 in the same layer. A separate layer in the diode structure of Fig. 6 typically has a thickness of approximately 100 nm, so that the entire structure forms a multilayer structure with thickness less than 1 μm. The mountains of the spine, which is implemented using GMAP, but with the electrode means E1, E2, as shown in Fig.2A-f, it is possible to form the electrodes 21, 22 on the steps of the order of magnitude of 0.2-1.0 μm usual lithography or by using converted by irradiation of the materials and method described in the aforementioned international application PCT/NO 99/00023. In addition, special printing methods or use of nanotechnology and chemical methods allow you to implement electrode structures with dimensions smaller by an order of magnitude. It can be assumed that when the available technologies for the manufacture of electrode means it is possible to spatially modulate a point and linear potentials in two dimensions to the smallest length of 0.1 μm.

EXAMPLE 2
Field MOS transistor
Fig. 7 schematically shows a field MOS transistor for use in the present invention and implemented entirely of organic material in thin-film technology. The gate electrode 12 is provided in subtle SS1 and connected to the horizontal conductive structure 9, while subslot SS2 is the gate insulator 13. The active semiconductor material 10 is provided in subtle SS3 and combined with the electrode sat the conductive structures 9 in the same layer. Each layer contains or conductive and/or semiconductive structure as the dielectric region. The thickness of the MOS transistor of this type may be 1/2 μm, while the length in the horizontal plane, implemented on modern technology, will be from several microns to less than 1 μm (see example 1).

EXAMPLE 3
Logic CMOS inverter
The structure of the MOS transistor shown in Fig.7, can be used in logic circuits, for example in a logical inverter, made by CMOS technology, as shown in Fig.8. The inverter of this type is formed by parallel connection of the electrodes of the drain and source respectively in the n-MOS transistor and p-MOS transistor connected in cascade configuration with a common gate electrode. For this purpose, is formed a vertical conductive structure 15, which passes through all subsoi SS1-SS7 and connecting electrodes 14'. The output signal from the inverter is applied to this conductive structure 15 to the horizontal connecting structure 9, as shown in the left part of the drawing. The common electrode of the shutter 12 MOS transistor receives the input signal through the horizontal conductive structure is m, while the horizontal length of the inverter has the same dimensions as above when considering the structure of the MOS transistor in Fig.7.

EXAMPLE 4
CMOS logic circuit, And
Active components, such as the structure of the MOS transistor shown in Fig.7, can be used to form integrated circuits by imposing subsoil with structures that have the required electrical properties and fully implemented by the organic thin-film technology. In particular, the following example relates to logic And implemented in CMOS technology using a transistor structure, as shown in Fig. 7. To explain how the active devices such as field effect transistors, can be combined in multilayer structures in functional devices, such as logic circuits, the link is given in Fig. 9, which shows the logic diagram And implemented in complementary MOS technology (CMOS technology). CMOS logic And is implemented using n-MOS field-effect transistors and p-MOS field-effect transistors enriched type as the switching devices. Two input signal a and b are given correspondingly to the gate electrodes of the p-the data signal a and b have a high level, outputwill have a low level. In this case, the transistors Q3and Q4will be included, and the p-MOS transistors Q1and Q2will be switched off, i.e. no current flows, and the output signal isit will therefore be low. On the contrary, if any of the input signals a or b is low, or both signals low, respectively, the p-MOS transistors Q1and Q2will be enabled, and the output signal isbecomes high, while either or both of the series-connected p-MOS transistors Q3, Q4off, and no current flows. Devices Q1, Q2, Q3, Q4implement logic NOT, AND for the implementation of the logic circuit And connect the output of the logic circuit is NOT-AND with a logical inverter, which is also implemented in CMOS technology, respectively, using p-MOS key Q2and n-MOS key Q6connected in parallel. This is a standard CMOS inverter, and if the input signal ishas a high level, the output X will be inverted signal of the input signaland so to have n the same signal X, and this corresponds to the case when the input signals a and b of the logical circuit is NOT-AND both have a high level. In other words, it is clear that the pattern shown in Fig.9 implements logic And, and specialists in the art clear how this can be implemented by a logic circuit OR, and NOT OR with any number of inputs. However, in principle, all Boolean functions can be implemented in combinations of one type of logic circuit and one or more inverters implemented in CMOS technology, for example using the structure of the transistor, as shown in Fig.7.

Purely practically logic And can be performed on thin-film technology, as shown in Fig.10A-10d using structures of the field MOS transistor corresponding to the shown in Fig.7. Fig.10a-10d show the logical schema And implemented by thin-film technology, and active and passive devices, provided in four sultload SS1, SS3-SS5. First subslot SS1 (Fig.10A) contains the gate electrodes g1-g6where the subscript indicates the corresponding index for the MOS transistor Q1-Q6in Fig. 9. The input signals a and b are given correspondingly to the electrodes of the gates g1that is estwenno electrodes paddles5, g6the inverter is connected to the horizontal current path 9. The vertical conductive structure is denoted by 15, and the symbolshows that it extends upward in the vertical direction from subslot SS1. In Fig.10b symbolsandshow that the vertical conductive structure 15 in the layer SS3 extends vertically through this layer and both sides of it. Layer SS3 contains the region of active semiconductor material b1-b6(10 in Fig. 7), which correspond to the gate electrodes g1-g6in the layer SS1 and coincide with them. It should be noted that the layer SS2 exclusively, except for the vertical conductive structure 15 extending through subsoil in both sides of it, consists of a dielectric material, which forms a common gate insulator for field MOSFETs Q1-Q6implementing logic And. Layer SS2 is located between SS1 and SS3 (not shown). Layer SS4 in Fig.10C deposited on top of and next to the layer SS3 and contains respectively the electrodes of the origins of s1-s6and the electrodes are drains d1-d6for the corresponding field of the MOS transistor Q is here the hatch lines. A vertical conductive path 15 also extends through the layer of SS4 and both sides of it and in contact with the horizontal conductive track 9 subslot SS5, as shown in Fig.10d. This horizontal conductive path corresponds to the connection between the electrodes drains d2and d3for the corresponding field of the MOS transistors Q2, Q3and additionally also connected to the drain electrode d1for Q1. Another horizontal conductive track 9 implements a serial connection between the source electrode s3for QCand the drain electrode d4for Q4. The electrodes of the origins of s4and s6grounded through additional horizontal conductive patterns 9, while on the horizontal conductive structure 9, the farthest to the right in the layer SS5, voltage Vddand it connects the source electrodes s1, s2, s5respectively, with Q1, Q2and Q5. Additional horizontal current path 9, the top of Fig.10A, forms a parallel connection between the electrodes drains d5d6for Q5, Q6and the output line indicated by X. the Output signal is2(128 μm2). The volume of the structure, therefore, will be equal to about 75 μm3. At a moderate spatial resolution, this corresponds to about 10,000 logic circuits of this type can be implemented in an area of 1 mm2and with thickness much less than 1 μm. At the proper scale length of the current paths 9, 15 together is 60 μm.

EXAMPLE 5
Logic And combined with the vertical CMOS circuits
Reducing the length of the current paths and a significant simplification of the structure of the logic circuit And can be achieved by imposing structures of the MOS transistor on vertia the structure of the logic circuit And uses the fact that the gate electrodes g1and g3transistors Q1, Q3are under the same common potential, the gate electrodes g2and g4in the Q2, Q4another common potential, and the gate electrodes g5and g6in the Q5, Q6under a third common potential. Therefore, the transistors Q1-Q6designed as a CMOS circuit in the steam cascade configuration with a common gate electrodes g1, g3; g2, g4; g5, g6for related structures of the field MOS transistor Q1, Q3; Q2, Q4; Q5, Q6. Each CMOS circuit formed on the insulating layer, which in Fig.12 is below Q3between the Q1and Q4and between the Q2and Q5in each of the structures of the MOS transistor. The gate electrodes g are also isolated from the material of the active semiconductor b using implicitly denoted by insulating layers, which contain the corresponding gate insulators. Horizontal conductive paths in Fig. 10 and 11 is essentially replaced by a vertical conductive paths that pass through the layers and provide the same connection, as shown in the equivalent Shealy in Fig.10 and, as will be seen, again connects the gate electrodes g5, g6for Q5, Q6with the connection between the electrodes drains d2d3for Q2, Q3and the drain electrode d1for Q1.

The vertical structure of the logic circuit, And Fig.12, includes a substrate 1, created from 24 subsoil, 6 of which are relatively thick insulating layer to form the gate insulators, and three corresponding thick insulating layer mutually isolated paired combinations of the structures of the MOS field-effect transistors. With the same size, as shown in Fig.11, the entire multi-layer configuration of Fig.12 will have a thickness of about 3 μm and an area of 16 μm2. The total, therefore, of less than 50 μm3, i.e., the reduction will amount to 1/3 with respect to the configuration of Fig.11. Most important, however, that the conductive paths, which in the structure of Fig.11 will have a length of 52 μm, in the structure according to Fig.12 can be close to 15 μm in an optimal implementation, which gives a reduction of about 70%. In this regard, in particular, should take into account that Fig.12 illustrates a schematic representation and that the vertical conductive paths are mutually displaced in a horizontal plane, so that they looked Bo

In the framework of modern thin-film technology using technology, as described above, to create electrically conducting and/or semiconducting structures in thin films by irradiation convert organic materials it is possible to reduce the linear dimensions in the horizontal direction, so that the component density can be increased at least by one order of magnitude. This leads to the fact that the configuration according to Fig.11 can implement about 105the logic circuits shown on the area of 1 mm2and when the layer thickness is much smaller than 1 μm, while the configuration in Fig. 12 can realize about 6105the logic circuits in the same area with some of the best form factor, so increasing the density of devices reaches 33% relative to the density of devices in the configuration according to Fig.11.

Processing of the individual layers, i.e., the formation of electrically conducting and/or semiconducting structures, may be performed after the conversion by the electric fields and, as shown in Fig.2A-f and Fig.3, includes a possible post-processing and adjustment, such as heat treatment before combining the individual layers in megosh layers after conversion can be performed to control the conductive and/or semiconductive features for example, the conversion of monomer to oligomer or polymer alloying, crystallization, etc., Such processes are well known and are widely used, and therefore, specific examples are not considered here. The heat treatment may be performed, for example, by irradiation. Another possibility is the use of fields of alternating electric current. In principle, the alternating current field can also be used to convert field CAPM, and the power source 23 shown in Fig.2A-f, should be the source of AC voltage. In this regard, it should be noted that the resistive material, which is exposed to the alternating current field, will be heated. By using the AC voltage to generate a transition, for example from non-conducting to a conducting state, may be heating the thus created conductive patterns and the required heat treatment can be carried out simultaneously with the conversion process.

By using, for example, organic materials in layers to create electrically conducting and/or semiconducting structures with conversion by the electric fields according to the present invention vozmozhno with the current technology of inorganic semiconductors. If production schemes use the configuration from "coil-on-coil, as shown in Fig.7, the production can be carried out in large volumes and with high speed and without significant dimensional constraints. When the connection of the individual layers in the multilayer structure and the formation of superimposed configuration, the coincidence between the layers is, however, a critical factor that must ensure that the vertical conductive structures in separate layers mutually coincide, and that, for example, the electrodes and the active semiconductor material in semiconductor structures are also the same. Accuracy requirements match will be determined step, which can be implemented in the production of electrically conducting and/or semiconducting structures, but can be also realized by using interferometric methods, management and positioning, optical damage to labeling or mechanical or electrical nanotechnology. Such activities, however, are not included in the scope of the present invention and are therefore not discussed in more detail, but should be considered as well-known specialists in this field of technology.

By using the method of forming the layer structure can be formed remotely relative to the location of production and transferred there to download, for example, in the control device, which controls the formation of structures, physical schema directly in the production process. The user can thus create and produce schemes using remote processing according to your own specifications simply by transferring the necessary information and commands. The present invention can, thus, provide a concept for the production of integrated circuits applied orientation and integral circuits with radically new content.


Claims

1. The method of forming electrically conducting and/or semiconducting two-dimensional or three-dimensional structures in a composite matrix containing one or more of the materials respectively provided in one or more spatially separate and homogenous structures of materials, and materials in response to the flow of energy can be subjected to certain physical and/or chemical state changes that cause the transition from electrically non-conductive state to an electrically conducting and/or semiconducting state or Vice versa, or a change in the mode of the conductivity of the material, with each structure matere with a given field strength and/or characteristics, corresponding to a certain response of a material to the energy supplied by the field, is carried out in each case, the spatial modulation of fields according to a specific Protocol, which is a predefined configuration of the electrically conducting and/or semiconducting structures in the material structure, whereby in response to energy supplied by the field, form a two-dimensional electrically conducting and/or semiconducting structures with the configuration, a predefined Protocol, and additionally stack two or more layers on one another in the folded configuration to form a composite matrix formed separate adjacent layers of conductive and/or three-dimensional semiconductor structures.

2. The method according to p. 1, characterized in that the spatial modulation of the electric field is carried out in a plane substantially parallel to a layer using the electrode means with structured electrodes, with electrode means through selective supply voltage to the electrodes according to a specific Protocol form an electrical point or line potentials that form electroproportional two or more layers after creating a conductive and/or semiconductive structure in each layer, combine in a layered multilayer structure to form a composite matrix with conductive and/or three-dimensional semiconductor structures.

4. The method according to p. 3, characterized in that the multilayer structure is formed by the overlap of two or more self-sustaining layers to obtain a folded configuration.

5. The method according to p. 4, characterized in that the positioning layer after applying to adjacent layers such that the two or more two-dimensional electrically conducting and/or semiconducting structures in the first-mentioned layer according to the Protocol coincided with the one or more two-dimensional electrically conducting and/or semiconducting structures in the adjacent layers, whereby in the transverse direction through the layers form one or more vertical conductive and/or semiconductive channels.

6. The method according to p. 5, wherein forming a conductive and/or the semiconductor structure, which forms a vertical channel, passing through the layers according to the Protocol, conducting and/or semiconducting compound with one or more two-dimensional electrically conducting and/or semiconducting structures in this layer.

7. The method according to p. 6, characterized in that each of the b-p. 6, wherein each channel is formed with a conductivity or conduction mode, which vary from layer to layer.

9. The way the complete destruction of electrically conducting and/or semiconducting two-dimensional or three-dimensional structures formed in the composite matrix containing one or more of the materials respectively provided in one or more spatially separate and homogenous structures of materials, and materials in response to the flow of energy can be subjected to certain physical and/or chemical state changes that cause the transition from an electrically non-conductive state to an electrically conducting and/or semiconducting state or Vice versa, or a change in the mode of the conductivity of the material, and each material structure made in the form of a thin layer, characterized in that what does the global application to matrix composite electric field with a given field strength and/or characteristics corresponding to the specific response of a material to the energy provided by the field up until the materials in the composite matrix in accordance with the energy provided by the field, not fully go into electrically neprology and/or semiconductor two-dimensional or three-dimensional structures in the composite matrix, containing one or more of the materials respectively provided in one or more spatially separate and homogenous structures of materials, and materials in response to the flow of energy can be subjected to certain physical and/or chemical state changes that cause the transition from an electrically non-conductive state to an electrically conducting and/or semiconducting state or Vice versa, or a change in the mode of the conductivity of the material, and each material structure made in the form of a thin layer, characterized in that it contains the first electrode means (E1) with lots of parallel strip electrodes (21) placed in the plane, second electrode means (E2) with lots of parallel strip electrodes (22) placed at a distance from the first electrode means (E1) and imposed on him a second plane parallel to the first plane, so that the electrodes (21, 22) are mutually substantially orthogonal oriented in metrication configuration, electrode means (E1; E2) through the commutation device (24; 25) is connected with upravlyaemym power supply (23), and the generator/modulator electric field (20) in the space between the e is or continuous tape, without contact with the electrode means continuously or intermittently fed through the space with simultaneous positioning and alignment relative to the electrode means (E1, E2) between and in a plane substantially parallel to them, whereby there are formed conductive and/or semi-conductor structure according to a specific Protocol using point, line, or surface potentials generated between the selected electrodes (21, 22) of the electrode means (E1; E2), when the first through the commutation device (24; 25) is supplied electric power.

11. Generator/modulator of the electric field at p. 10, characterized in that the electrodes (21; 22) in each electrode means (E1; E2) is placed on the surface of the respective substrates or in them and facing each other.

12. Generator/modulator electric field on p. 11, characterized in that the strip electrodes (21, 22) is designed as a part of the substrate to form the conductive structures in the substrate material.

13. Generator/modulator of the electric field at p. 10, characterized in that the distance between the electrode means E1, E2) is adjustable depending on the thickness of the thin-film material.

14. Generate; E2) placed with a mutual distance of from 0.1 to 1.0 μm.

15. Generator/modulator of the electric field at p. 10, characterized in that the electrodes (21; 22) in each electrode means (E1; E2) are essentially constant width from 0.1 to 1.0 μm.

Priority items:
28.01.1998 - PP. 1-9;
02.06.1998 - PP. 10-15.

 

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1 cl, 2 dwg

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FIELD: physics, optics.

SUBSTANCE: invention is related to design of semiconductor injection lasers and technology of their manufacture, and may be used for creation of laser matrices of multi-channel fibre optic interfaces. Injection laser comprises contact layers and layers of semiconductor materials that form active radiating structure, which are installed coaxially in channel of circular, n-angular or figure section arranged in substrate body, at that external contact layer is connected to channel walls directly or via buffer layers, layers of semiconductor materials are installed on it, which create active radiating structure, and central contact layer is applied on them, at that on end surface of semiconductor materials layers that create active radiating structure, there is nontransparent mirror layer installed from one side, and semi-transparent mirror layer is arranged on the other side; also central contact layer and external contact layer are connected to conducting paths, which are arranged on substrate. Method for manufacture of injection laser includes serial application by method of chemical deposition from gas phase to substrate of layer of materials that create structure of injection laser, at that through channels are arranged in substrate body, and then gas phase of metal organic compounds is serially passed through them, and thus materials layers are deposited on internal surface of channels; also external contact layer is formed, as well as layers of semiconductor materials that create active radiating structure, and central contact layer, then conducting paths are applied on substrate, as well as mirror layers. Device for gas-cycle epitaxy comprises reactor, holder of substrates, inlet and outlet nozzles, heaters, loading and inspection manholes, at that reactor is separated into high pressure and low pressure zones by holder of substrates with substrates installed in them with through channels, and has control system that provides for maintenance of specified pressure values in zones of high and low pressure, and also difference of gas pressures in them, which is connected to pressure sensors installed in each reactor zone, and with reduction units, and holder of substrates represents plate with seats for substrates and with through holes in those areas, where through channels are available in substrates, at that size of holes in holder is more than size of area with channels in substrate.

EFFECT: possibility of large-scale production of laser strips and matrices without manual assembly.

5 cl, 9 dwg

FIELD: physics; semiconductors.

SUBSTANCE: invention relates to semiconductor engineering. When making a short-range particle detector, through ion implantation into a window, a silicon surface layer is doped with a p-type impurity on the p-n junction side, and on the ohmic side with an n-type impurity with a dose of 1015-1016 with ion energy of 500-2000 keV. The implanted layers are calcined at temperature 850-950°C for 1-2 hours. Chemical etching is then carried out in the window on the ohmic side at a depth of the mean path of the ions implanted into the silicon.

EFFECT: design of a short-range particle detector with reduced thickness of dead layers on the surface and low level of dark current.

6 cl

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