The encoder of bilocate orthogonal signals


H03M13/31 - combining coding for error detection or correction and efficient use of the spectrum (without error detection or correction H03M0005140000)

 

The invention relates to automation and computer engineering and can be used in radio communication systems with noise-like signals. The technical result consists in the simplification of the device. The device comprises an input register, unit bitwise addition modulo two with two m-bit inputs, m logical XOR block pairwise conjunction odd and even digits with one m-bit input, m/2 logic elements And, modulo two, the unit of inversion of the sign, a clock generator, a binary counter with an even number of digits. 3 Il., table 1.

The invention relates to automation and computer engineering and can be used in radio communication systems with noise-like signals using digital methods for the formation of large complex systems of orthogonal signals (see [1], S. 101-102).

The number of known devices that can be used to form systems of orthogonal signals. For example, for the formation of systems of orthogonal signals Walsh can be used by the encoder for the code, reed-Muller first order R(1, m) (see [2], S. 406, Fig. 14.8) - based matrices Hadamard type Sylvester (see [2], S. 52-53). With whom,...,2m-1} (see [2], 400 C., the formula 14.7) mathematically describes the operations of binary arithmeticwhere m is the number of bits of the binary counter; vi{0,1} is the output of the i-th digit of the binary counter; ui{ 0,1} is a binary input device, determining the number of orthogonal code sequences; u0{ 0,1} is the sign inversion (complement modulo two) of the system of orthogonal code sequences.

Code reed-Muller first order R(1, m) consists of the unit weight of 2m(consisting of all ones "11...1"), zero weight 0 (consisting of all zeros "00...0") and 2m+1- 2 code sequences of weight 2m-1.

A disadvantage of the known encoder R(1, m) lies in the fact that people belonging to one of the orthogonal system or the other system code sequences have the same weight 2m-1.

Typically, when even m system of orthogonal signals biblequote Cameron (see [2] , S. 414, corollary II, formula 14.29, exercise 16.) was built by the formulaThe orthogonal code in the same plane Cameron consists of 2mcode sequences of weight 2msup>+2(m-2)/2.

A disadvantage of the known formula (2) constructing orthogonal biblequote lies in the complexity, as it requires m+m/2-1 two-input logical XOR (adders modulo two) and m+m/2 logic elements And. it is Advisable to reduce excess m logical elements And.

Closest to the proposed device is a device for coding [3], containing the information register, control register, the first and second memory blocks, the block adders, and inputs information register are information input device that outputs information register connected to inputs of unit adders with inputs of the second memory block and are information output device that outputs a block of adders connected to the first inputs of the control register and the inputs of the first memory block, the outputs of the first and second memory blocks are connected to second inputs of the control register, the outputs of the control register are the outputs of the control characteristics of the device.

A disadvantage of the known device coding [3] is the difficulty.

Task - simplifying the device.

This object is achieved in that in the device, the content is the od of the m logical XOR, block pairwise conjunction odd and honest discharges with one m-bit input of the m/2 logic elements And, modulo two, the unit of inversion of the sign, a clock generator, a binary counter with an even number of digits, and m-bit information input of the input register is the input number signal of the encoder and the information bit input of the input register is input to the inversion of polarity-shift keyed signals to the opposite value of the encoder m-bit output register and an information output bitwise binary counter are connected respectively to the inputs of the first and second components of the block is bitwise addition modulo two, and the output of the overflow of the binary counter is connected with the control input write input of register m-bit output of the sum block is bitwise addition modulo two bitwise connected to the input of the pairwise conjunction odd and even bits, m/2-bit output block pairwise conjunction odd and even bits connected to m/2-bit input of the modulo two, the output of which is connected with the information input unit of inversion of the sign, the counting input of a binary counter connected to the output of the clock generator, the bit is raised by the output of the encoder. The advantage of the proposed device in comparison with the prototype [3] is to simplify and to eliminate the complex and redundant elements. In comparison with the known rule (2) constructing orthogonal signals biblequote Cameron proposed device uses on m less logic elements And. In comparison with the known description of reed-Muller codes of the first order [2] the proposed device, the binary code sequence have their own distinctive weight plane 2m-12(m-2)/2instead of one weight 2m-1. In addition, the proposed device allows you to practically implement the formation of large systems of complex signals with pulses of 103...106because the device is a memory unit for storing a code sequence. Thus, the proposed device is substantially different from the known [1-3].

Functional diagram of the encoder of bilocate orthogonal signals is shown in Fig.1, in Fig.2 is a timing diagram of operation of the device of Fig.3 is a view of the generated signals. The generator is characterized by the table.

The encoder of bilocate orthogonal signals includes (see Fig.1) (m+1)-bit input is a module with two two m-bit inputs of the m logical XOR, unit 6 pairwise conjunction odd and even digits with one m-bit input of the m/2 logic elements And the adder 7 modulo two with m/2 inputs, and single-bit and m-bit information inputs of the input register 1 are respectively input Y0 inversion polar-shift keyed signals to the opposite value of the encoder and the input Y1 numbers signal encoder, single-bit output of the input register 1 is connected with the control input of the unit 2 inversion of the sign, the counting input of the binary counter 3 is connected to the output of the clock generator 4, the output of the overflow of the binary counter 3 is connected with the control input write input register 1, m-bit output of the input register 1 and an information output of the binary counter 3 bitwise connected respectively to the inputs of the first and second components of block 5 bitwise addition modulo two m-bit output sum block 5 bitwise addition modulo two bitwise connected to the input unit 6 pairwise conjunction odd and even bits, m/2-bit output block 6 pairwise conjunction odd and even bits connected to the inputs of the adder 7 modulo two, the output of the adder 7 modulo two is connected with the information input unit 2 inversion of the sign, vazirovich codes integral number (Y0, Y1) for the entire period of time the formation of a complex signal: code Y0{0,1} determines the type of polar-shift keyed signal in direct or inverse (opposite) of the code; - code Y1{0,1,...,2m-1} specifies the binary number of the orthogonal code sequence signal.

Receiving a binary code with an input bus of the device is performed under the influence of logical level "1" from the control (clock) input write input of register 1. Changing the information on the output data bus input register 1 is at a negative difference at the control input record, i.e. at the beginning of each period. In the presence of the control input is the logical level "0" input register 1 shall store the received information for all time T generate a complex signal.

Unit 2 inversion of the sign allows you to receive the output signal in direct or inverse (opposite) of the code depending on the control logic level to a single-bit output of the input register 1. In addition, in the function block 2 inversion of the sign of the transition from a logic level "1", "0" to the analog values"+1", "-1".

The binary counter 3, counting the pulses from tachovska state "11...1" of the binary counter 3 produces a logic level "1" at the output of the overflow (reset) binary counter 3. This signal controls the reception of the input information in the input register 1, and the recording is performed at the beginning of each period.

Unit 5 bitwise addition modulo two with two m-bit inputs consists of m logical XOR. For each i-th category of the current conditions vithe binary counter 3 and a constant (in period T) of the displacement uispecified with m-bit output of the input register 1, block 5 bitwise addition modulo two computes the bitwise sum
wi= ui+ vi(mod 2),(3)
Thus, during the period T depending on the value "0" or "1" of the i-th bit of m-bit output of the input register 1 at the output of the i-th discharge unit 5 bitwise addition modulo two signal type "meander" from the i-th digit of the binary counter 3 in the forward or opposite your code accordingly.

Unit 6 pairwise conjunction odd and even digits with one m-bit input and m/2-bit output consists of m/2 logic elements And. For each of the n-th output of the discharge from the odd values of w2n-1and even w2nthe input bits of the block 6 pairwise conjunction odd and even digits computes a Boolean operamini 7 modulo two with m/2 inputs calculates the value of a logical operation

Thus, block 6 pairwise conjunction odd and even bits, and the adder 7 modulo two (see [2], S. 414, corollary II, formula 14.29) calculate the value of the maximum nonlinear "bent"functions
fj=w1w2+w3w4+...+wm-1wm(mod 2) (6)
The encoder of bilocate orthogonal signals is as follows.

When turning on the power source (Fig.1 not shown) is supplied the impetus for the installation in the logic state "11...1" of the binary counter 3 and to install in one state push-pull D trigger input register 1, so with a single-bit output of the input register 1 logic level "1" is supplied to the control input of block 2 of the inversion of the sign. Output overflow of the binary counter 3 of the logical level "1" is supplied to the control input write input register 1, turning it into receive mode (m+1)-bit digital code integral number signal. With m-bit output block 5 bitwise addition modulo two signals of logic level "0" are received at the inputs of block 6 pairwise conjunction odd and even digits. From the output of block 6 pairwise conjunction odd and even bits of the signals of logic level "0" are received Informatsionnyi the input unit 2 inversion of the sign, therefore, at the output device is set to a positive potential of a single amplitude "+1".

The clock generator 4 generates pulses with a repetition period Tandthat arrive at the counting input of the binary counter 3. After the first clock pulse, the binary counter 3 of the state "11...1" goes to the zero state, while the logic level "0" output reset binary counter 3 is supplied to the control input write input register 1, turning it into a storage mode of the input code composite numbers (Y0, Y1) for all time T = 2mTandthe formation of the complex signal. The logic level "0" or "1" in accordance with the input code Y0 with single-bit output of the input register 1 is supplied to the control input of block 2 of the inversion of the sign for the formation of polar-shift keyed signal of the orthogonal system (plane) in direct or inverse (opposite) of the code. With m-bit output of the input register 1 to the input of the first term unit 5 bitwise addition modulo two supplied binary code Y1{0,1,...,2m-1} non orthogonal signal in the system (the plane). Under the influence of each clock pulse, the binary counter 3 of predydushih the od of the second term unit 5 bitwise addition modulo two. From the output of block 5 bitwise addition modulo two computed bitwise sum (3) is fed to the input of block 6 pairwise conjunction odd and even digits. For each n-th bit of m/2-bit output block 6 pairwise conjunction odd and even digits calculates the logical conjunction (4). At the output of the adder 7 modulo two, the sum is calculated (5). The output of the encoder orthogonal code sequence signal is described by the expression

At the transition of the binary counter 3 in the state T the logic level "1" output from the overflow of the binary counter 3 is supplied to the control input write input of register 1. Input register 1 is transferred to the receive mode, a new (m+1)-bit binary numbers biorthogonol signal. Under the influence of the following clock cycle of device operation is repeated.

To the timing charts of the operation of the device (Fig.2) shows that the binary counter 3 (charts top 12-15) performs the division of the repetition frequency of clock pulses received at its counting input with the output of the clock generator 4 (chart 11). If the counter 3 becomes in a state T, then at the output of the overflow is set to logical is W Y0, Y1 (chart 1-5). After the next clock pulse counter 3 becomes zero state at the output of the overflow is set to logic level "0" and the register 1 goes into storage mode input codes Y0, Y1 for all time T form a complex signal (figure 6-10). For time T at the inputs of register 1 are prepared new digital codes Y0, Y1 (chart 1-5). Depending on the signals on the respective outputs of block 5 (figure 7-20) signals are formed at the outputs of block 6 (charts 21 and 22). Depending on the output signal of the adder 7 (figure 23) and output a single-bit output register 1 (figure 6) is formed output polar-shift keyed signal device (figure 24) in the forward or in the opposite code.

The table shows the code sequence biorthogonol signals generated by the proposed device when five digit input bus data register 1 (m=4) where the symbols "+" and "-" indicate pulses of unit amplitude positive and negative polarity, respectively. Depending on the five bits of the input code (Y0, Y1) (table columns 2 through 6) is formed from 1 to 32 shestnadcatiletnih polar-shift keyed signals (table CMU, as

The second sixteen signals (Fig. 3 (B), lines 17-32 table) also form an orthogonal system of signals as

Signalsi(t) andi(t) the opposite,
The advantage of the proposed device in comparison with analogue and prototype is to simplify and to eliminate the complex and redundant elements. In comparison with the known rule (2) constructing orthogonal signals biblequote Cameron proposed device uses on m less logic elements And. In comparison with the prototype of the proposed device, the excluded block of memory, and modulo (T-1) replaced by simpler in technical execution unit 5 bitwise sum modulo two. In comparison with the known description of reed-Muller codes of the first order [2, 3, 4] the proposed device, the binary code sequence have their own distinctive weight plane 2m-12(m-2)/2instead of one weight 2m-1. In addition, the proposed device allows you to practically implement the formation of large systems is in code sequences.

Sources of information
1. Varakin L. E. communication Systems with noise-like signals. - M.: Radio and communication, 1985. - 383 S.

2. Mack-Williams, F. J., The Sloan N. J.A. theory of error-correcting codes. - M.: Communication, 1979. - S. 744

3. Grinenko N. I., Lysakowski A. F., Shevchuk P.F. Generator orthogonal opposite signals /USSR Author's certificate 1697071 A1, class MKI G 06 F 1/02.

4. Hall, M. Combinatorics. - M.: Mir, 1970. - 424 S.


Claims

The encoder of bilocate orthogonal signals containing the input register, wherein the additionally introduced block bitwise addition modulo two with two m-bit inputs of the m logical XOR block pairwise conjunction odd and even digits with one m-bit input of the m/2 logic elements And, modulo two, the unit of inversion of the sign, a clock generator, a binary counter with an even number of digits, and m-bit information input of the input register is the input number signal encoder, and the information bit input of the input register is input to the inversion of polarity-shift keyed signals to the opposite value of the encoder m-bit output of the input register and the information the and bitwise addition modulo two, and the output of the overflow of the binary counter is connected with the control input write input of register m-bit output of the sum block is bitwise addition modulo two bitwise connected to the input of the pairwise conjunction odd and even bits, m/2-bit output block pairwise conjunction odd and even bits connected to m/2-bit input of the modulo two, the output of which is connected with the information input unit of inversion of the sign, the counting input of a binary counter connected to the output of a clock generator, a single-bit output of the input register is connected with the control input of the inversion of the sign, the output of the inversion of the sign is the output of the encoder.

 

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