A method of manufacturing a powerful high-current mos transistor

 

Usage: in microelectronics, in the manufacture of integrated circuits and semiconductor devices. The inventive method of manufacturing a powerful high-current MOS transistor includes the steps of forming the drain regions of the 1st conduction type MOS transistor, a masking dielectric on the surface of the plate, grooves for allocation on a monocrystalline plate sections, a thin gate dielectric on the surface of the open areas of silicon, filling the recesses with polyctenium, which is the gate, creating methods of ion doping and heat treatment of the gate region 2 of the first conductivity type, the contact area for her 2nd type conductivity and the area of source 1 type conductivity in each of the above single-crystal phase, the formation of metal contacts. After creating a gate dielectric on the surface of the plate is precipitated by a thin layer of polysilicon, the recesses are filled with photoresist to the planarity of the surface of the plate, remove the unmasked photoresist areas of polysilicon is removed from the recesses of the photoresist and methods of local deposition from the gas phase hollows filled with polyctenium trebuemogo the simplification of the method of manufacturing a powerful high-current MOS transistor by reducing the number of operations, including precision, and accordingly increase the percentage of yield in manufacturing. 10 Il.

The invention relates to microelectronics, namely the integral p/p circuits and p/p devices. In the technology of integrated circuits are widely used different ways to create the MOS transistors of the p - or p-type and n - and p-type on one silicon wafer (CMOS technology).

A known method of manufacturing IP [1] , including the creation in the substrate of the first conductivity diffusion of pockets of the second type, the formation of the drain-sources of the transistors of the first type and the buffer areas for the transistors of the second type, the formation of the drain-sources of the transistors of the second type and the buffer areas for the transistors of the first type, the formation of a thin oxide in the areas of channels, forming contact Windows and metal wiring.

The disadvantages of the method for the production of this IP are the low degree of samoobladanie paddles, contact Windows, security areas and pockets with drain regions-the sources of the transistors of both types, as well as the need to obtain high-current MOS transistors considerable increase their size when the magnification ratio W/L (W - the width of the SLA, resistance drain-stokovyh areas, etc.

The closest technical solution is a high-current N-channel MOS transistor manufactured according to the technology [2], which includes the operation of forming the drain regions of the 1st conduction type MOS transistor (Fig. 1, 2), masking dielectric on the surface of the plate, grooves for isolation on a plate of monocrystalline plots (Fig. 3), a thin gate dielectric on the surface of the open areas of the silicon (Fig. 4), the filling of the recesses with polyctenium, which is the gate by the deposition of thick polysilicon on the surface of the plate by the method of deposition from the gas phase at low pressure and planarization method of plasma-chemical etching of polysilicon to a masking dielectric, creating methods of ion doping and heat treatment of the gate region 2 of the first conductivity type, the contact area for her 2nd type conductivity and the area of source 1 type conductivity in each of the above single-crystal phase, the formation of metal contacts to corresponding areas of the drain, gate, source and gate region.

The disadvantages of the prototype is the complexity of the technology this transis the manufacture.

The problem to which this invention is directed, is the achievement of the technical result consists in simplifying the method of manufacturing a powerful high-current MOS transistor by reducing the number of operations, including precision, and accordingly increase the percentage of yield in manufacturing.

The problem is solved by a method of manufacturing a powerful high-current MOS transistor that includes the operation of forming the drain regions of the 1st conduction type MOS transistor (Fig. 1, 2), masking dielectric on the surface of the plate, grooves for isolation on a plate of monocrystalline plots (Fig. 3), a thin gate dielectric on the surface of the open areas of the silicon (Fig. 4), the filling of the recesses with polyctenium, which is the gate, creating methods of ion doping and heat treatment of the gate region 2 of the first conductivity type, the contact area for her 2nd type conductivity and the area of source 1 type conductivity in each of the above single-crystal phase, the formation of metal contacts, and after operations create a gate dielectric on the surface of the plate precipitated thin layers of polysilicon (Finno the photoresist areas of polysilicon (Fig. 5B), are removed from the recesses of the photoresist (Fig. 5g) and methods of local deposition from the gas phase hollows filled with polyctenium a desired type of conductivity to the planarity of the surface of the plate (Fig. 6).

Thus, the hallmark of the invention is that after the operation of creating a gate dielectric on the surface of the plate precipitated thin layers of polysilicon (Fig. 5A), the recesses are filled with photoresist to the planarity of the surface of the plate (Fig. 5B), remove the unmasked photoresist areas of polysilicon (Fig. 5B), are removed from the recesses of the photoresist (Fig. 5g) and methods of local deposition from the gas phase hollows filled with polyctenium a desired type of conductivity to the planarity of the surface of the plate (Fig. 6). The final structure of the high-current MOS transistor shown in Fig. 7.

This transistor is a high degree of integration: - used vertical structure transistor as opposed to the horizontal in the previous case, i.e., the gate of the transistor is in the recesses of the substrate and the transistor channel is vertical to the surface of the substrate along the surface of the grooves, and not on the surface of the plate; - implemented the principle of phoneline monocrystalline areas, is formed by the gate region, the contact area and her and Itokawa region with the corresponding contact; also implemented samoobladanie Stoke-stokovyh areas with stopper.

All this allows to significantly increase the ratio of W/L and accordingly increase the amount of current at a constant square transistor at the surface of the plate. Estimate what win ratio W/L gives the vertical structure of the MOS transistor in comparison with the horizontal structure of the MOS transistor. Assume that transistors made according to the technology with 1.5 μm design rule in both cases, the slit width of 0.6 μm, the effective channel length is taken equal to 1 μm in both cases.

1. A variant of the vertical MOS transistor, in which a monocrystalline region allocated recesses located on the surface of the plate in the form of a "lattice".

The size of each single-crystal region with regard to the window under the metal contact (1,5x1,5) microns and the gap between the window and deepening of 1.5 μm is 4,5x4,5 μm2. Given the deepening of the area will be 5,h,1 μm. The effective ratio of W/L for each crystal region is equal to 9, with consideration of the recesses is equal to 8, 2. Option horizontal MOS transistors between the window and the edge of the shutter to 1.5 μm.

The area of the transistor is 4,5x6,0 μm, where a 4.5 μm - width of the transistor, and 6.0 μm - length of the transistor (the selected distance between the centers of the boxes under the metal contact to the source and the drain).

Thus, the gain current at the same area on the surface of the plate at 1.5 µm design rules and other conditions being equal, will be 2.3 times. The use of grooves with a width of 0.6 μm leads to a loss of total 25% at 1.5 μm design rules slightly. This method allows you to create high-current transistor.

The use of the invention allows to reduce by 1 the number of precision operations: instead of the deposition of the thick polysilicon that fills the cavities and planarization of the surface by the method of plasma-chemical etching of polysilicon to a masking dielectric covering monocrystalline areas using a local polysilicon deposition from the gas phase to the planarity of the surface of the plates.

It should be noted that to improve the quality of the filling of the recesses with polyctenium, the deposition of thick polysilicon is mainly carried out in several stages in layers with additional heat treatments that substantially the etoy precision (without regard to the additional heat treatments used in the method of the invention increases by 4 operations, i.e. slightly Thus, the invention will simplify the method of manufacturing and increase product yield. This set of distinctive features allows you to achieve the mentioned technical result. The invention is illustrated in Fig. 1-7.

An example implementation of a method of manufacturing a powerful high-current MOS transistor.

1. The original silicon substrate of N+ type, orientation (100),v=0.01 Ohmcm (Fig. 1).

2. Epitaxy of N - type: h=2,5-4,0 µmv=1-7 Omcm (Fig. 2).

3. Forming a dielectric layer on the surface of the plate: oxidation in H2About h=0.05 to 0.4 µm.

4. Projection photolithography "recesses" (shutter) L=0,6-1,0 mm.

5. Plasma etching of "holes" with the subsequent removal of photoresist and cleaning the surface of the plate: SiO2+Si with depth hSi=2 ám.

6. Chemical treatment (Fig. 3).

7. Forming a gate dielectric T=850oC - 1000oWith h=100-500 (Fig. 4).

8. The deposition of thin Si* (Fig. 5A) h=1000-1500 A.

9. Filling the recesses of the photoresist to the planarity of the surface of the plate (Fig. 5B).

10. Removing the unmasked photoresist sections Si* (Fig. 5V).

Lauda Si* desired type of conductivity (Fig. 6).

13. Forming a gate of the P - region Xj=1.0 to 1.5 μm.

14. The formation of the N+ stokovyh areas Xj=0.25 to 0.45 μm and the P+ contact to the P - region.

15. Forming an insulating dielectric on the surface of the plate, h= 0.4 to 0.7 microns.

16. The formation of ohmic contacts to the regions of the source N+, P+ contact (gate region), Si* the shutter.

17. Application pestiviruses layer on the front surface of the plate and forming Windows in the passivation.

18. The thinning of the wafer to the desired thickness h=200-400 mm and forming a contact to the back side of the plate (flow) (Fig. 7).

Sources of information 1. U.S. patent 3461361, CL 313-235. published. 1969

2. U.S. patent 5298442, CL 437/40, published. 1994

Claims

A method of manufacturing a powerful high-current MOS transistor that includes the operation of forming the drain regions of the 1st conduction type MOS transistor, a masking dielectric on the surface of the plate, grooves for allocation on a monocrystalline plate sections, a thin gate dielectric on the surface of the open areas of silicon, filling the recesses with polyctenium, which is the gate, creating methods of ion doping and thermal processing podzatvornogo in each of the above single-crystal phase, the formation of metal contacts, wherein after creating a gate dielectric on the surface of the plate is precipitated by a thin layer of polysilicon, the recesses are filled with photoresist to the planarity of the surface of the plate, remove the unmasked photoresist areas of polysilicon is removed from the recesses of the photoresist and methods of local deposition from the gas phase hollows filled with polyctenium a desired type of conductivity to the planarity of the surface of the plate.

 

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