Integrated mos transistor structure
Usage: microelectronics. The inventive integrated MOS transistor structure includes a semiconductor substrate of the first conductivity type dielectric layer, which are ishikawae and a drain region of the first conductivity type separated by gate region of the second conductivity type, the overlapped area of the gate dielectric with located on the shutter, and introduced additional region of the second type of provodimosti adjacent to the stock area and forming an emitter of a bipolar transistor, the base of which is referred to the drain region, and a collector - mentioned gate region. The technical result of the invention is to increase performance and decrease in the area of integrated MOS transistor structures. 3 Il. The invention relates to microelectronics, and more particularly to integrated transistor structures of the MOS type.Known integrated transistor structure with channels n and p type conductivity and gates in MOS structures (see, for example, U.S. Pat. USA 4149176, complementay MOSFET device, Fig. 10, 1979).Closest to the technical nature of the design selected as protot>century" Nenotechnology 10 (1999) 113-116. Printed in the UK. PII: S0957-4484(99)97402-0).A significant disadvantage of the known integral MOS transistor structures is their relatively poor performance in digital circuits CMOS. This disadvantage is due to the fact that MOS structure is capable of switching currents of relatively small magnitude.The invention sets the target to increase the performance of integrated MOS transistor structures.Another problem solved by the invention is a reduction in the area of digital circuits CMOS using complementary MOSFET Device.These tasks are solved in the design of integrated MOS transistor structure comprising on a semiconductor substrate of the first conductivity type dielectric layer, which are Itokawa and a drain region of the first conductivity type separated by gate region of the second conductivity type, the overlapped area of the gate dielectric with located on the shutter.Differences between the proposed integrated MOS transistor structure lies in the fact that it further comprises the region of the second conductivity type, adjacent to the stock area and forming an emitter of a bipolar transistor, the base of which serve the proposed integrated transistor structure is achieved thanks to the presence of a bipolar transistor, and space saving is due to the overlapping regions of the base and collector, respectively, with the drain and gate region.The invention is illustrated in the shown drawings of Fig.1 shows a section of the integrated MOS transistor structure according to the invention.In Fig.2 shows the electrical equivalent circuit of the integrated MOS transistor structure according to the invention.In Fig.3 shows the electric diagram of the logical element type BiCMOS using the invention.Integrated transistor OS structure includes a semiconductor substrate 1 of the first conduction type and the dielectric layer 2, on which is located the area of source 3 of the first conductivity type MOS transistor T1, the split gate region 5 of the second conductivity type which is overlapped by the region 6 gate dielectric, with on her gate 7, an additional area 8 of the second conductivity type, adjacent to the stock area 4 and forming the emitter of the bipolar transistor T2, the base of which serves as the drain region 4 and the collector - gate region 5.Integrated MOS transistor structure according to the invention can be used to build logic element VSM is presented in Fig. 2, forms a circuit of the charge handling capacity 9 BiCMOS logic element type, connected to its output 10. This structure is connected regions 3 and 5 to the power bus 12, and a shutter 7 to the input 11. The second MOS transistor structure according to the invention, the gate of n-channel MOS transistor T2 is connected to the input 11 logic element, the emitter of the bipolar p-n-p transistor T2' to exit 10, and the source - to the common bus 13 and forms a discharge circuit load capacity 9.Integrated MOS transistor structure according to the invention are as follows. If the input 11 of the voltage equal to the voltage of the common bus (i.e., voltage, equal to zero), the transistor T1' is closed, and the transistor T1 is open. Thus, the current from the power bus 12 through the opened transistor T1 flows in the base 4 of the transistor T2 and opens it, starts to leak current from the power bus 12 that charges the load capacitance 9. The charge of the load capacitance when this occurs, a relatively large current exceeding the current flowing through the transistor T1 is more than ten times, which leads to less time delay in comparison with classical CMOS circuit. When the voltage at the input 11 is increased to values exceeding the threshold naprasnosti T1' to the base of transistor T2' is passed, the potential of the common bus 13. The transistor T2' is opened and there is a discharge of the load capacitance 9. When the discharge current flowing through the bipolar transistor T2' is considerably higher than the current switching MOS transistor T1', which leads to lower switching delay logic element.Integrated MOS transistor structure can be widely used in the construction of VLSI logic and memory devices due to its high performance combined with high-density, line-up, due to the combination of workspaces field and bipolar transistors. For the manufacture of the integrated structure according to the invention does not require any additional process steps, it may be manufactured, for example, by technology type SIO CMOS.
ClaimsIntegrated MOS transistor structure with a semiconductor substrate of the first conductivity type dielectric layer, which are Itokawa and a drain region of the first conductivity type separated by gate region of the second conductivity type, the overlapped area of the gate dielectric with located on the shutter, characterized in that stoter bipolar transistor, base which is referred to the drain region, and a collector - mentioned gate region.
FIELD: computer engineering and integrated electronics; integrated logic gates of very large-scale integrated circuits.
SUBSTANCE: newly introduced in integrated logic gate that has semi-insulating GaAs substrate, first input metal bus, first AlGaAs region of second polarity of conductivity disposed under the latter to form common Schottky barrier junction, first inherent-conductivity AlGaAs spacer region disposed under the latter, first GaAs region of inherent-conductivity channel disposed under the latter, second AlGaAs region of second polarity of conductivity, second AlGaAs spacer region of inherent conductivity, second input metal bus, output region of second polarity of conductivity, output metal bus, power metal bus, zero-potential metal bus, and isolating dielectric regions are inherent-conductivity AlGaAs tunnel-barrier region, InGaAs region of inherent-conductivity channel, AlGaAs region of second inherent-conductivity barrier, L-section power region of second polarity of conductivity, and Г-section zero-potential region of second polarity of conductivity; first GaAs region of inherent-conductivity channel and InGaAs region of inherent-conductivity channel are disposed in relatively vertical position and separated by AlGaAs region of inherent-conductivity tunnel barrier; output region of second polarity of conductivity is ┘-shaped and ┘-section region.
EFFECT: enhanced efficiency of using chip area, enhanced speed and reduced power requirement for integrated logic gate switching.
1 cl, 3 dwg
FIELD: computer science and integral electronics, in particular - engineering of VLSI integral logical elements.
SUBSTANCE: integral logical element contains semi-insulated GaAs substrate, first input metallic bus, first AlGaAs area of second conductivity type, positioned above aforementioned bus and forming Schottky transition together with it, below it first AlGaAs area of native conductivity spacer is positioned, below it, first GaAs area of native conductivity channel is positioned, second AlGaAs area of second conductivity type, second AlGaAs area of native conductivity spacer, second input metallic bus, output area of second conductivity type, output metallic bus, zero potential metallic bus, metallic power bus, areas of separating dielectric. Integral logical element additionally contains AlGaAs area of native conductivity tunnel barrier, InGaAs area of native conductivity channel, AlGaAs area of second conductivity barrier, zero potential area of second conductivity type with transverse cross-section in form of symbol L, while first GaAs area of native conductivity channel and InGaAs area of native conductivity channel have vertical mutual position and are divided by AlGaAs area of native conductivity tunnel barrier, output area of second conductivity type is L-shaped and has L-shaped cross-section.
EFFECT: decreased efficiency of crystal area usage, increased speed of operation and decreased energy consumed by switching integral logical element.
FIELD: power semiconductor microelectronics.
SUBSTANCE: newly introduced in central part of semiconductor structure that has substrate, semiconductor material with depleted area in its central part enclosed by depleted area in peripheral part of structure, and relevant current-conducting contacts are recessed components of reverse polarity of conductivity with spherical depleted area whose electric field strength is higher than that of depleted areas in gap between recessed components and in peripheral part of structure.
EFFECT: improved power characteristics, enhanced resistance to pulse overcurrents.
7 cl, 1 dwg
SUBSTANCE: invention relates to design and technology of manufacturing semiconductor integrated circuits (IC) and can be used in digital, analogue and memory units in microelectronics. The semiconductor IC has a high-resistance monocrystalline silicon layer grown in form of a hollow cylinder in which there are regions with different conduction type, which form bipolar transistors, resistors and capacitors. On the outer surface of the high-resistance monocrystalline silicon layer there are emitter and base contacts adjacent to corresponding regions of corresponding transistors connected to resistors and capacitors by conductive paths formed on the surface of a dielectric placed on the outer surface of the high-resistance monocrystalline silicon layer, and on the inner surface of the high-resistance monocrystalline silicon layer there is a collector contact in form of a hollow cylinder adjacent to the collector regions of the transistors or the adjacent silicon layer.
EFFECT: higher degree of integration of the IC, reduced feature size of the element, lower level of inter-electrode connections, reduction of power consumption by one switching, increased reliability.
3 cl, 1 dwg
SUBSTANCE: semiconductor structure of the logical element AND-NOT comprising the first and second logical transistors, the first and second injecting transistors and a substrate is made as nanosized with a stepped profile and comprises four collectors, four bases and at least four emitters on the substrate of the first type of conductivity.
EFFECT: reduced consumed power and increased efficiency.
SUBSTANCE: in the integral logical AND-NOT element based on a layered three dimensional nanostructure (the element containing the first and the second logical transistors, the first and the second injecting transistors and a substrate) the logical structure is designed to be nanosized with a stepped profile.
EFFECT: increased response speed and reduced power consumption.
SUBSTANCE: multifunctional microwave monolithic integrated circuit board based on a multilayer semiconductor structure combines functions of several monolithic integrated circuit boards and comprises field-effect Schottky transistors and quasivertical Schottky barrier diodes with high values of boundary frequencies, which are integrated at the same chip and used as active and non-linear elements. Active areas of the field-effect transistors and basic areas of the quasivertical diodes are placed in different epitaxial layers with a low-ohmic contact layer placed between them and ohmic source and drain contacts of the transistors and ohmic cathodic contacts of the diodes are attached to it.
EFFECT: increased degree of integration for the microwave multifunctional integrated circuit board, reduced weight and dimensions for receiving and transmitting modules of antenna arrays, reduced losses related to signals passage between the schemes of functional units, increased boundary frequencies for the Schottky barrier diodes.
SUBSTANCE: in a semiconductor device a diode area and IGBT area are formed at the same semiconductor substrate. The diode area includes a multitude of anode layers with the first type of conductivity open at the surface of the semiconductor substrate and separated from each other. The IGBT area includes a multitude of contact layers of the body with the first type of conductivity open at the surface of the semiconductor substrate and separated from each other. An anode layer includes at least one or more first anode layers. The first anode layer is formed close to the IGBT area at least, and the square area in each of the first anode layers in the direction of the semiconductor substrate plane is more than the square area in each contact layer of the body in direct vicinity from the diode area in the direction of the semiconductor substrate plane.
EFFECT: invention prevents direct voltage growth in the diode area and increased heat losses.
2 cl, 5 dwg
FIELD: process engineering.
SUBSTANCE: invention relates to microelectronics, particularly, to production of solid-state devices by evaporation of metal coating on the substrate back surface. Claimed process consists in that the substrate is flexed in reverse direction before evaporation of metal coating. It differs from known processes in that said coating is evaporated on substrate back surface through stencil with through holes shaped and sized to crystals. Jumpers between said holes in stencil are comparable with the width of division webs made between crystals on substrate face surface.
EFFECT: reduced residual thermomechanical strains at said boundary.
FIELD: manufacturing technology.
SUBSTANCE: invention relates to production of integrated microcircuits in part of interposer forming for 3D assembly of several chips in single micro-system and process of its production. Invention is aimed at reducing effect of temperature gradients and associated mechanical stresses arising in body of interposer during operation of integrated microelectronic system. For this purpose, in body of interposer around through holes (TSV) filled with conducting material to create electric connection of metallized electric wiring working side with metallized layout of interposer reverse side formed holes, one of topological dimensions considerably smaller than minimum feature size TSV.
EFFECT: formed holes for reducing effect of temperature gradients are filled with material with heat conductivity higher than that of silicon, for compensation of mechanical stresses are not filled or are filled partially with formation of cavities inside hole.
18 cl, 11 dwg