Analog-to-digital converter

 

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code. The technical result is to increase speed ADC by applying the optimal logical procedure of selection of the output code, taking into account the statistical characteristics of the signal, the temporal characteristics of the DAC, and code values obtained in previous cycles of transformation. The device comprises a comparison circuit, a DAC, a trigger pulse generator, a counter, a register, a ROM, block prediction. 4 Il., table 2.

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code.

Known analog-to-digital Converter (ADC) the witness of the type with a voltage comparator, oscillator, item, count, voltage reference and digital-to-analogue Converter (DAC) (microelectronic device automation: Educational. manual for schools/ A. A. Sazonov, V. I. Nikolaev and others ; Ed. by A. A. Sazonova. - M.: Energoatomizdat, 1991. - S. 153, Fig. 2.29).

The disadvantage of this device is to increase the conversion time when the ADC is a successive approximation, contains a comparison circuit (SS), at the first input of which is fed to the input of the converted voltage, and the output connected to the first input register of the successive approximation (RPA), the first outputs of which are connected to the inputs of the digital to analogue Converter (DAC) and are simultaneously outputs of the ADC, the DAC output is connected to the second input of the comparison circuit, the second input of the successive approximation register is the second ADC input, a third input connected to the output element And the second output to the second input of this element And, the first input of which is connected to the generator output clock pulses (Chernov Century, Device I / o analog information to digital systems of data collection and processing. - M.: Mashinostroenie, 1988. - S. 85, Fig.57. Functional diagram and the timing diagram of the ADC successive approximation). Successive approximation ADC is characterized by the following features. During code selection method is used half of the division, but the principle of half-fission does not take into account the statistical characteristics of the input analog signal. The conversion process always takes N clock cycles, where N is the ADC, and the duration of the transformation is Tp is the quality of the tDACtake the value equal to its maximum value of tCapMan(corresponding to the feed input of the DAC zero after the maximum code for a given DAC), i.e., is not taken into account the different time of the output voltage at the DAC output for different codes. ADC successive approximation also does not account code values obtained in previous cycles of the conversion.

The disadvantage of this device is a low speed, because it does not takes into account statistical characteristics of the signal, the settling time voltage output digital to analogue Converter and code values obtained in previous cycles of the conversion.

The technical result improved ADC performance through the application of optimal logical procedure of selection of the output code, taking into account the statistical characteristics of the signal and the temporal characteristics of the DAC (the settling time of the input voltage), and code values obtained in previous cycles of the conversion.

The technical result is achieved by the successive approximation ADC, containing a comparison circuit (SS), at the first input of which is fed to the input of the converted voltage, moves register and are the first outputs of the device, the first input register of the second ADC input, the pulse generator is introduced counter, a persistent storage device (ROM), the block prediction, the trigger, the first input connected with the second input device, the output is the second output device and connected to the first input of the block prediction and the input of the pulse generator, the first output of which is connected to the first counter input and a second output connected to the second input of the trigger, the second input of the counter is connected with its output, the third input of the comparison circuit and the second input register, the outputs of which are connected with the second inputs of the block prediction, the outputs of which are connected to third inputs of the register and to the first inputs of the ROM, the second input is connected to the output of the comparison circuit, the third input connected to the output of the register, the first outputs of the ROM is connected to the fourth inputs of the register, the second outputs to the third inputs of the counter, the third output to the third input of the trigger.

A structural scheme of the device differs from the known fact that it introduced a counter, a persistent storage device (ROM), the block prediction and the trigger, which are standard nodes analog and digital computers. As a researcher the project - register IR (Avanesyan, R., Levshin VP of Integrated circuits TTL, TTLS. The Handbook. - M.: Mashinostroenie, 1993. - C. 160, 194, 195, 199, 207, 171). However, despite the fact that the blocks are standard nodes of digital technology, their introduction, as well as the emergence of new functional connections between them and the existing blocks provide an opportunity to appear in the device to a new property. Namely, the ADC can reduce the conversion time of the measured value by applying optimal matching code, taking into account the probabilistic characteristics of the measured value, the temporal characteristics of the digital to analogue Converter (settling time output voltage), and the values of the codes in the ADC output at the previous conversion cycles. The optimal procedure code selection can be made using methods known in theory of automatic control and Troubleshooting (Paszkowski, C. the problem of optimal detection and search failures in CEA/ Under. editor I. A. Ushakov. - M.: Radio and communication, 1981. - 280 C.). Application of best practices, built taking into account previous values of the output code, allows to reduce the time spent on the selection code corresponding to the input is, the de 1 - comparison circuit; 2 - analog Converter (DAC); 3 - trigger; 4 - pulse generator; 5 - meter; 6 - register; 7 - persistent storage device (ROM); 8 - block prediction. In Fig.2 shows the block structure prediction 8, implements a linear prediction algorithm, where 9, 10, the first and second registers block prediction; 11 - block subtraction.

Comparison circuit 1 is intended to compare the input to be converted voltage UIand voltage output DAC 2 - UDAC. If UI>UDACthe output of the comparison circuit 1 appears a signal corresponding to a logical unit, otherwise a logic zero. As the comparison circuit 1 uses strobing comparator - when applying the zero level at its third (gate) input voltage at the output of the comparison circuit 1 is fixed. This is necessary in order to eliminate the change of the output signal of the comparison circuit 1 when overwriting information from the ROM 7 in the counter 5 and the case 6. Comparison circuit 1 can be implemented on the chip strobing comparator SA (Bulychev, A. L. Analog integrated circuits: a Handbook / by A. L. Bulychev, V. I. Galkin, V. A. Prokhorenko. - Minsk: Belarus, 1994. - S. 382-383). DAC 2 is designed voltage. The trigger 3 is designed for fixing the beginning and end of the conversion process. When submitting its first input pulse trigger 3 passes in one state and starts the conversion process. At the end of the conversion process, the trigger 3 is reset to the zero state by a pulse from the second output of the pulse generator 4 (supplied to the second input of the trigger 3) for admission to the third input of the trigger 3 single signal from the third output of the ROM 7. The pulse generator 4 is designed to synchronize the operation of the device. He has two outputs, and the pulses on the second inverted output pulses at the first output. He starts feeding on its control input voltage corresponding to a logical unit, the output of the trigger 3.

The counter 5 is designed to generate a time interval corresponding to the time of establishing the voltage at the DAC output 2 for the current code. For this purpose, the counter 5 is written to a certain number and it is switched to the mode of addition (subtraction). When applying to the first input of the pulse counter content it increases (if you are using a summing counter) or decreases (if using subtractive counter). Upon reaching the contents of the counter maximum is level logic zero, which signals the end of the specified time interval. A logic level zero output of the counter 5 receives at its second input, and it goes into record mode. With the arrival of the positive edge on the first input of the counter 5 is recorded in it the information presented on its third (information) inputs. At the output of the counter 5 is set to the logical level of the unit, it goes into the mode of addition (subtraction) and the formation of the next time period.

As a counter 5 can be used with chip IE. Out-migration (P) must be connected through an inverter to the input control mode (L). In sum mode signal at the output of transfer (R) appears when you reach the contents of the counter maximum value. Let for a given code (submitted to the DAC input) setup time of the output voltage of the DAC is Tiand the period of the pulses from generator 4 ist. Then at the count of 5 you must record the number of NSCequal to NSC= Nmax-Ti/t, where Nmax- the maximum value of the content of the counter where there is a signal at the output of transfer (B).

vanesyan, R., Levshin VP of Integrated circuits TTL, TTLS. The Handbook. - M.: Mashinostroenie, 1993. - S. 199). In subtractive mode for forming a time interval 7, the counter will need to write code is equal to NSC=Ti/t. When describing the operation of the device assumes that you are using subtractive counter. In addition, we assume that the delay is proportional to the difference between the previous code and the following (delay setting voltage output DAC 2) plus one pulse at the time of the comparison circuit 1. For example, if after the code 8 (1000) at the input of the DAC 2 is fed code 6 (0110), the counter 5 is necessary to record the number 3 (3=8-6+1).

Register 6 is designed to store the current value of the output code conversion. When applying the pulse to the first input of the register 6 is recorded in it the information presented on its third input from the output of the block prediction 8. On the positive front, the impulse applied to the second input of the register 6, it is written information submitted on his fourth inputs from the first outputs of the ROM 7. Case 6 can be implemented on-chip dual-channel register IR (Avanesyan, R. , Levshin VP of Integrated circuits TTL, TTLS. The Handbook. - M.: Mashinostroenie the market selection of the output code, the corresponding analog input voltage UI. In ROM 7 also stores the values of the delays for all codes used (corresponding to the time of establishing the voltage at the DAC output 2).

The block prediction 8 is used to select the search process depending on the codes from the previous conversion cycles. As unit 8 predictions can be used normal case. It will be used for storing code that you received in the previous conversion cycle (algorithm zero prediction). It is assumed that the input of the converted value will change slightly during the entire conversion cycle and, accordingly, the value of the output code in the next conversion cycle will be close to the code value in the previous cycle.

To implement more accurate (linear) prediction of the block structure prediction (BPR) may have the form shown in Fig.2. In the first case 9 block prediction 8 stores the code value received at the end of the last conversion cycle To ai. This code will be written in the first register 9 BPR with output register 6 devices with the appearance of negative differential on the first input unit forecast is wskazania 8 will be rewritten code from the output of the first register 9 block prediction 8, i.e. the code in the previous conversion cycle To ai-1. Define the difference between the current and the previous value of the code=Ki-Ki-1. (1) In accordance with the linear prediction algorithm following the expected code value is defined as follows:i+1=Ki+. (2) Substituting (1) into (2), we obtain Ki+1=2Ki-Ki-1. (3) the formula (3) is performed using a subtraction unit 11, the value of Kiis fed to the first input of the subtraction unit 11 with the output of the first register BPR 9 with a shift by one digit toward the senior ranks. Thus implements the multiplication of Kion two. On the second input of the subtraction unit 11 is fed code with outputs of the second register BDP 10. The subtraction unit 11 can be implemented on the chip IP (Avanesyan, R., Levshin VP of Integrated circuits TTL, TTLS. The Handbook. - M.: Mashinostroenie, 1993. - S. 140).

It should be noted that the first inputs of the ROM 7 and the third inputs of the register serves 6 M high-order bits of the result of the calculation by the formula (3) from the output of the subtraction unit 11 (and respectively from the outputs of the block prediction 8, Fig.2). In the General case 1MN, where N is rasra the P. This will require a ROM 7, a significant volume. Given the inaccuracy of the prediction, it is reasonable to use a value of M less than N, i.e., an optimal selection procedure code to use to group the output codes whose values are close to each other. A specific value M determined on the basis of the accuracy of the prediction, the effectiveness of the selection procedure code and on the basis of constraints on the capacity of the ROM 7. Note also that when M<N, empty (Junior) third inputs of the register 6 is logic level zero.

The problem of constructing optimal matching code in the process of analog-to-digital conversion corresponds to the well-known problem of constructing optimal programs of diagnosis, i.e., the search control object only defective item (Paszkowski, C. the problem of optimal detection and search failures in CEA/ Under. editor I. A. Ushakov. - M.: Radio and communication, 1981. - C. 50-84). In this case it is necessary to find a unique code value that most closely matches the input to be converted to voltage. Let the algorithm predict the most likely next code value is set to 8 (1000). Then optimalprint code equal to 8 (1000). If the voltage on the DAC output 2 will be larger than the input voltage (UI<U), then the following must be checked code 6 (0110) - transition is on the left branch of the graph extending from the first vertex and is marked with 0. If the voltage on the DAC output 2 will be less than the input voltage (UI>UDAC), then the following must be checked code 10 (1010) - the transition is on the right branch of the graph extending from the first vertex and is marked with 1. Upon reaching the hanging vertices, or vertices, in which there is no left branch, the code selection process ends. As a result of the conversion is taken code shown in Fig. 3 in the rectangle (to which suit the arrows). In the rectangles to the right of the vertices of the graph indicates the delay for this code. Note that the codes closest to the most likely (e.g. codes 6, 7, 9, 10) can be obtained in fewer steps than code values, less likely (e.g codes 0, 1, 14, 15).

The contents of a memory ROM 7 for this procedure, the selection code shown in table.1.

Recruitment procedure code recorded in the ROM 7 in the form of a sequence of words. The addresses of the words listed in the second column "Address". The address value of p is of the addresses in the table.1 separate parts separated by spaces. The older part of the address is supplied from the output unit 8 predictions for this procedure code selection it has the same value. The middle part of the address (1 bit) is formed by the output signal of the comparison circuit 1. The younger part of the address code is received from the output of the register 6.

Each word has three fields. First the "Code" field contains the current code used in this step, the selection of the output code (in the table. 1 shows the decimal value of this code and in parentheses is its binary representation). The "Delay" contains a number that is proportional to the time response of the DAC 2 and the operation of the comparison circuit 1 for the appropriate code from the "Code" field (in this case assumed that this time is equal to the difference between the current code and the previous plus one operation of the comparison circuit 1). The "Sign of the end" specifies the time the end of the procedure code selection. Procedure code selection ends, if this field will contain the unit.

Optimal recruitment procedure code for the case when the most probable value of the code is 4 (0100), shown in Fig.4. The contents of the memory area of the ROM 7, the corresponding procedure of the selection code shown in table. 2.

Consider prozrachnogo ADC in this case, the quantization step is equal toU=10V/24=10V/16=of 0.625 V. This means that when applying to the input of the DAC-2 code, for example, equal to 4, its output will be a voltage UDAC=4of 0.625=2,5 V. Assume that the ADC input voltage UI=2,6 V. as block prediction is normal register (zero prediction).

Suppose also that the outputs of the block prediction 8 on the third inputs of the register 6 is supplied code 8 (1000). This means that in the previous conversion cycle, when using the zero prediction was obtained code 8 (1000). (When using a linear prediction code 8 (1000) can be obtained, for example, if the two previous cycles of the conversion were received codes 6 and 7 or 4 and 6, and so on). Code 8 (1000) will also be available on the first (highest) address inputs of the ROM 7, i.e., will be selected memory area of the ROM 7, where recorded recruitment procedure code for the case where the most likely value for the next cycle analog-to-digital conversion step code is 8 (1000).

In the counter 5 at the end of the previous conversion cycle should be recorded code, generally equal to the difference between the output of the code obtained in the previous cycle transformation, and code values that will be the first primantis the HHS program search (all bits of the block prediction 8 are connected to the first inputs of the ROM 7, i.e. M=N) and is used to zero the algorithm predictions, the content of the counter 5 should be equal to unity, because the code value on the input of the DAC 2 is not changed and there is no need to enter for DAC delay, it is only necessary to consider the delay of the comparison circuit 1. (When the unit is turned counter 5 should contain the maximum value and the register 6 is arbitrary - it can provide special schemes prior installation of Fig.1 is not shown).

In the initial state trigger 3 is in the zero state. To start the next cycle of the analog-to-digital conversion on the second input device "start" serves a short pulse, which is supplied to the first input of the register 6, it will be written to the code output unit 8 predictions, in this case, the code 8 (1000). Code number 8 (1000) output register 6 will arrive at the input of the DAC 2 and its output will be a voltage UDAC= 8of 0.625= 5V. This voltage will go to the second input of the comparison circuit 1, to the first input of which is filed convert the input voltage (for example made UI= 2,6 V). Since UI<Uat the output of the comparison circuit will be level appropriate logicist effects which trigger 3 will go in one state. The trigger output 3 set the level of logical units, which will be available on the second output device, signaling the beginning of the next conversion cycle. Single output trigger 3 will go also to the control input of the pulse generator 4, which will begin to generate rectangular pulses. The pulses from the first output of the pulse generator 4 will come to the first input of the counter 5. Because the content of the counter 5 is non-zero (as mentioned earlier, the content of the counter 5 at the beginning of the conversion cycle is equal to the unit), the signal of the logical unit with its output fed to its second input, i.e., the counter 5 is set to subtract. On the positive edge of the next pulse from the output of the pulse generator 4, the content of the counter 5 to be decreased by one and becomes equal to zero. During this time transients comparison circuit 1 will end. The zero level of the output of the counter 5 will arrive on the third (gate) input of the comparison circuit 1, fixing the value of the signal at its output in order to prevent it from changing when overwriting information from the ROM 7 in register 6 and the counter 5.

Thus, the address inputs of the ROM 7 is formed code 264 (1000 0 to 1000). At first Vya row in the table. 1). Because when the counter reaches zero, the 5 he goes into record mode, with the arrival of the next pulse from the first output of the pulse generator 4 to the first input of the counter it will be recorded code number 3 (0011) from the second outputs of the ROM 7. The content of the counter 5 will be different from zero and its output will be generated positive differential voltage at which the register 6 will be recorded code number 6 from the first outputs of the ROM 7. In Fig.3 this corresponds to the transition from code 8 to code 6 if UI<U.

DAC output 2 will be a voltage UDAC=6of 0.625=3,75 V, and since UI<Uat the output of the comparison circuit 1 will be a logic level zero. The address inputs of the ROM 7 set ID number 262 (1000 0 0110) and the first outputs of the ROM 7 code appears 4 (0100), and the second outputs code 3 (0011) (7th row in the table. 1). After the reset of the counter 5 code 4 (0100) will be recorded in the register 6, and the contents of the counter 5 will be equal to 3 (0011).

DAC output 2 you will see the voltage UDAC=4of 0.625=2,5 V. Since in this case UI>UDACat the output of the comparison circuit 1 will set the level of logical units. The address inputs of the ROM 7 set ID number 276 (1000 1 0100) and the first VIH) will be recorded in the register 6, and the contents of the counter 5 becomes equal to 1 (0001).

DAC output 2 you will see the voltage UDAC=5of 0.625=3,125 V. Since in this case UI<Uat the output of the comparison circuit 1 will be a logic level zero. The address inputs of the ROM 7 set ID number 261 (1000 0 0101) and the first outputs of the ROM 7 code appears 4 (0100), and the second outputs code 1 (0001) (6th row in the table. 1). After the reset of the counter 5 code 4 (0100) will be recorded in the register 6, and the contents of the counter 5 becomes equal to 1 (0001).

At the third output of the ROM 3 set the level of logical units (6th row in the table. 1, the column "Sign of the end") which will be sent to the third input register 3, so with the arrival of the pulse from the second output of the pulse generator 4 trigger 3 will go to the zero state. The trigger output 3 will be zero logic level, which will arrive on the second output device, signaling the end of another cycle of the analog-to-digital conversion. On the negative differential output of the trigger 3 in block 8 predictions will be written to the result of the last conversion, in this case the code is 4 (0100). When using the algorithm of zero prediction code 4 (0100) from the output of the block to pressoffice recruitment procedure code from another memory area of the ROM 7. The contents of a memory ROM 7 for the case when the most likely next code value is 4 (0100), are given in table. 2. Recruitment procedure code for this case in the form of the graph shown in Fig.4.

The zero level of the trigger output 3 will also suspend the operation of the pulse generator 4. The content of the counter 5 is equal to 1 (0001), i.e., the device will be ready for the next cycle analog-to-digital conversion.

Determine the conversion time for the ADC. In Fig.3 near the vertices of the graph (right) shows the values of the delays for each tested combination (latencies are enclosed in a rectangle). The value of delay is defined as the number of pulses which must come from the output of the pulse generator 4 to the counter 5 to test this code. It is equal to the value of the delays given in table. 1 for each code, plus one pulse necessary to overwrite the information from the ROM 7 in the counter 5 and the case 6. Given the above conditions and using the procedure of selection, the count of which is shown in Fig.3, the maximum delay will be, if the following output codes 0, 1, 14, or 15. So, code for 0 you will need to check codes 8, 6, 4, 3, 2, 1. The total delay will be 2+4+4+3+3+3´┐Żneed to check four of the code for 4-bit ADC. When checking each code uses a time interval equal to the maximum time of an output voltage of the DAC (i.e., the settling time when applying to the input of the DAC after the combination 0 a combination of 15). When using the pulse generator of the device, the time interval corresponding to the maximum time setting will correspond to 15 pulses. I.e., the conversion of conventional successive approximation ADC will be 154=60 pulses.

Thus, the proposed device allows to increase the conversion rate more than three times. For output codes that are close to the predicted conversion time is even less. So, for code 6 (0110) the conversion time will be 2+4+3=9 pulses.

Therefore, the proposed ADC can reduce the conversion time by applying optimal matching code and account as of the time of establishing the voltage at the DAC output, and codes from the previous conversion cycles.

Claims

Analog-to-digital Converter comprising a comparison circuit, the first input of which is fed to the input of the converted voltage the outputs of the register and are the first outputs of the device, the first input register of the second ADC input, the pulse generator, characterized in that it introduced a counter, a persistent storage device (ROM), the block prediction for selecting search process depending on the codes from the previous conversion cycles, the trigger, the first input connected with the second input device, the output is the second output device and connected to the first input of the block prediction and the input of the pulse generator, the first output of which is connected to the first counter input and a second output connected to the second input of the trigger, the second input of the counter is connected to its output, the third input of the comparison circuit and the second input register, the outputs of which are connected with the second inputs of the block prediction, the outputs of which are connected to third inputs of the register and to the first inputs of the ROM, the second input is connected to the output of the comparison circuit, the third input connected to the output of the register, the first outputs of the ROM is connected to the fourth inputs of the register, the second outputs to the third inputs of the counter, the third output to the third input of the trigger.

 

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