Analog-to-digital converter

 

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code. The technical result is to increase the performance of the ADC due to the conversion in two stages. The device comprises a comparison circuit, a DAC, a trigger pulse generator, counter, register, ROM, ADC reading. table 1. , 2 Il.

The invention relates to electrical and computer engineering and can be used to convert the analog voltage into the code.

Known N-bit ADC reading, containing the divider reference voltage, 2Nstrobing voltage Comparators (KN), the decoder, the XOR, the register (Fedorov, B. Taurus C. A. Chip DAC and ADC: operations, parameters, applications. -M.: Energoatomizdat, 1990. -S. 151, Fig.3.17).

The disadvantage of the ADC reading is rapidly increasing complexity with increasing capacity, because to build an N-bit ADC requires 2Nof voltage Comparators and a voltage divider containing the same number of the same resistance. At the same time, the ADC of this type provide maximum Bisti to offer is a successive approximation ADC, contains a comparison circuit (SS), at the first input of which is fed to the input of the converted voltage, and the output connected to the first input register of the successive approximation (RPA), the first outputs of which are connected to the inputs of the digital to analogue Converter (DAC) and are simultaneously outputs of the ADC, the DAC output is connected to the second input of the comparison circuit, the second input of the successive approximation register is the second ADC input, a third input connected to the output element And the second output to the second input of this element And, the first input of which is connected to the generator output clock pulses (Chernov Century, Device I / o analog information to digital systems of data collection and processing. - M.: Mashinostroenie, 1988. -S. 85, Fig.57. Functional diagram and the timing diagram of the ADC successive approximation). Successive approximation ADC is characterized by the following features. During code selection method is used half of the division. The conversion process always takes N clock cycles, where N is the ADC, and the duration of the transformation is TCR= NtDACwhere tDAC- time setting voltage on the DAC output when changing code on his whoodie on the input of the DAC zero after the maximum code for a given DAC), i.e., is not taken into account the different time of the output voltage at the DAC output for different codes.

The disadvantage of this device is a low speed, because it does not take into account the settling time voltage output digital to analogue Converter and the search is performed among all possible codes.

The technical result improved ADC performance by performing the conversion in two stages. The first step is "rough" conversion by the ADC reading low capacity, due to which narrows the search area in the second stage. The second stage involves the optimal logical procedure of selection of the output code in the selected area, taking into account the statistical characteristics of the signal and the temporal characteristics of the DAC (the settling time of the voltage at the output).

The technical result is achieved by the successive approximation ADC, containing a comparison circuit (SS), at the first input of which is fed to the input of the converted voltage from the first input device and the second input connected to the output of the DAC, the first and second inputs of which are the first outputs of the device, the second inputs of the DAC are connected to the outputs of the region is nausea device (ROM), ADC reading, the trigger, the first input connected with the second input device, the output is the second output device and connected to the input of the pulse generator, the output of which is connected to a second input of the trigger and the first counter input, a second input connected to its output, a third trigger inputs and the comparison circuit and the second input register, a first input device connected to the first input of the ADC is read, a second input connected to the trigger output, and outputs connected to first inputs of the DAC and the ROM, the second input of the ROM is connected to the output of the comparison circuit, third inputs connected to the output of the register, the first outputs of the ROM are connected with the third input register, the second output with the third inputs of the counter, and the third output to the fourth input of the trigger.

A structural scheme of the device differs from the known fact that it introduced a counter, a persistent storage device (ROM), ADC readout and trigger that are standard nodes analog and digital computers. As the trigger can be used with chip TV counter - IE, ROM - RE (Avanesyan, R., Levshin VP of Integrated circuits TTL, TTLS: a Handbook. - M.: Engineering and digital technology, their introduction, as well as the emergence of new functional connections between them and the existing units gives the chance to appear in the device to a new property. Namely, the ADC can reduce the conversion time of the measured value due to the fact that the transformation is performed in two stages. The first step is "rough" conversion by the ADC reading low capacity, due to which narrows the search area in the second stage. The second stage involves the optimal logical procedure of selection of the output code in the selected area, taking into account the statistical characteristics of the signal and the temporal characteristics of the DAC (the settling time of the input voltage). The optimal procedure code selection can be made using methods known in theory of automatic control and Troubleshooting (Paszkowski, C. the problem of optimal detection and search failures in CEA/ Under. editor I. A. Ushakov. -M.: Radio and communication, 1981. - 280 C.). Application of best practices, built taking into account the statistical characteristics of the signal, the possible retrieval of the output code (determined in the first stage) and temporal characteristics of the DAC (time setting), allows the the speed of the ADC.

Structural diagram of the ADC is shown in Fig.1, where 1 - comparison circuit, 2 - analog Converter (DAC); 3 - trigger; 4 - pulse generator; 5 - meter; 6 - register; 7 - persistent storage device (ROM); 8 - ADC reading.

Comparison circuit 1 is intended to compare the input to be converted voltage UIand voltage output DAC 2 - UDAC. If UI>UDACthe output of the comparison circuit 1 appears a signal corresponding to a logical unit, otherwise a logic zero. As the comparison circuit 1 uses strobing comparator when applying the zero level at its third (gate) input, the output voltage of the comparison circuit 1 is fixed. This is necessary in order to eliminate the change of the output signal of the comparison circuit 1 when overwriting information from the ROM 7 in the counter 5 and the case 6. Comparison circuit 1 can be implemented on the chip strobing of the comparator 521 SAZ (Bulychev, A. L. Analog integrated circuits: a Handbook / by A. L. Bulychev, V. I. Galkin, V. A. Prokhorenko. - Mn.: Belarus, 1994. -S. 382-383). DAC 2 is designed to convert a digital code supplied to its input, the corresponding output level of the analog voltage. When eto) is the code from the output of the register 6. The trigger 3 is designed for fixing the beginning and end of the conversion process. When submitting its first input pulse trigger 3 passes in one state and starts the conversion process. At the end of the conversion process, the trigger 3 is reset to the zero state by a pulse from the output of the pulse generator 4 (supplied to the second input of the trigger 3) for admission to the third input of the trigger 3 zero logic level from the output of the counter 5 and a single signal from the third output of the ROM 7. The pulse generator 4 is designed to synchronize the operation of the device. He starts feeding on its control input voltage corresponding to a logical unit, the output of the trigger 3.

The counter 5 is designed to generate a time interval corresponding to the time of establishing the voltage at the DAC output 2 for the current code. For this purpose, the counter 5 is written to a certain number and translate it in the subtraction mode. When submitting its first input pulses the contents of it decreases. Upon reaching the contents of the counter values of zero at its output is set to logic level zero, which signals the end of the specified time interval. A logic level zero output sci input of the counter 5 it is recorded information, submitted on its third (information) inputs. At the output of the counter 5 is set to the level of logical units, it goes in the subtraction mode and shape the next time.

As a counter 5 can be used with chip IE in subtractive mode. It should output transfer (R) connect to the input (L) (Avanesyan, R., Levshin VP of Integrated circuits TTL, TTLS: a Handbook. - M.: Mashinostroenie, 1993. - S. 199). Let for this code To thei(submitted to the DAC input) setup time of the output voltage of the DAC is Tiand the period of the pulses from generator 4 ist. Then for the formation of the time interval Tiat the counter you want to write code that is equal to NSC= Ti/t. When describing the operation of the device will assume that the delay is proportional to the difference between the previous code and the following (delay setting voltage output DAC 2) plus one pulse at the time of the comparison circuit 1. For example, if after the code 8 (1000) at the input of the DAC 2 is fed code 6 (0110), the counter 5 is necessary to record the number 3 (3=8-6+1).

Register 6 is designed to hold the younger razreda the W unit and the remaining bits are set to zero. On the positive front, the impulse applied to the second input of the register 6, it is written information submitted on its third input from the first outputs of the ROM 7.

ROM 7 is intended for storage of digital codes used in the procedure of selection of the output code corresponding to the input analog voltage UI. In ROM 7 also stores the values of the delays for all codes used (corresponding to the time of establishing the voltage at the DAC output 2).

ADC read 8 is designed for a preliminary "rough" conversion of the input analog voltage to reduce the search area in the second stage of the selection code. This uses the ADC reading small capacity with low complexity and cost.

The problem of constructing optimal matching code in the process of analog-to-digital conversion corresponds to the well-known problem of constructing optimal programs of diagnosis, i.e., the search control object only defective item (Paszkowski, C. the problem of optimal detection and search failures in CEA/ Under.ed. I. A. Ushakov. -M.: Radio and communication, 1981. -S. 50-84). In this case it is necessary nalnosti ADC (proposed device) is equal to 6, and with the help of ADC reading 8 are formed two senior level device. Let the first stage (using ADC reading) determined that the output code corresponding to the input voltage is in the range from 16 to 31 (i.e., the code on the output of the ADC reading 8 = 01). Then the optimal recruitment procedure code may have the form shown in Fig.2.

In accordance with Fig. 2 the first should be checked code, equal to 24, or in binary form - 01 1000 (upper two digits are generated by the ADC reading, separated by a space). If the voltage on the DAC output 2 will be larger than the input voltage (UI<U), then the following must be checked code 22 (01 0110) - transition is on the left branch of the graph extending from the first vertex and is marked with 0. If the voltage on the DAC output 2 will be less than the input voltage (UI>UDAC), then the following must be checked code 26 (01 1010) - the transition is on the right branch of the graph extending from the first vertex and is marked with 1. Upon reaching the hanging vertices, or vertices, in which there is no left or right branch, the code selection process ends. As a result of the conversion is taken code shown in Fig. 2 in pramugara. Note that some codes, for example 24, 22, 26, can be obtained in fewer steps than the values of some other codes, such as 16, 17, 30, 31. So it is possible to build a recruitment procedure code so that the codes, the probability of which above, had been in fewer steps.

Content of the ROM 7 for this procedure, the selection code shown in table. 1. Recruitment procedure code recorded in the ROM 7 in the form of a sequence of words. The addresses of the words listed in the second column "Address". Address value is given in decimal form, and binary (in parentheses). The address consists of three parts. In the binary representation of the address in the table.1 separate parts separated by spaces. Two senior level addresses come from the output of the ADC reading 8 for this procedure code selection they have the same value of 01. The middle part of the address (1 bit) is formed by the output signal of the comparison circuit 1. The younger part of the address code is received from the output of the register 6.

Each word stored in the ROM 7, has three fields. First the "Code" field contains the low-order bits of the current code used in this step, the selection of the output code (the table shows the decimal value of this code and in parenthesis it dwania of the comparison circuit 1 for the appropriate code from the "Code" field (in this case taken this time is equal to the difference between the current code and the previous plus one operation of the comparison circuit 1). The "Sign of the end" specifies the time the end of the procedure code selection. Procedure code selection ends, if this field will contain the unit.

In the last column of the table.1 shows the current values of the code used in the selection process of the output code. Each code consists of two parts, separated from each other by gaps. The older two digits are generated by the ADC reading, and the youngest four digits stored in the register 6.

Consider the operation of the device at the following source data. ADC - 6. ADC reading of 8 is equal to two. The input voltage range is 10 V To 6-bit ADC in this case, the quantization step is equal toU=10V/26=10V/64=0,15625 V. This means that when applying to the input of the DAC-2 code, for example, equal to 24, its output will be a voltage UDAC= 240,15625=3,75 V. Assume that the ADC input voltage UI=3,2 V.

In the initial state trigger 3 is in the zero state. To start the next cycle of the analog-to-digital conversion on the second I is the second digit is written to the unit, and the remaining bits are set to zero. In this case, since the bit width of the register 6 is equal to four, it will be recorded code 1000.

The triggering pulse from the second input device "start" will also be available at the first input of the trigger 3, under the influence of which the trigger 3 will go in one state. The trigger output 3 set the level of logical units, which will be available on the second output device, signaling the beginning of the next conversion cycle.

A positive differential voltage trigger output 3 will go also to the second input of ADC read 8 so that its output will freeze the code corresponding to the input voltage, served on the first ADC reading 8. This corresponds to the first stage of conversion: using ADC read 8 low bits is a "rough" translation and there are two senior level of the output code, in this case they are equal 01 (code 01 0000 corresponds to the voltage 160,15625=2,5 V, code 01 1111 corresponds to the voltage 310,15625=4,84 V, and according to the above assumption on the ADC input voltage UI=3.2 V).

At the input of the DAC 2 is submitted code number 24 (01 1000): two digit ADC output is read in the unit, and the rest are set to zero). DAC output 2 set the voltage UDAC= 240,15625=3,75 V. This voltage will go to the second input of the comparison circuit 1, the first input of which is filed convert the input voltage (for example made UI= 3.2 V). Since Ubx<Uat the output of the comparison circuit will receive a level corresponding to a logical zero.

Single output trigger 3 will go also to the control input of the pulse generator 4, which will begin to generate rectangular pulses. The pulses from the output of the pulse generator 4 will come to the first input of the counter 5. The content of the counter 5 original must be equal to 1 (when turning on the device, it is provided by a special schemes prior installation of Fig.1 is not shown). Because the content of the counter 5 is non-zero, the signal of the logical unit with its output fed to its second input, i.e., the counter 5 is set to subtract. After receipt of one pulse to the first input of the counter 5, its contents will be equal to zero. During this time transients comparison circuit 1 will end. The zero level of the output of the counter 5 will arrive on the third (gate) of itisi information from the ROM 7 in register 6 and the counter 5.

At the address inputs of the ROM 7 is formed code 40 (01 0 1000). Accordingly, the first outputs of the ROM 7 code appears in the number 6 (0110), the second output code number 3 (0011) and the third output is zero (9th row of the table.1). Because when the counter reaches zero, the 5 he goes into record mode, with the arrival of the next pulse from the first output of the pulse generator 4 to the first input of the counter it will be recorded code number 3 (0011) from the second outputs of the ROM 7. The content of the counter 5 will be different from zero and its output will be generated positive differential voltage at which the register 6 will be recorded code number 6 from the first outputs of the ROM 7. In Fig.2 this corresponds to the transition from code 24 code 22 (01 0110) if UI<U.

On the input of the DAC 2 is the code number 22 (01 0110), respectively, at the DAC output set voltage UDAC=220,15625=3,4375 V, and since UI<Uat the output of the comparison circuit 1 will be a logic level zero. The address inputs of the ROM 7 set code number 38 (01 0 0110) and the first outputs of the ROM 7 code appears 4 (0100), and the second output code 3 (0011) (7th row in the table. 1). After the reset of the counter 5 code 4 (0100) will be recorded in the register 6, and the contents of the counter 5 will be equal to 3 (0011) 200,15625=3,125 V. Since in this case UI>UDACat the output of the comparison circuit 1 will set the level of logical units. The address inputs of the ROM 7 set code number 52 (01 1 0100) and the first outputs of the ROM 7 code appears 5 (0101), and the second output code 2 (0010) (21st row in the table. 1). After the reset of the counter 5 code 5 (0101) will be recorded in the register 6, and the contents of the counter 5 becomes equal to 1 (0001).

Now on the input of the DAC 2 is the code number 21 (01 0101), respectively, at the DAC output will appear a voltageDAC=210,15625=3,28125 V. Since in this case UI<Uat the output of the comparison circuit 1 will be a logic level zero. The address inputs of the ROM 7 set code number 37 (01 0 0101) and the first outputs of the ROM 7 code appears 4 (0100), and the second outputs code 1 (0001) (6th row in the table. 1). After the reset of the counter 5 code 4 (0100) will be recorded in the register 6, and the contents of the counter 5 becomes equal to 1 (0001).

At the third output of the ROM 3 set the level of logical units (6th row in the table. 1, the column "Sign of the end"), which goes to the fourth input of the trigger 3, the third input is a logic level zero output of the counter 5. With the arrival of the pulse from the output of the pulse generator is who will be on the second output device, signaling the end of another cycle of the analog-to-digital conversion. On the first outputs of the device will set the final output code number 20 (01 0100). The zero level of the trigger output 3 will also suspend the operation of the pulse generator 4. The content of the counter 5 is equal to 1 (0001), i.e., the device will be ready for the next cycle analog-to-digital conversion.

Thus, in the proposed ADC the first step is "rough" conversion by the ADC reading (with high performance), which allows to reduce the number of analyzed code at the second stage of the selection code. When using double-bit ADC reading of the number of analyzed code at the second stage is reduced by 22= 4 times. Accordingly, not less than 4 times reduces the conversion time. In addition, in the proposed ADC is considered the time for establishing the voltage at the DAC output. The proposed device also allows for each area code (allocated to the first stage) to set their recruitment procedure codes, this area in the ROM is addressed by a code from the ADC output reading 8, admission to the upper address bits of the ROM 7.

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