Universal digital driver signals with continuous phase modulation

 

The invention relates to electrical engineering and can be used in the transmission systems of discrete data to form a signal with continuous phase modulation. The technical result - improving the accuracy of the generated signal with continuous phase modulation due to synchronization in time of the successive transformations of samples generated signal with boundary clock and symbol intervals. The device includes a shift register, a decoder for the current phase, the RAM of the current phase with the generator, RAM initial phase, the counter clock intervals and the frequency synthesizer. 1 C.p. f-crystals, 4 Il.

The invention relates to electrical engineering and can be advantageously used to generate a signal with continuous phase modulation in communication systems discrete information.

Known shapers signal with continuous phase modulation (CPM [1-5] , which allows to receive radio signals with different types of continuous phase modulation CPFCK, MSK, GMSK, TFM, GTFM.

These devices use digital modulators capable of forming a signal with continuous phase modulation (CPM, the next i-th order symbol 7.gif">3; ...(M - 1) - values that can be used with the i-th information symboli; g(t) is the symbol of the modulating signal (frequency pulse) duration LTwithL is an integer; Twith- the length of the information symboli; fnthe carrier frequency; h=p/q is the modulation index (p and q are integers);0- the initial phase of the signal (the first character signal); q(t) - law-of-phase (phase pulse) generated signal.

Duration LTcsymbol g(t) of the modulating signal and the corresponding phase response q(t) is called the length of the partial response.

In practice, the most often chosen modulation index h=1/2, in which conditions are q(t) = 0; q(LTc) = 1/2. (2)
These conditions satisfy all of the above signals with continuous phase modulation.

When the digital formation of character (1) signal with continuous phase modulation in known devices initially form a set of N samples of the phase of the symbol. Any n-th sample (n=0, 1,... N) phase formed of the i-th symbol (1) is used with regard to conditions (2):

where n = 0, 1 which will be formed in the sample values generated symbol, and then use d / a conversion in continuous time signal.

As a result of multiple sequential transformations of samples of signals in known devices on the borders of clock intervals occur transients, which reduces the accuracy of the generated signal.

Closest to the proposed set of features is a universal digital driver signals with continuous phase modulation [1], containing the shift register, the information input by the information input device and the output is connected to the information input of the decoder for the current phase, the clock input connected to the output of the counter clock intervals, and the output to the input of digital to analog generator whose output is the output device.

A disadvantage of the known device is the presence of transient processes on the borders of clock intervals defined by the clock pulses fed to the counter input clock intervals.

To eliminate this drawback it is necessary to strictly synchronize the moments of change of state digital to analog generator with boundary clock and symbol intervals. is reading phase modulation, containing the shift register, the information input by the information input device and the output is connected to the information input of the decoder for the current phase, the clock input connected to the output of the counter clock intervals, as well as analog generator whose output is the output of the device, put the RAM at the current phase, RAM initial phase and the frequency synthesizer, the first character of the output of which is connected to the control input of the RAM write initial phase, the second character output to the clock input of the shift register and setting the counter input clock intervals, the clock input of which is connected to the first clock output of the frequency synthesizer, the second clock output of which is connected to the control input of the entry RAM of the current phase, the output of which is connected to the analog input of the generator, and the input - output of the decoder, the current phase, the character input connected to the output RAM initial phase.

In Fig.1 shows the electrical structural diagram of the proposed universal digital driver signals with continuous phase modulation, and Fig. 2 is a timing diagram explaining his work. In Fig.3 shows an electrical block diagram of predlagaeyoy device on the elements of a discrete technology. In Fig.4 shows an electrical block diagram prototype [1].

Universal digital driver signals with continuous phase modulation (see Fig.1) contains a register 1 shift decoder 2 current phase, RAM 3 current phase, analog generator 4, a counter 5 clock intervals, RAM 6 initial phase and the synthesizer 7 frequencies. The output of register 1 shift through the decoder 2 current phase and RAM 3 current phase is connected to the analog input of the generator 4. The output of the RAM 6, the initial phase is connected to a character input decoder 2 current phase. The output of the counter 5 clock intervals connected with a clock input of the decoder 2 current phase. The first character of the output of the synthesizer 7 frequency connected to the control input of the write RAM 6 initial phase, his second character output to the clock input of the register 1 shift and installation of the meter inlet 5 clock intervals, the clock input of which is connected to the first clock output of the synthesizer 7 frequency, the second clock output of which is connected to the control input of the write RAM 3 current phase.

Works universal digital driver signals with continuous phase modulation as follows.

In the proposed device is (3) the n-th sample (n=0, 1,... N) initial phase and Delta phase:

where(i)0(0that...i-l- the initial phase of the i-th symbol;
(i)(nTd,i-L+lthat...i- the current increment the phase of the i-th symbol for the n-th sample.

The initial phase of the current i-th symbol is given (2) and (3)

in the proposed device is determined by using the RAM 6 initial phase, the current phase of the previous (i-1)-th symbol at the end of the last at t* = NTB= TC(n = N) by the rule

Therefore, to determine the initial phase of the current i-th symbol at a known initial phase of the previous (i-1)-th symbol is sufficient to know only L penultimate information symbolsi-Lthat...i-l.
The current increment the phase of the i-th symbol for the n-th sampling

is uniquely determined in the decoder 2 current phase generated by the counter 5 clock intervals, the number n of the current sample and the values of L last informazione increment phase for the N-th sampling taking into account the equality NTB=TC

When this current value of the phase according to (4), (5) and (8) subject to (2)

in accordance with (5) coincides with the initial phase of the next (i+1)-th symbol.

The operation of the proposed device provides the synthesizer 7 frequencies, generating the following sequence of pulses, the mutual position of which is shown in Fig.2:
- character sequence of pulses with a repetition period TCthe first character of the output (Fig.2, a);
sequence detainees character of the pulses at the second character output (Fig.2, b);
sequence of clock pulses with a repetition period TB=TC/N (N is an integer) on the first clock output (Fig.2, in);
sequence detainees clock pulses in the second clock output (Fig.2, g).

At the beginning of the work RAM 6 initial phase enter the value of0the initial phase of the generated signal. For this RAM 6 initial phase may have the appropriate information and control inputs.

During operation after the recording in the RAM 3 current phase values phase(i-l)(NTB,(i)0(0that...i-lthe current i-th symbol of the generated signal to the recurrent rule (8):
(i)0(0that...i-l) =(i-l)(NTB,0that...i-l).
The specified process control character pulses (see Fig.2, a), input control entry RAM 6 initial phase with the first character of the output of the synthesizer 7 frequencies.

Then for any symbol interval of duration TCon the character input decoder 2 current phase output RAM 6 initial phase enters the value of(i)0(0that...i-l) the initial phase of the current i-th symbol of the generated signal.

Detainees character pulses from the second character of the output of the synthesizer 7 frequencies arrive at the clock input of the register 1 shift and ensure the consistent input of an information symbolifrom the information input device.

Register 1 shift has L resporation the input of the decoder 2 current phase for the i-th symbol interval.

At the same time on the clock input of the decoder 2 current phase from the output of the counter 5 clock intervals receives a binary signal that takes N values of n* = 1, 2,... N-1, 0, and determines the corresponding number n = 1, 2, . . . N-1 N clock interval of duration TBwithin the duration of TCcharacter. The specified number n* is received at a clock input of the counter 5 bit clock periods of clock pulses from the first clock output of the synthesizer 7 frequencies. While detained character pulses from the second character of the output of the synthesizer 7 frequency supplied on the installation counter input 5 clock intervals, confirm its zero state at the boundaries of the symbols generated signal at n* = 0 (n = N, t* = TC).

Using decoder 2 current phase define phase values(i)(nTB,0that...i) generated signal for N times, following each other through the clock time interval TBwithin the duration of TCinformation symbol. The value of (3) every n-th sample (n = 1,... N-1, N) phase i-th symbol (1) is uniquely determined by the set of values of L last /img.russianpatents.com/chr/934.gif">(i)0(0that...i-l) the initial phase at the beginning of this symbol (at t* = 0, n* = 0) and the value of n* binary signal, determining the number n of the given reference.

Record the values of(i)(nTB,0that...ithe current phase in the RAM 3 current phase is carried out using detainees clock pulses received at its control input record from the second clock output of the synthesizer 7 frequencies.

Then the set of N samples (n = 1, 2,... N-1, N) phase(i)(nTB,0that...i) the i-th symbol using the analog generator 4 is converted into a continuous time symbol S(i)(t,0that...i) generated signal (1) with continuous phase modulation.

Universal digital driver signals with continuous phase modulation can be implemented on known functional elements.

Decoder 2 current phase may be in the form of a ROM, a set of values of all input signals which is the address with the carried out analog generator 4 shown in Fig. 4, which shows an electrical block diagram prototype [1]. Analog generator 4 includes (see Fig.4) drive 6, the ROM 7 samples (samples) of the harmonic signal, d / a Converter 8 and the filter 9 of the lower frequencies. Recommendations on the choice of parameters and operation modes of the analog generator 4 is given in [6].

In the particular case of implementing the universal digital driver signals with continuous phase modulation on the discrete elements of technique, as shown in Fig.3, the decoder 2 current phase contains consistently enabled ROM 8 current phase and the adder 9, additional input and output which are, respectively, the character input and output of the decoder, the initial phase information and the clock inputs of which are respectively the first and second inputs of the ROM of the current phase.

The device allows you to generate a signal with continuous phase modulation with tight synchronization in time of the successive transformations of samples generated signals and changes the state of the analog generator with boundary clock and symbol intervals, which allows to improve the accuracy of the generated signal and prevent the loss of informatiion-35, 4, April 1987, pp. 458-462.

2. T. Aulin, N. Rydbech, C. E. Sundberg. Transmitter and receiver structures for M-ary partial response FM. IEEE Trans. on comm., vol. com-26, 5, May 1978, pp. 534-538.

3. S. Ray. Generation of serial CPMFSK signal. Proc. IEEE, vol. 72, 1, Jan. 1984, pp. 129-129.

4. C. B. Decker. On the application of tamed freguency modulation to various field of digital transmission. Proc. 1980 Int. Zurich Seminar on Digital Commun., Zurich, Mar. 1980, pp. A1.1 - A1.10.

5. H. Suzuki, Y. Yamas, K. Momma. Single chip baseband waveform generation CMOS LSI for a quadrature-type CPM modulator. Electron. Lett., vol. 20, 21, Oct. 1984, pp. 875-876.

6. J. Tierney, C. Rader, And B. Gold. A digital frequency synthesizer., IEEE Trans. on Audio Electroaconst., vol. AU-19, 3, Mar. 1971, pp. 48-56.


Claims

1. Universal digital driver signals with continuous phase modulation, containing the shift register, the information input by the information input device and the output is connected to the information input of the decoder for the current phase, the clock input connected to the output of the counter clock intervals, as well as analog generator whose output is the output of the device, characterized in that the input RAM of the current phase, RAM initial phase and the frequency synthesizer, the first character of the output of which is connected to the control input of the RAM write initial phase, the second character output to the clock input of the shift register and the installation of the entrance counter tectosilicate which is connected to the control input of the entry RAM of the current phase, the output of which is connected to the analog input of the generator, and the input - output of the decoder, the current phase, the character input connected to the output RAM initial phase.

2. Universal digital driver signals with continuous phase modulation under item 1, characterized in that the decoder current phase contains consistently enabled ROM the current phase and the adder, additional input and output which are, respectively, the character input and output of the decoder, the initial phase information and the clock inputs of which are respectively the first and second inputs of the ROM of the current phase.

 

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