Device control and management for communication systems with dynamic resource allocation of relay

 

The invention relates to electronic devices adaptive management plan for the distribution of power and time resources of the relay link (RL) in communication systems with dynamic resource allocation of relay. The technical result of the invention is to expand the functionality of the device control to enable optimal management of distribution plan and a training resource PC when performing the specific requirements on quality of service. In the control device, containing connected in series register and decoder, added block detection signals, the group of keys, a group of counters, counter, first and second groups accumulative adders, accumulating adder, a group of inverters, the device forming clock pulses, the element group delay, group of decoders, the first, second and third blocks averaging the first and second Comparators, the group of registers, the control microprocessor. 1 Il.

The present invention relates to electronic devices adaptive management plan for the distribution of energy ing and control in communication systems with dynamic resource allocation of relay SS with PID).

Known devices of the control and management of the closest to the essence of the technical solution is the device described in and.with. The USSR 311600, MKI N 04 3/46, 1990, containing connected in series register and decoder. The disadvantage of this device is that it is designed to work on a fixed resource PC, but its functionality is limited to the regulation of access applications.

The technical result of the invention is to expand the functionality of the device control to enable optimal (from the point of view of efficiency of use) management plan of allocation and training resource PC when performing the specific requirements on quality of service.

The invention consists in that the control device containing connected in series register and decoder, added block detection signals, the group of keys, a group of counters, counter, first and second groups accumulative adders, accumulating adder, a group of inverters, the device forming clock pulses, the element group delay, group of decoders, the first, second and third blaricum group of inputs of the block detection signals, numerically equal to the number of units of a resource (channel) PC, is the first information input device, and the first inputs of the group of registers, the number of which corresponds to the number of subscriber terminal (AT), are the second input device, the output power detection signals connected to respective inputs of the counter, with the inputs of the respective inverters and the first inputs of the respective keys, the first output of the device forming clock pulses is connected with additional counter input and the second input key, the second output of the device forming clock pulses is connected with the second inputs of the respective accumulative adders of the first and second groups, with additional input is accumulating adder, a second input of the control microprocessor and the second input of the third block averaging, the key outputs connected to first inputs of respective counters, the outputs of the inverters are connected to second inputs of respective counters, with the first inputs of the respective decoders, with the inputs of the respective delay elements and to the corresponding inputs accumulating adder, the outputs of the counters are connected to first inputs from the modern to the corresponding inputs of the first block averaging, the output of the accumulating adder is connected to an additional input of the first block averaging, the output of the first block averaging is connected to the first input of the second comparator, the outputs of the delay elements are connected to second inputs of the respective decoders, the outputs of the decoders are connected with the first inputs of the respective accumulative adders of the second group, the accumulating outputs of the adders of the second group are connected to the corresponding inputs of the second block averaging, the output of the second block averaging is connected to the third input of the control of the microprocessor, the output of the counter is connected to the first input of the third block averaging, the output of the third block averaging is connected to the first input of the first comparator, the output of the first comparator is connected to the fourth input of the control of the microprocessor, the output of the second comparator is connected to the fifth input of the control of the microprocessor, the outputs of registers connected to respective first inputs of the control of the microprocessor, the first output of the control microprocessor connected to the second inputs of registers, the second output control mikroprocesorem input of the second comparator, the fourth group of control outputs of the microprocessor, the number of which corresponds to the number of serviced AT an output device.

The drawing shows a structural diagram of the device control and management for communication systems with dynamic resource allocation of relay.

The device includes: a detection unit signals (1), the group of keys (21... 2R), a group of counters (31. ..3R), counter (18), the first (41...4R) and second (101. . . 10R) group accumulative adders, accumulating adder (8), a group of inverters (71...7R), the processing unit clock pulses (6), a group of delay elements (121...12R), a group of decoders (111...11R), first (5), second (9) and third (17) blocks averaging, the first (15) and second (16) of the Comparators, the group of registers (131...13M), the control microprocessor (14).

The device operates as follows. Outputs of equipment temporary sealing and separation of the channels at intervals equal to the duration subbarow, to corresponding inputs of unit 1 receives signals PC. In the block 1 by the method of matched filtering is detect airway channels or logical units (in case of detection of the useful signal PC), or a logical zero (in the case of failure to identify the useful signal). Next, on the basis of the obtained data about the presence or absence of useful signal PC for each of the R channel, is parallel to the definition of medium intensity values of receipt of applicationstime of service, the number of concurrent requests.

Determining values ofoccurs as follows. Signals of logical units with outputs of unit 1 open the appropriate keys 21...2Rand to the inputs of respective counters 31...3Rstarts flowing sequence of clock pulses with a frequency fT. Reading respective counters occurs simultaneously with the reset signal of the logical unit from the output of the corresponding inverter 71...7Rgenerated when a loss of signal of the logic unit at the respective outputs of the block 1, which indicates the completion of service requests in the channel. The counters in parallel binary code received at the inputs of the respective accumulative adders 41H<foutput device forming clock pulses 6. Simultaneously with the reading accumulative adders 41. ..4Rto the input unit 5 receives evidence is accumulating adder 8, numerically equal to the number of serviced requests for all R channels during the observation time (the period of the pulse repetition frequency fH).

is determined as follows. The signal of the logic zero outputs of the respective inverters 71...7Rformed in case of detection of useful (information) signals in the respective channels block 1, proceed to the first inputs of the respective decoders 111...11Ron the second input of which receives signals from the outputs of the same inverters 71...7Rdelayed by respective delay elements 121...12Rfor a time equal to the duration of Subhadra. The output of the decoder signal of the logic unit is formed only if the previous (delayed) signal corresponds to a logical unit, i.e., the appearance at the output of the corresponding decoder signal of the logic unit certificate which each of R channels at the time of observation, equal to the repetition period of pulses with a frequency fHis determined by the indications of the corresponding accumulative adders of the second group 101...10R. The average value of the intensity of receipt of applicationsduring the observation time is determined in the second block averaging 9.

Determining values ofoccurs as follows. Signals of logical units with outputs of block 1, which is formed in case of detection of the information signal in the corresponding channel of the PC, proceed to the appropriate inputs of the counter 18, which provides a parallel account of the signals of the logical units at the outputs of block 1 in each step. Simultaneously, the counter 18 in a parallel binary code is read in the third block averaging 17. When it arrives at the second input unit 17 from the output of block 6 of the signal frequency fnin the block 17 is a calculation of the average during the observation period the number of concurrent applications in a single stroke.

The values of the signals at the outputs of blocks 5, 9, 17 are updated with a frequency fH.

The inputs of the registers 131...13Mthe control channels are received state information AT: inteno the i-th priorityi, the number of affected system EW enemy units resource input AT rp. Connect the outputs of the registers 131...13mto the input of the control microprocessor 14 determines priorities AT assigned to the appropriate registers.

The first comparator compares the value ofcalculated by the block 17, with a valid value calculated Manager of the microprocessor.

The second comparator compares the value ofcalculated unit 5, with a valid value calculated Manager of the microprocessor.

All elements of the proposed device can be implemented on modern element base.

The use of the proposed device will ensure the maximum efficiency of resource PC in the conditions of non-stationary traffic and the impact of the REB opponent when performing the specific requirements on quality of service.

Claims

Device control and management for communication systems with dynamic resource allocation of relay containing serially connected registers and a decoder, characterized in that Thu is which group accumulative adders, accumulating adder, a group of inverters, the device forming clock pulses, the element group delay, group of decoders, the first, second and third blocks averaging the first and second Comparators, the group of registers, a control microprocessor, and a group of inputs of the block detection signal is numerically equal to the number of units of a resource (channel) relay communication is the first information input device, and the first inputs of the group of registers, the number of which corresponds to the number of subscriber terminals, the second input device, the output power detection signals connected to respective inputs of the counter, with the inputs of the respective inverters and the first inputs of the respective keys, the first output of the device forming clock pulses is connected with additional counter input and the second input key, the second output of the device forming clock pulses is connected with the second inputs of the respective accumulative adders of the first and second groups, with additional input is accumulating adder, a second input of the control microprocessor and the second input of the third block averaging, the outputs of the respective counters, with the first inputs of the respective decoders, with the inputs of the respective delay elements and to the corresponding inputs accumulating adder, the outputs of the counters are connected with the first inputs of the respective accumulative adders of the first group, the accumulating outputs of the adders of the first group are connected to the corresponding inputs of the first computing unit averages the output of the accumulating adder is connected to an additional input of the first block averaging, the output of the first block averaging is connected to the first input of the second comparator, the outputs of the delay elements are connected to second inputs of the respective decoders, the outputs of the decoders are connected with the first inputs of the respective accumulative adders of the second group, the accumulating outputs of the adders of the second group are connected to the corresponding inputs of the second block averaging, the output of the second block averaging is connected to the third input of the control of the microprocessor, the output of the counter is connected to the first input of the third block averaging, the output of the third block averaging is connected to the first input of the first comparator, ora is connected to the fifth input of the control of the microprocessor, the outputs of registers connected to respective first inputs of the control of the microprocessor, the first output of the control microprocessor connected to the second inputs of registers, the second output of the control of the microprocessor is connected to a second input of the first comparator, the third output of the control microprocessor connected to the second input of the second comparator, the fourth group of control outputs of the microprocessor, the number of which corresponds to the number accepted is the output device.

 

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