Ultrahigh-speed surenthiran bimap ram on the avalanche transistors

 

(57) Abstract:

The invention relates to devices and structures integrated microelectronics, in particular to an integrated static memory cells and memory devices BIS and computers. The technical result is a micro-power mode consumption static capacity (units, tens NW), acceptable noise immunity, high operating frequencies. The invention provides a bistable cells avalanche transistors, managing the p-MOS transistor, the bit and word bus, the n-MOS transistor is read, the current generator. 2 S. p. f-crystals, 8 ill.

This invention relates to devices and structures integrated microelectronics, in particular to an integrated static memory cells and memory devices (RAM) BIS and computers.

The fundamental problem of development element base BIS and the computer is to increase the level of integration of devices dynamic and static memory, increasing the packing density of the bistable cells (BOJ), decreasing the size of the BOJ, the number of working tires, as well as reducing power consumption BAA RAM increase their load capacity and the associated system twoset dramatically reduce the size and working area BOJ, however, the problem of increasing the operating frequency in the further reduction and power consumption remains critical for prospective ultravis (UBIS).

The increase in operating frequency of the microprocessor (MP) CMOS UBIS up to 300-600 MHz, however, the price increase in power consumption up to 30-80 W/crystal exacerbated the problem of the gap in performance logical MP systems and dynamic storage devices (DOSE, DRAM), the working frequency is defined as F(DOSE)=1/sampling time. To avoid loss of system performance perspective processor globalsummary and nanoelectronic KBI-KLIKTOP/CMOS UBIS for a wide class from personal computers to supercomputers with workers gigahertz frequencies, there are two possible options for development. First, the use of significantly more high-speed architectures DOSE - SDRAM, RAMBUS, SYNC LINK implemented technology deep submicron. Secondly, the use of standard cost-effective capacity and footprint deep submicron implementations static cache RAM (SRAM) for advanced CMOS UBIS. Thirdly, the search for new low power and footprint deep submicron implementations with the measures at (BOJ) with avalanche transistors and with the control MOS keys.

Despite the significantly less attention in the literature and the flow of R & d on ultra-fast microprocessor systems, third alternative development seems very promising, opening up immense opportunities close-Packed cache memory technologies for deep submicron when creating the newest types of General-purpose computer with subligaculum operating frequencies.

Thus, the known standard two-dimensional and three-dimensional BOJ DOSE on a single MOS device and one capacitor memory one bit of information, which are characterized by very high density layout, but low speed and use of unwanted regeneration cycles stored information. Known static RAM on the trigger THEMSELVES with cross-connections made two transistors with high resistance collector loads, or four MOS transistors (two CMOS inverters), containing, as two key - MOS transistor selection connected with inputs of the inverters. The data THEMSELVES and the actual RAM have a low density composition at a sufficiently high speed.

To try to realize ultra-high density to ragment RAM, chosen as a prototype, closest to the proposed facility design solutions. contains bistable cell on the avalanche transistor, the base of which is connected to the drain of the control of the p-MOS transistor, the source of which is connected to the bit line and the gate - code bus, and the emitter of the avalanche transistor is connected to the common bus and the collector - source of collector voltage.

The potential of this type are THEMSELVES large enough: 1) when storing information in them unlike the BOJ DOSE almost no interference from ground leakage currents of MOS devices, 2) is implemented ultra-high density layout, for a 1 micron technologies THEMSELVES occupied an area on the crystal just 8.58 μm2[1] . At the same time, the data THEMSELVES are characterized by low system performance and considerable power consumption in the storage mode "1", about 0.45 mW. Reduce static power consumption by the BOJ and system organization SRAM cache memory while maintaining the high potential performance remain open.

To increase the degree of integration and performance perspective a static RAM avalanche transistors, competitive on the totality of pairs is maintaining high load capacity and low power consumption for micro-power high-speed UBIS RAM.

The objective of the invention is the creation of OURSELVES and fragments of RAM on the avalanche transistors, providing micro-power mode consumption static capacity (units, tens NW), acceptable noise immunity, high working frequency, reduced working space malokomplektnoj THEMSELVES for close-Packed UBIS. Additional objectives, whose achievement of sferisterio and sorbitrate UBIS to declare RAM are more significant reduction in chip area when implementing combined functionally integrated BICMOS structures, as well as providing a reduction in the chip area required for busbar connection units and cells and power distribution.

This task is achieved by the fact that: 1) ultra-fast surenthiran BIMAP RAM on the avalanche transistors containing bistable cell on the avalanche transistors, the base of each of which the cell is connected to the drain of the control of the p-MOS transistor, the source of which is connected to the bit line and the gate - with-word bus, characterized in that the avalanche transistor is made in the form duemilanove transistor, the collector of which is connected to a source of strain is BEGO for a group of cells of the first n-MOS transistor is read with the relevant circuits bias voltages at the source and the gate, and the second emitter avalanche transistor is connected to the bus of the first current generator and the total runoff for a group of cells of the second n-MOS transistor of the first current generator with the respective bias circuits of the gate voltage and the source; 2) ultra-fast surenthiran BIMAP RAM on the avalanche transistors containing bistable cell on the avalanche transistors, the base of each of which the cell is connected to the drain of the control of the p-MOS transistor, characterized in that the avalanche transistor is made in the form duemilanove transistor, the collector of which is connected with the word bus and shutter control of the p-MOS transistor, the channel which is isolated from other active regions of the devices, the first emitter is connected to bit bus, the output of a cell and the total runoff for a group of cells of the first n-MOS transistor is read with the relevant circuits bias voltages at the source and the gate, and the second emitter avalanche transistor is connected to the bus of the first current generator and the total runoff for a group of cells of the second p - MOS transistor of the first current generator with the respective bias circuits of the gate voltage and the source; 3) the device according to PP.1,2, characterized in that bit bus is connected to the leader of the reference transistor, the collector of which is connected to the output through a resistor with a common bus connected to the collector of the input transistor and the base of the reference transistor to a source of variable reference voltage.

The invention and its distinguishing from the prototype signs are unique opportunities to ensure sorbitrate in micro-power mode, high noise immunity and health BOJ bipolar durametric avalanche transistors used in the circuitry of the emitter follower, where the effect of the effective zero base current and the associated increase of current transfer ratio base resistance nor give any contribution in the loss of system performance is the fastest recharge load capacity (bits bus and others). Implemented in THEMSELVES and all RAM is the principle of functional integration - combining workspaces appliances and tires: bit output, word and power supply allows to reach the super dense packing of OURSELVES, is comparable with the density achieved in the DOSE. This also contributes to the use for many BOJ single generators and n-MOS transistor discharging that by providing small areas in snitz GHZ micro-power mode units watt THEMSELVES. Compromise provide the required noise immunity in the high range of operating frequencies, implemented using input in RAM threshold device on the switch current with a variable threshold as a variable reference voltage allows to realize the high potential of the system performance, noise immunity and reliability of static surenthiran RAM.

Review the list of figures, graphics, and specific examples of the requested RAM according to the paragraphs of the invention in the form of a functionally-integrated structural embodiment of the BOJ in the crystal claims.

In Fig.1 shows the principle of the generalized scheme of the main snippet BOJ 1 ultra-fast verhinderung BIMAP RAM on avalanche duhemian transistor 2, and its base 3 is connected to the drain of the control of the p-MOS transistor 4, source 5 which is connected to bit bus 6, and the shutter 7 - with-word bus 8. The collector 9 duemilanove transistor 2 is connected to the voltage source 10 and channel 11 of the p-MOS transistor 4. The first emitter 12 avalanche transistor 2 is connected to bit bus 6, the cell output and the drain of the first n-MOS transistor is assumed to be 2 connected to the bus 15 total for a group of cells of the first current generator and the drain of the second n-MOS transistor 16 with the respective bias circuits of the gate voltage and the source.

In Fig.2 shows a modified scheme of the main snippet BOJ 1 ultra-fast verhinderung BIMAP RAM on avalanche duhemian transistor 2. The collector 9 duemilanove transistor 2 in each cell connected to the word bus 8 ( combined bus voltage source 10), the shutter control of the p-MOS transistor 7, channel 11 which is isolated from other active areas of the devices. The first emitter 12 avalanche transistor 2 is connected to bit bus 6, the output of a cell and the total runoff for a group of cells n-MOS transistor 13 discharge with the appropriate circuit bias voltages at the source and the gate, and the second emitter 14 of transistor 2 is connected to the bus 15 total for a group of cells of the first current generator and the drain of the second n-MOS transistor 16 with the respective bias circuits of the gate voltage and the source.

In Fig. 3 illustrates the design of ultrahigh-speed verhinderung BIMAP RAM on the basis of the technical solutions THEMSELVES (Fig.1) using a threshold device on the current switch. Bit bus 6 is connected to the base input of transistor 17 of the current switch, the emitter of which is connected to the current generator 19 and the emitter of the reference transistor 18, call the Torah 17, and the base - with a source of variable reference voltage 21.

In Fig. 4 illustrates the design of sorbitrate verhinderung BIMAP RAM on the basis of the technical solutions THEMSELVES (Fig.2) using a threshold device on the current switch. Bit bus 6 is connected to the base input of transistor 17 of the current switch, the emitter of which is connected to the current generator 19 and the emitter of the reference transistor 18, the collector of which is connected to the output through the resistor 20 with a common bus connected to the collector of the input transistor, and the base - with a source of variable reference voltage 21.

The device in Fig. 1 operates as follows. Using MOS 4 and 13 keys select mode BOJ to write and read, respectively. In reverse biased collector-base junction of the transistor 2 is avalanche multiplication in the collector current. When a reverse collector voltage Ua incremental avalanche collector current offset component diffusion current recombination base of the transistor 2, which leads to a zero base current of the transistor. This mode corresponds to the stored "1" THEMSELVES. Storing "0" is in full locking of the transistor 2. In the first fat emitter; in the second case, the potential of the base is equal to zero and the through current is zero (except for leakage). In contrast to the purely dynamic memory elements considered THEMSELVES (Fig.1) during storage can compensate for the constant interference of the type of leakage the greater the value, the more the through current in the storage mode "1".

In the recording mode in the BOJ is unlocking input key on MOS device and setting of the data bus logic level corresponding to the fixed voltage at the base of the transistor 2. When this occurs, recharge mainly collector barrier capacitance through the resistance of the input key on the MOS device. Moreover, in contrast to the dynamic element, where for long-term storage it is necessary to use a large storage capacity, this capacity is much less, leading, first, to save space on the chip and, secondly, to reduce the time it recharges. When reading information are unlocking output switch on the MOS device. While on active front BOJ provides recharge load capacity mode emitter follower (EP) with a very large effective conversion gain of the current mode effective Nuevo is relative to the voltage U (deviation voltage emitter-base from landline) and an output current I can be approximated by the equation:

I=I0[EXP(U/It)-1], (1)

where I0- static emitter current. The voltage deviation load capacityLthe same absolute value with U and has the opposite sign. Therefore, taking into account (1) for the transition process we have the following relation:

CLdU/dt=-I=-I0[EXP(U/(It)-1]. (2)

In this case U(0) = Ul. Let time tk such that the voltage U has dropped to the k-th part of the UL, i.e., U(tk)=kULthen the relation (2) can be converted to the form for the time-based switching level logical 1/2 drop

t(1/2)=T0EXP(-m/2)/m=t0EXP(-m/2). (3)

This is a little exponentially with increasing values of the logical difference. For example, if Ulequal to 0.4 V, m is approximately 15 and EXP(-m/2) is equal to 46(10-4), i.e. a decrease in t1/2 more than 4 order. The value of tk can be written differently:

tk=(T0EXP(-km)/m=CL(It/Ik). (4)

Therefore, tk (4) can be interpreted as the characteristic time of recharge load capacity in a small signal through the differential resistance of the emitter junction when current Ik. For large values of U and high currents may be that the main role is played not the emitter junction, and ballast coprative base resistance, reduced In time, which in turn consists of the base resistance and the output resistance of the circuit sets the signal. Effective effective zero base current and the associated increase In the base resistance does not give any contribution.

We will formulate a number of requirements signals on all tyres fragments RAM shown in Fig.1,3. In the storage mode and write on the bus 10 is set to 3 V supply, the reading mode of the cells that are connected to this bus, this bus output voltage (increased by 1.2 In). In the storage mode and the read column BOJ for the private key to the gate 7 of the p-MOS transistor 4 is supplied with a high voltage. In write mode, the column BOJ on the shutter 7 of the p-MOS transistor 4 is supplied to the low voltage. For bit bus 6 in the storage mode is supported voltage EP corresponding to a logical zero when read. In record mode and read the key on the transistor 13 is locked, when writing on the bus is set to the voltage on the base 3 of the avalanche transistor 2 during storage of the recorded values. For bit bus 6 when reading the recorded zero on it implements a low voltage of less than Eon - reading will be more NAIA working tires due to combination of bus 8 (Fig.1) bus 10,which will increase integration potential BOJ just RAM. In the storage mode and the read voltage on the bus 10 is identical to the voltage on the bus 10 schemes in Fig.1, POS.3. In write mode, the bus 10 is supplied to the low voltage. The principle of operation of the circuits of Fig.2, 4 is identical to the principle of operation of the circuits of Fig.1, POS.3.

The inclusion threshold device (on bit bus BOJ) on the switch current is performed on the transistors 17 and 18, by setting the reference voltage 21 we set the level of detection of the read signal on bit bus. This is a tradeoff provide the required noise immunity and high range of operating frequencies, which makes it possible to realize the high potential of the system performance, noise immunity and reliability of static surenthiran RAM.

In Fig.5 presents a cross-section of functionally-integrated integral design of the two BOJ with a dielectric insulation for circuit solutions of 1.3. A base region of a bipolar transistor 2 connected with the drain region 4, the region of the collector 9 is combined with the channel region 11 of the p-MOS key. Columns of cells separated by grooves filled with oxide 22, all cells of a column have a common collector 9 (signalground bus 10). In the third direction Z in blockley to the bus 15. All the emitters 12 strings THEMSELVES are connected to bit bus 5. Word bus 8 generates the gate 7 of the p-MOS key.

Entire the application of a new ultrahigh-speed circuitry, micro-power THEMSELVES (Fig.1, 3) was modeled for the technology of 0.15 μm and functionally-integrated designs THEMSELVES on duhamic-turn the transistor (Fig. 5). With the help of adequate tools for the numerical two-dimensional device and circuit simulation [2] the analysis of performance and capacity, as well as physical limitations THEMSELVES on the scaling of avalanche transistors in micro-power mode RS = 0.1-10 NVT. In Fig.6 presents transients when reading from the BOJ at various load capacities. In Fig.7, 8 presents the dependence of time delay on the value of the detection threshold Tu read the output potential (Fig.6) for different capacities and load capacity for different threshold voltage Uon (and specified levels of noise immunity). To increase the integration of UBIS RAM should be possible to reduce the static power THEMSELVES. Reduce static pass-through current in the BOJ is carried out by reducing the current of the current generator to the n-MOS transistor 16. You can huts the first voltage, sounds when reading. Reducing static current I0limited by leakage currents IV, respectively, it is necessary that I0>>IV and not lost information in THEMSELVES. For static capacity BOJ less than 0.3-1 NRT, under the proposed hierarchical Gigabit architectures static RAM achievable f=1/Dostupa over 3-5 GHz, RS(t (BOJ))<2 10-19J.

Technical and economic effect of the invention is to significantly increase system performance micro-power options surenthiran memory cells of a static RAM UBIS, as well as job opportunities fragments of RAM at acceptable noise immunity, which is very important when building an ultra-fast UBIS for future microprocessor, super computer of higher generations, working with operating frequencies in units of tens of GHz for intelligent systems terrestrial and space-based.

Sources

1. Sakui, K., Hasegawa T. et. al. A New Static Memory Cell Based on the Reverse Base Current Effect of Bipolar Transistors.- IEEE Trans., V. ED-36, pp.125-127 (prototype).

2. Bubelnikov A. N., Chernyaev, A. C. Instrument-circuit modeling in CAD BIS. - Association of developers of CAD BIS, TREI, Taganrog, 1992.

1. Sorbitrate the different transistors, the base of the avalanche transistor in each bistable cell group is connected to the drain of the control of the p-MOS transistor, the source of which is connected to the bit line and the gate - with-word bus, characterized in that the avalanche transistor in each bistable cell group is made in the form duemilanove transistor, the collector of which is connected to a voltage source and channel control p-MOS transistor, a first emitter connected to bit bus, the output of bistable cells and total runoff for a group of bistable cells n-MOS transistor is read with the relevant circuits bias voltages at the source and the gate, and the second emitter avalanche transistor connected to the current generator.

2. Ultrahigh-speed surenthiran BIMAP RAM on the avalanche transistors containing a group of bistable cells in avalanche transistors, the base of the avalanche transistor in each bistable cell group is connected to the drain of the control of the p-MOS transistor, the source of which is connected to bit bus, characterized in that the avalanche transistor in each bistable cell group is made in the form duemilanove transistor, the collector of which is connected with the word line power source and C the initial emitter avalanche transistor is connected to bit bus, the output of bistable cells and total runoff for a group of bistable cells n-MOS transistor is read with the relevant circuits bias voltages at the source and the gate, and the second emitter avalanche transistor connected to the current generator.

 

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