Adc with periodic adjustment of the dc component

 

(57) Abstract:

The technical solution relates to digital measuring technique and can be used in ADC with periodic adjustment of zero with a large dynamic range of the input signal in the presence of external noise. The technical result is to increase the accuracy of adjustment of the zero due to the exclusion of the influence on the results of the transformation occurring errors. This result is achieved in that the ADC with periodic adjustment of zero contains the source signal, analog subtractive device, control device, and accumulating adder, normalizing device, digital subtractive device, the device summation-subtraction and the parallel register. ADC allows the suppression of noise due to the accumulation and averaging of the signal provides a measurement of the difference between the zero code and the code of the averaged error and compares it with the previous measurement. The accuracy of adjustment of the permanent component increases as decreases the number of significant digits, affecting the measurement accuracy. 1 Il.

The invention relates to a digital measurement technology and can MOU.

There are many schemes conversion with ADC in the form of integrated circuits, which are made according to the semiconductor integrated and hybrid technology.

There are simple and cheap ADC with a small width, and known precision converters have a large number of States, and the number of States referred to specific measurement intervals of the input parameter, is a measure of the attainable resolution. However, high resolution only makes sense if it is attainable accuracy.

Known ADC, and also include the nodes more or less drifting. This drift though and can be made very small, but it cannot be eliminated. Source of error in the ADC are zero drift and nonlinearity of the conversion.

Known measuring device, made in the form of microcomputers and associated analog block, and the measurement cycle consists of three steps, and at each of these steps at the entrance alternately connect a null value (e.g., short circuit), the measured value of the reference value.

Analog block generates three time interval, proportion the integrated value of the measured values, the output word of microcomputers accurately represents the amplitude of the analog signal. The measurement excludes the impact of the drift, because the magnitude of the drift, it can be assumed, does not change at all three measurement steps.

A disadvantage of the known technical solution is that one transformation requires a relatively long time, decreases the accuracy of the compensation of the DC component in the presence of noise and due to the nonlinearity of the ADC.

Known for integrating ADC (see inventor's certificate SU N 1211886, IPC H 03 M 1/52, from 25.07.84), consisting of six keys, integrator, comparator, site, determine the sign of the mathematical expectation, switch, two DACS, two reversible counters, pulse shaper, diagrams And control device.

The integrating ADC has, in General, two main features, firstly, the output voltage is the integral or average of the input voltage, within a constant period of time. In this regard, integrating Converter will provide repeatability in the presence of high frequency (relative to the measured period) noise, secondly, in the transducer of this type is used to the time to DL the ska output codes.

A disadvantage of the known device is a low speed ADC.

The closest in technical essence and the achieved result is ADC with adjustment of the bias voltage of zero (see E. A. particularly, 1991, microelectronic means for processing analog signals, Moscow, Radio I Svyaz, page 302) containing the signal source, the output of which is connected through the analog subtractive device to the first ADC and the second analog subtractive device connected to the DAC output, the second ADC input and the first input of the DAC are connected respectively to the outputs of the control device, and the output of the ADC is connected to the second input of the DAC.

A disadvantage of the known device is the low accuracy of tuning constant component due to the presence of noise, the nonlinearity of the ADC, and the differential quantization steps ADC and DAC.

The technical result of the proposed solutions is to improve the accuracy of the tuning constant component due to the exclusion of the influence on the results of the transformation occurring errors.

This result is achieved in that the ADC with periodic adjustment of the DC component containing the source sigd analog subtractive device connected to the DAC output, and the second ADC input and the first input of the DAC are connected respectively to the outputs of the control device, connected in series introduced accumulating adder, normalizing device, digital subtractive device, the device summation-subtraction and the parallel register, the accumulating adder is connected with the output of the ADC, and the output of the parallel register is connected to the input of the DAC and the second input of the summation subtraction, in addition, the second input of the subtractive device is connected to a source of zero-input and the second input is accumulating device (adder), normalizing device and the parallel register are connected respectively to the outputs of the control device.

The essence of the proposed technical solution lies in the implementation of the principle of compensation of errors caused by drift and noise, which are formed in the source signal, and the zero drift and noise of the nodes included in the ADC and DAC and ADC nonlinearity, and at each step of the operation of the device summation-subtraction is performed clarification code voltage adjustment DC component, i.e., with each step decreases the residual error adjustment constant component.

THE COM, p. 104) where the code number is added to the contents of the parallel register. When the summation of large numbers requires a large bit width of the adder and parallel register, and accumulating adder is used to iterate over the addresses of RAM. The proposed device, the accumulating adder is used for summing and accumulating samples of the mixture constant component and noise, when this bit is accumulating adder and parallel register is equal to the data width at the entrance is accumulating adder, because it uses a single-bit output transfer digit adder.

Normalizing the device is offset and can be performed on the multiplexers (see U. Titze, K. Schenk, 1983, solid state circuitry, Ed. by A. G. Alexenko, Moscow, Mir, page 328). Shift one digit to the right corresponds to dividing the number by two. Normalizing device in the proposed technical solution moves the code to the right by counting pulses overflow accumulating adder, thus, the averaged value of the mixture constant component and noise present at the input device in the adjustment mode of the DC component, i.e., when otsutstvuet, Volume 2. The English translation edited by Halperin, Moscow, Mir, page 51). In offset binary code is a code combination 1000 0000 0000 (12-bit code). The source code of zero produces a null code combination, but most of the high-speed ADC work in additional code that causes additional noise when the zero-crossing in connection with switching all (for example, for the AD9042 ADC - twelve) discharges. To reduce the intrinsic noise of the device may be offset zero code with the following account of this offset on the output device, so the source code of zero may, in particular, to generate different from the known device zero code.

Digital subtractive device may be made in the form (see Digital radio receiving system, 1990, Handbook, under. ed M. I. Jezinskogo, Moscow, Radio I Svyaz, page 53) and is used to build a comparator with a digital adder. In order to perform the comparison operation, the word is represented in two's complement, with the known device is the subtraction function, and the output of the overflow of the adder to perform the comparison function of two words a and b when the subtraction. Digital subtractive device the pillar, i.e. to highlight the error adjustment constant component.

The device summation-subtraction can be implemented in the form (see Digital radio receiving system, 1990, Handbook, under. ed M. I. Jezinskogo, Moscow, Radio I Svyaz, page 43), which is used to increase the bit, i.e., increasing the dynamic range of the input to the ADC. The device summation-subtraction in the proposed device calculates the difference or sum of money (depending on sign) between the source voltage adjustment constant component and error adjustment of the permanent component, i.e., specifies the value of the voltage adjustment constant component. The availability of this device with a few tweaks constant component minimizes the number of significant digits of the error adjustment constant component.

A parallel case can be made in the form (see E. A. particularly, 1991, microelectronic means for processing analog signals, Moscow, Radio I Svyaz, page 323), which is used to remember the previous measurement result of the conversion, a similar figure. The parallel register stores the updated code value voltage adjustment constant component.

To clarify the essence of the proposed solution provides an illustration in the drawing, which shows a structural diagram of the ADC with periodic adjustment of the DC component.

ADC with periodic adjustment of the DC component contains the signal source 1, analog subtractive device 2, ADC 3, DACS 4, control unit 5, connected in series accumulating adder 6, the normalizing unit 7, digital subtractive device 8, the device summation-subtraction 9, the parallel register 10, and the source code of zero 11.

The device operates as follows.

The signal source 1, in the absence of the useful signal, is the source of the noise and DC offset due to drift of zero and a constant offset and noise are fed to the analog subtractive device 2 and further to the ADC input 3, which converts the analog signal into a digital code, which goes to the accumulating adder 6 and further normalizing device 7. Accumulating adder 6 and normalizing device 7 calculates the average of the CPU 3. The difference between the reference code, which, in particular, can be zero ADC code 3, and code the measured DC component is the error adjustment DC component at the input of the ADC 3. When the first iteration of the parallel register 10 is set to zero, so on. error code tuning constant component passes through the summing-subtracting 9 and is converted in the DAC 4 in analog voltage, approximately corresponding to the magnitude of the DC bias source 1. In analog subtractive device 2 is compensated DC offset signal source 1. Compensation, however, is not entirely due to the presence of integral and differential ADC 3 and DAC 4, and also because of a difference of ADC quantization steps 3 and DAC 4. In the second iteration, the output of subtractive device 8 is allocated to the residual error between the constant offset of the signal source 1 and the voltage adjustment DC component generated during the first iteration. This error code is subtracted or added, depending on the sign, device summation-subtraction 9 code voltage adjustment constant component, which is stored in the parallel register 10, ie, a clarification velicity 3 can be arbitrarily large within the dynamic range of the ADC 3, and at the second iteration, the voltage at the ADC input 3 cannot be greater than the total error of the devices included in the proposed device, when measuring small quantities are only low-order bits of the ADC 3 and DAC 4, and so on. in the second and subsequent iterations decreases the error due to integral nonlinearity and differential ADC quantization steps 3 and DAC 4, and several iterations may be achieved by adjusting the constant component with maximum precision.

The proposed solution has improved the accuracy of tuning constant component due to the exclusion of the influence on the results of the transformation occurring errors.

Analog-to-digital Converter with periodic adjustment of the DC component containing the source signal, the output of which is connected through the analog subtractive device to the first input of the analog-to-digital Converter and the second analog subtractive device connected to the output of digital to analog Converter and the second analog-digital Converter and the first input of the digital to analogue Converter connected respectively to the outputs of the control device, characterized those who provoe subtractive device, the device summation-subtraction and the parallel register, the output of which is connected respectively to the input of a digital to analogue Converter and the second input of the summation-subtraction, and the entrance is accumulating adder is connected with the output of the analog-to-digital Converter, in addition, the second input of the digital subtractive device is connected with the source code of zero, and the second input is accumulating adder, normalizing device and the parallel register are connected respectively to the outputs of the control device.

 

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