Device code frame synchronization

 

(57) Abstract:

The invention relates to systems for the transmission of discrete data and can be used for frame synchronization in systems robust data protection that apply corrective, in particular concatenated codes. The technical result - increased robustness frame synchronization messages and enabling operation of the device in channels with high noise level. The technical result is achieved by introducing a random access memory (RAM) unit adders modulo two, Comparer rooms, full adder, register number matches, block compare, counter synchronization. The first output of the block decoders connected to the input of the adders modulo two, the other input of which is connected to the output register of the second filter Huffman, the second output of block decoders connected to the enable input of the RAM write, output unit modulo two are the inputs of the block comparisons of rooms, the other input of which is connected with the older bits of the counter, the output of block comparisons of rooms connected with the older bits of the address input of the RAM low-order bits of the ADR is anizatio device, and with a clock input of the counter synchronization, set the inputs of which are connected to the outputs of block modulo two, the enable input of counter synchronization connected to the output of the threshold unit, the output of the RAM is connected to the input of the full adder, the second input of which is constantly applied logic "1", the output of the full adder is connected to the information input of RAM, as well as information input register of the number of matches and the input unit of comparison, a second input connected to the output of register numbers of matches, and the output of the Comparer is connected with the allow input register of the number of matches, the output of which is connected also to the input of the threshold unit, the output of the counter synchronization connected with the allow input clock timing sequence, and also connected to the output of the synchronization device. 1 Il.

The invention relates to systems for the transmission of discrete data and can be used for frame synchronization in systems robust data protection that apply corrective, in particular the cascade codes.

In the device code frame synchronization clock indication is transmitted words pomekhoustoichivoi the ity of the error correcting code. After establishing synchronization signs synchronization are removed from the error-correcting code, not reducing correcting ability of the code.

The most effective use of the code frame synchronization in the cascade codes. In this case, synchronization is provided by repetition of signs synchronization in different words internal code cascade code.

The main task is to increase the noise immunity of the frame synchronization when working in communication channels with high noise level.

A device frame synchronization, containing a register of the delay, the node detecting the error, the decoder and the counter, and register delays and node error detection combined input and output node of the error detection is connected to the input of the decoder [1].

However, this device has insufficient immunity.

Closest to the proposed device is the device (prototype) containing the register delay, the node detecting the error, the block decoders, a counter, a threshold unit, a clock generator sequence, the output of the modulo two, and register delays and node detected the Yong in the form of two series-connected filters Huffman and register syndrome, each filter Huffman consists of serially connected register and modulo two, the input of the syndrome register is connected to the output of the second filter Huffman, and the output connected to the input of block decoders, the output of clock generator sequence connected to the first input of the output adder modulo two, a second input connected to the output register delay, and the output is connected with the information output device [2].

A disadvantage of the known device is the lack of immunity, consisting in the fact that communication channels with high noise levels are not reliable series of synchronization messages.

The purpose of the invention to increase the noise immunity of the frame synchronization messages and as a consequence making possible the operation of the device in channels with a high level of noise.

To achieve the objectives of the proposed device code frame synchronization, containing a register of the delay, the node detecting the error, the block decoders, a counter, a threshold unit, a clock generator sequence, the output of the modulo two, and register delays and node error detection combined input and the United filters Huffman and register syndrome, each filter Huffman consists of serially connected register and modulo two, the input of the syndrome register is connected to the output of the second filter Huffman, and the output connected to the input of block decoders, the output of clock generator sequence connected to the first input of the output adder modulo two, a second input connected to the output register delay, and the output is connected with the information output device, and additionally containing random access memory (RAM), a block of adders modulo two, the Comparer rooms, full adder, a register number matches, block compare, counter synchronization. The first output of the block decoders connected to the input of the adders modulo two, the other input of which is connected to the output register of the second filter Huffman, the second output of block decoders connected to the enable input of the RAM write, output unit modulo two are connected with inputs of block comparisons of rooms, the other input of which is connected with the older bits of the counter, the output of block comparisons of rooms connected with the older bits of the address input of the RAM low-order bits of the address input of which is connected with younger rdom counter synchronization installation the inputs of which are connected to the outputs of block modulo two, the enable input of counter synchronization connected to the output of the threshold unit, the output of the RAM is connected to the input of the full adder, the second input of which is constantly applied logic "1", the output of the full adder is connected to the information input of RAM, as well as information input register of the number of matches and the input unit of comparison, a second input connected to the output of register numbers of matches, and the output of the Comparer is connected with the allow input register of the number of matches, the output of which is connected also to the input of the threshold unit, the output of counter synchronization connected with the allow input clock timing sequence, and also connected to the output of the synchronization device.

The drawing shows a structural electrical diagram of the device.

Device code frame synchronization register contains delay 1, the node error detection 2, is made of two series-connected first filter 3 and the second filter 4 Huffman and syndrome register 5, and each filter is composed respectively of registers 6 and 7 and adders 8 and 9 on module two, unit day two, RAM 15, the register number of hits 16, counter synchronization 17, the generator 18 synchronizing sequence, the full adder 19, block 20 comparison and threshold block 21.

The device operates as follows.

On the transmission side is formed in the input sequence. This sequence is the sum modulo two of the three sequences: internal binary cascade code with1synchronizing of binary sequences with2and the sequence with3violating the cyclical properties of the source code.

First, on the transmission side, the original message volume k m-ary (m>1) characters encoded m-ary error-correcting code, such as m-ary error-correcting code is a reed-Solomon. A reed-Solomon code is the outer code or code first-stage robust cascade code.

In the coding of the information is received code word reed-Solomon code (n, k), the information length is equal to k, and the block - n characters.

Further information is coded with a binary code, such as binary Bose - Roy-Chaudhury - Hocquenghem (BCH codes) with check polynomial h1(x). Code BCH is in>- block code length, k1information length of the code.

The source information for each word of the BCH code are symbols of a reed-Solomon code, considered as a sequence of binary symbols. A coding BCH code will be n binary words BCH code (n1, k1).

Next is the addition modulo two synchronizing sequence2with the words BCH code. As a synchronizing sequence selected binary code with block length n1and information length of k2for example code, reed-Muller (RM) 1-th order (sequence maximum period) with the check polynomial h2(x). Between the numbers of words in concatenated BCH code and an information part of the synchronizing sequence (code RM) is one-to-one correspondence. The first word BCH is folded sequence obtained by encoding 1 code of the Republic of Moldova, the second in the encoding code RM - 2, and so on, Such an addition is performed with all the words BCH code. If the check polynomials summable codes h1(x) and h2(x) are coprime and are divisors of binomial xn1+1, resulting in bude who will be quite certain guaranteed minimum code distance and to have certain curative properties.

The third sequence with3which are the words BCH, will be constant for all words in the sequence of length n1bits that violate the cyclical properties of BCH code. Such a sequence may be any sequence that is not a code word BCH code, for example a sequence of 10000...000.

At the receiving side input sequence, formed as the sum of three sequences, is supplied to the information input device frame synchronization. When this input sequence is written to the register delay 1 and simultaneously fed to the input node of the error detection 2, consisting of two series-connected first filter 3 and the second filter 4 Huffman and register syndrome 5.

In the filters 3, 4 Huffman is the multiplication of the input sequence on the test polynomials BCH codes and PM-h1(x) and h2(x). Thus, in the first filter 3 Huffman is calculated syndrome BCH code or a sequence with1and in the second filter 4 - syndrome code of the Republic of Moldova or the sequence c2.

When entering the infallible word syndrome code is zero and the syndrome register 5 will be recorded CLASS="ptx2">

The proposed device synchronizes not only the inerrant words of the BCH code, as in the known device, but according to the code, accepted with errors.

When the input misspelled words, the multiplicity of which lies within the correcting ability of the code in the syndrome register 5 will be written to a combination of some set {di}, the corresponding transformed into the filters 3, 4 Huffman sequence c3and the error vector.

The block decoders 10 upon detection of combinations of d0or a combination of the set {di} generates the enable signal to the write input of RAM 15.

At this point of time in the register 7 of the second filter 4 Huffman is a combination that uniquely corresponding to the sequence c2since the sequence1removed by the first filter 3 Huffman, and the sequence3is permanent.

This combination from the output of the register 7 is supplied to the input of the adders 14 modulo two. In block adders 14 corrects discharges consider combinations, so that at the output of adders 14 module two was the combination corresponding to the number of words BCH code. what R the bugs and issues appropriate correction signals to the second inputs of unit adders 14 modulo two.

The block structure of the decoders 10 corresponds to the combinations of the syndrome to correct the error vectors. Combination syndrome, you should recognize that obtained by calculating a syndrome for each of the required vector of errors. Example of construction of the block decoders errors presented in [3].

Adjusted combination with a unit output of the adders 14 is supplied to the first input of the comparison of numbers 13. To the second input of block comparisons of rooms 13 receives signals from the senior ranks of the counter 11.

The counter 11 operates at a clock frequency received at the input of the synchronization device. The frequency of cycles is equal to the rate of supply of information to the input device.

The counter 11 is composed of two parts: the low-order bits are the conversion factor equal to the word length code BCH - n1, the most significant change in signal transfer with low and consider the number of words BCH code received at the input device. The number of high-order bits of the counter is selected to provide an account of all n words BCH code cascade code.

In block compare numbers 13 calculates a difference between the numbers of code words, calculated on the adopted code words and usrsa bits of the counter 11 is changed synchronously with the numbers of code words, input device code frame synchronization.

The output of the Comparer rooms 13 is connected to the address inputs of the RAM 15. The remaining address inputs of the RAM 15 is connected with the younger bits of the counter 11. Thus, the address input of RAM 15 receives signals that determine the phase of the received code words or the location of the code words in concatenated BCH code.

In the RAM 15 for each address corresponding to the phase of the received code words, stores the number of received code words. Signal installation, which is not shown in the figure, the contents of the RAM 15 is set to zero. With the arrival of the next code word to the contents of the RAM 15, the corresponding number of code words received from the phase, using the full adder 19 adds one, and this new value of the number of code words with matching phase is recorded in the RAM 15. In case the number of matches 16 stores the maximum number of matches phases of code words. Record the maximum number of matches in case the number of matches 16 is as follows. New number of matching phases of the output of the full adder 19 is supplied to the input unit of comparison, 20, to the second input of which is applied the maximum number of matches from the output of register with the Oia and the new number of hits recorded in the register of the number of matches 16. If the number of matches phases of code words exceeds a preset value, the output of the threshold unit 21 occurs, the enable signal received at the input 1 counter synchronization 17. This signal is set counter synchronization 17 in the state corresponding to the number of the last received code word. While the number of the last code word in which occurred the threshold is exceeded, the output of unit adders 14 modulo two comes on the installation inputs 2 counter synchronization 17. The enable signal low-order bits of the counter synchronization 17 are set to 0, and high - writes the number of the last code word.

The full amount of counter synchronization 17 is equal to n code words BCH code or nn1. To the clock input of counter synchronization 17 is supplied with the clock frequency of the input synchronization device code frame synchronization, equal to the speed information is received at the input of this device, and after receiving all words BCH code cascade code at the output of the counter synchronization 17 there is a signal overflow.

This signal generator 18 synchronizing sequence starts generating clock posledovateli is input to 1 output of the adder 12 modulo two.

The number of bits of the register delay 1 is selected equal to the length of the entire cascade code, and at the onset of the synchronization sequence at the input 2 the output of the adder 12 modulo two received code word cascade code.

The sync sequence is removed from the code words, and an information output device code frame synchronization receive words of the source code BCH or a sequence with1.

At the same time the overflow signal from the output of the counter synchronization 17 is output synchronization device code frame synchronization, accompanying the beginning of the cascade code.

Cycle synchronization is carried out according to the majority principle. For the final decisions need to match a certain number of rooms and phases of the received code word exceeding a threshold.

The threshold of the threshold block is selected in such a way as to ensure high reliability of the decision frame synchronization.

The greater the number of rooms and phases, to the various words BCH code, coincided, the higher the accuracy of the synchronization.

Achievable technical rez the new synchronization in the present invention is not only error-free code words, as in the known device, but the code words with errors on the determination of which is configured block decoders. This increases the robustness frame synchronization and allows synchronization with a higher level of interference in the communication channel, where the number of undistorted code words is reduced.

Cycle synchronization is carried out in all the rooms and the phases of the received code words. In the known device uses a limited number of rooms and phases, because the increase in the number of rooms and phases of the complexity of the known device is increased. The increase in the number of rooms and phases, in which the synchronization, in the inventive device also provides the ability to synchronize with a higher level of interference in the communication channel and increases the immunity of the device.

Sources of information

1. USSR author's certificate 461480, CL H 04 L 7/02, publ. 1972.

2. USSR author's certificate 849521, CL H 04 L 7/08, publ. 1981.

3. Clark, J., ml, Kane, J. Encoding with error correction in digital communication systems: Transl. from English. - M.: Radio and communication, 1987, pp. 96-101.

Device code frame synchronization, containing a register of shadowfiles, the output of the modulo two, and register delays and node error detection combined input and is connected to the information input device, the node error detection is made in the form of two series-connected filters Huffman and syndrome register, and each filter Huffman consists of serially connected register and modulo two, the input of the syndrome register is connected to the output of the second filter Huffman, and the output connected to the input of block decoders, the output of clock generator sequence connected to the first input of the output adder modulo two, a second input connected to the output register delay and the output is connected with the information output device, characterized in that it contains random access memory (RAM), a block of adders modulo two, the Comparer rooms, full adder, a register number matches, block compare, counter synchronization with the first output block decoders connected to the input of the adders modulo two, the other input of which is connected to the output register of the second filter Huffman, the second output of block decoders connected to the enable input of the RAM write, output block of the adder groups counter, the output of block comparisons of rooms connected with the older bits of the address input of the RAM low-order bits of the address input of which is connected with the younger bits of the counter, the clock input of the counter is connected to the synchronization input of the device, and also to a clock input of the counter synchronization, set the inputs of which are connected to the outputs of block modulo two, the enable input of counter synchronization connected to the output of the threshold unit, the output of the RAM is connected to the input of the full adder, the second input of which is constantly applied logic "1", the output of the full adder is connected to the information input of the RAM, as well as the information input register of the number of matches and the input unit of comparison, a second input connected to the output of register numbers of matches, and the output of the Comparer is connected with the allow input register of the number of matches, the output of which is connected also to the input of the threshold unit, the output of the counter synchronization connected with the allow input clock timing sequence, and also connected to the output of the synchronization device.

 

Same patents:

Device sync cycles // 2192711
The invention relates to communication technology and can be used for receiving data from a downhole telemetry system using looped packets of digital data

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal

The invention relates to techniques for digital communication, namely, devices frame synchronization in digital transmission systems with a temporary seal

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital transmission systems with a temporary seal

The invention relates to techniques for telecommunication and can be used in the transmission channels for digital conversion of signals, working both in time and frequency domain

The invention relates to digital communication systems and can be used in communication networks, in particular in apparatus for the formation and separation of digital streams

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

1 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg

Up!