The data transmission system comprising a cyclic shift of the data elements and processing bytes

 

(57) Abstract:

The invention relates to a device data transmitted from the transmitter to the receiver. Technical result achieved - an exception error when decoding the transmitted symbols. The first station encodes the data as character data, cyclically shifts the character data so that the data symbols corresponding to each other in the areas of synchronization of data segments of a data block are arranged so that they worked together, and inserts the cyclically shifted data characters in the data plots of the data segments of the data block so that the block of data has a number of data segments, each data segment has a plot synchronization segment and plot data. The second station processes the data symbols, so that the corresponding data symbols in the first set of data symbols are processed with a delay of twelve data symbols and the corresponding data symbols in the second set of data symbols are processed with a delay of twenty-four character data based on character positions of the data relative to the clock plots. 2 c. and 15 C.p. f-crystals, 13 ill.

The destination area of the invention

Present izobretennye

In terrestrial communication system 8 VSB (i.e., terrestrial communication system with partially suppressed sideband, which transmits symbols, each of which has one of the 8 possible signal levels) information is usually transmitted by a transmitting station to the receiving station over the air. In one example of such a system every two bits to be transmitted data is encoded by the broadcaster as a symbol having one of eight possible levels of signal amplitude, so that each data byte having eight bits, is represented by four characters.

In one such system, disclosed in the standard for digital television ATSC, published on 16 September 1995, each pair of bits is served in the pre-coding (precoder) in the trellis encoder. The pre-coding and trellis encoder, each of them includes a twelve bit delay elements. Thus, the pre-coding and trellis encoder can be represented as twelve identical pre-coding and trellis encoders with (1) the input multiplexer for the serial connection of the input sets of two bits with twelve identical device connecting the output sets of three bits with the device display characters. Twelve pre-coding and trellis encoders alternate pairs of bits so that each pair of bits in the first byte of data is processed by the first pre-encoding and trellis encoder, each pair of bits in the second byte of data is processed by the second pre-encoding and trellis encoder,... and so that each pair of bits in the twelfth byte of data is processed twelfth pre-coding and trellis encoder. Every subsequent sets of twelve bits are processed in the same way.

The pre-coding and trellis encoder converts each pair of input bits in the three corresponding output bits, served in the display device of the character. The display device converts each character sequence of the three output bits in a symbol having a corresponding one of the eight signal levels in eight level set. The resulting symbols are fed into the multiplexer that adds the synchronization symbols to the data symbols to structure the data and synchronization symbols in the block.

The unit is structured in such observasi plot segment, containing four symbol synchronization segment, and (2) the sync field containing 828 pseudo-random generated synchronizing symbols field. Each of the other 312 segments includes (1) clock plot segment containing four symbol synchronization segment, and (2) plot of data containing 828 data symbols.

After that, the characters in the above described structure of the block is transmitted and received by the receiver. The receiver includes a comb filter and a trellis decoder. Comb filter is used to filter out interference that may be caused by channels NTSC (National Committee on television USA), which broadcasts from neighbouring stations. Trellis decoder in the receiver is to decode the symbols in the received blocks in their respective initial pair of bits. Lattice decoder similar to the trellis encoder in the sense that the lattice decoder processes the symbols of the same bytes together. Thus, these characters must act in the trellis decoder in the correct sequence.

As you can see from the above descriptions of the data block, the data blocks Hispalis contains twelve bytes when each byte contains four characters. Accordingly, each data segment of each data block transfers the partial data group, so that the bytes of a partial group of the split between the two data segments. In the sync symbol segment sync section of the data segment is separated by some character data bytes from the other data characters of these bytes. Thus, if the character data is summarized in the block of data in the same sequence in which they are issued on a display device (conversion) characters, the characters will not be in the trellis decoder in the correct sequence. Accordingly, the trellis decoder in the receiver will not process the characters of the same bytes together, which will cause errors in the decoding of the transmitted symbols.

This invention involves a device for alternating (cyclic shift) of data to be included in the structure of the data block, so that the characters do in the trellis decoder in the correct sequence, so that you can avoid errors in the decoding process caused by the presence of synchronizing symbols of the segment. This invention also involves the nalitch with one aspect of the present invention the processing device processes the data elements, want to insert into the data block. The block of data has a number of data segments and each data segment has a clock section of the site and data. The processing device includes an encoder tool rotation and the tool insert. The encoding means encodes data as data elements. Means interleaves interleave data elements, the data elements corresponding to each other for synchronization section of the segment are arranged so that they worked together. The tool inserts inserts alternating data elements in the areas of data in the data block.

In accordance with another aspect of the present invention, the receiver receives the data symbols are arranged in the data block. The block of data has a number of data segments. Each data segment has a clock section of the site and data. Each clock plot contains four clock symbol, and each plot contains data 828 data symbols. The data symbols are interleaved, so that the data symbols of the same bytes, separated by a synchronization section of the data segment are arranged so that they worked together. The receiver includes a receiving means and a processing means. Pricey character data of the same bytes together even if the data symbols are the same bytes separated synchronizing sections of each data segment.

In accordance with another aspect of the present invention, the receiver accepts the data elements that are organized in the data block. The block of data has a number of data segments, each data segment has a clock section of the site and data. Each clock plot contains S clock elements, and each segment of data comprises N data items. The data elements are interleaved, so that the data elements corresponding to each other on each clock plot of each data segment are arranged for joint processing. The receiver includes a receiving means and a processing means. The receiving means receives the data elements of the data block. The processing means processes the corresponding pairs of data elements depending on the separation between the corresponding elements of the data by synchronizing the phases of each data element.

Brief description of drawings

These and other features and advantages of this invention will become apparent from a detailed consideration of the invention in conjunction with the drawings, in which pravednyh numbers, which you can implement for randomization data Fig.1 in order to randomize the data;

Fig. 3 - clotting device of alternation of bytes that can be implemented for the coagulation device of alternating bytes Fig.1;

Fig. 4 - grouping of characters as the result of the encoding Converter from bytes to characters and lattice encoder of Fig.1;

Fig.5 - interleaved symbols in Fig.4, to which is added the sync symbol segment;

Fig. 6 is a more detailed type Converter byte character and lattice encoder of Fig.1;

Fig.7 is a table showing the rotation (rotation) bytes implemented by rotator bytes Fig.6;

Fig. 8 is a table showing the correspondence between alternating implemented in accordance with the table of Fig.7, and groups stored data;

Fig.9 - pre-coding and lattice encoder that can be used in this as in Fig.6;

Fig. 10 is a table showing an oscillation realized by the rotator characters Fig.6;

Fig. 11A, 11B, 11C and 11D is a table showing the sequence with which the data symbols are inserted in the data block according to this invention;

Fig. 12 - the structure of the data block in which the delay value for data presented on Fig.11A, 11B, 11C and 11D to trellis decoder in the receiver together correctly processed symbols of the same byte.

Detailed description

As shown in Fig.1, the first station 100 includes a synchronization compensator 101 MPEG, which receives the MPEG data packets from a data source MPEG2 (not shown) and which is more fully described in the application 08/479428, filed June 7, 1995, the MPEG data Packets arrive at a rate of approximately 12,893 of Kaketa per second. These packages include MPEG 187 bytes of MPEG data and one byte sync MPEG. Because the MPEG synchronization is not needed to process the remainder of the encoder ground modem 8 VSB, according to this invention the synchronization compensator 101 MPEG removes one byte synchronization of MPEG packets MPEG and passes only the 187 data bytes MPEG to randomization data 102, which endomysium each MPEG data packet generated by the synchronization compensator 101 MPEG. Randomization data 102 may perform a bitwise EXCLUSIVE OR operation between each byte of data received from the synchronization compensator 101 MPEG, and a pseudo-random sequence.

A pseudo-random sequence can be obtained, for example, by using a generator is consistent generator of pseudorandom sequences Fig. 2, is initialized at the first data packet of the data block and then re-initialized after each 312 data packets. The registers of the random sequences shown in Fig. 2, are initialized to OxF180 at the beginning of each data block (where the outputs of registers X16, h, x14, X13, X9, X8 is set to one). The generator of pseudorandom sequences shown in Fig.2, ahead of each byte of the input data packet. A pseudo-random sequence generated by this random sequences, issued on outputs D0-D7, which can be connected to respective inputs of EXCLUSIVE OR. Other inputs of the EXCLUSIVE OR take the appropriate bits in the bytes from the synchronization compensator 101 MPEG.

The output signal from randomization 102 data is fed into the encoder 103 reed-Solomon. The encoder 103 reed-Solomon calculates twenty bytes of parity reed-Solomon and makes these twenty bytes for packets of randomized data generated by randomization data 102. Accordingly, the encoder 103 reed-Solomon generates data packets, each of which contains 207 bytes (i.e. 187 bytes randomized data from randomization 102 d is in the multiplexer 104 type "packet bytes". The multiplexer 104 type "packet bytes" converts each data packet reed-Solomon 207 bytes in a continuous stream of bytes. Then this stream of bytes processed coagulation device 105 alternating bytes, which is conventionally shown in Fig.3 and which is more fully described in the application 08/315153, which was filed on September 29, 1994, Each block in Fig.3 is a register that stores one byte. Coagulation device 105 alternating bytes are synchronized, so that the first byte of the first data packet reed-Solomon enters the upper arm device rotation, shown in Fig.3, the second byte of the first data packet reed-Solomon comes in the second arm of the device rotation, shown in Fig.3,... fifty-second byte of the first data packet reed-Solomon enters the lower arm device rotation, shown in Fig.3, fifty-third byte of the data packet reed-Solomon enters the upper arm device rotation, shown in Fig.3, and so on

The alternating flow of bytes from the coagulation device 105 interleaving of bytes fed to the inverter byte-symbol" and trellis encoder 106, which encodes the data bits in the received bytes as characters Danner 106 - this, in result, the twelve trellis encoders designed to accommodate delays in the twelve symbols of the comb filter used in the receiver, such as the second station 109 in Fig.1. That is, the presence of the comb filter in the receiver requires that the inverter is "byte-symbol" and trellis encoder 106 encodes data bits of the received bytes of data as coded data symbols, so that the coded data characters of each trellis encoder are separated with eleven other data trellis encoders. So in result, there are twelve trellis encoders. In addition, the Converter "byte-symbol" and trellis encoder 106 must encode pairs of data bits of the received bytes of data as coded data symbols, so that a pair of data bits of the same byte are encoded by the same encoder.

In Fig. 4 shows the transmitted data symbols. For example, the symbol E0 n-1 can be a symbol obtained by encoding by the encoder zero bits 7, 6 bytes are zero, the symbol E0 group n can be a symbol obtained by encoding by the encoder zero bits 5, 4 bytes are zero, the symbol E0 n+1 can be so separated from other nearby characters E0 eleven characters.

Similarly, the symbol E1 n-1 can be a symbol obtained by encoding by the encoder, a bit 7, 6 bytes one symbol E1 group n can be a symbol obtained by encoding by the encoder, a bit 5, 4 bytes one symbol E1 n+1 can represent a symbol obtained by encoding by the encoder, a bit 3, 2 bytes one and so on, Each symbol E1 separated from other nearby characters E1 eleven characters. Thus, the encoder zero encodes the characters of the first byte, the encoder encodes one of the symbols of the second byte, the encoder encodes two characters of the third byte, and so on, Respectively, the characters are encoded in groups of twelve bytes and transmitted groups of twelve bytes.

As mentioned above, each segment includes 832 symbols in the data stream. These 832 symbols include four synchronization segment symbols and 828 data symbols. Thus, the data symbols in the transmitted data stream are periodically interrupted synchronization segment symbols, as shown in Fig. 5. Since the transmitted symbols of the data from each encoder must be separated from each other, so that they could properly handle resetcore distance between data characters, in the present invention, the data symbols are rotated (alternate) in each segment at a preset value in order to recover the data symbols at the desired distance from each other.

For example, this amount of rotation may be null for character data in the first data segment following the sync block data segment may be equal to four for the characters in the next data segment may be equal to eight characters of data in the next segment of the data, may be null for character data in the next data segment, and so on, Thus, the character data following immediately for synchronizing segment symbols in the plot data of the first data segment followed by the same sync block data segment is a symbol E0 corresponding to the trellis encoder zero. Following the data symbols in the data segment in order is E1, E2, E3, E4, E5, E6, E7, E8, e, E10 and E11, as shown by the group (n-1) data symbols in Fig.5. This structure is repeated throughout the data segment (segment zero), as shown lattice column for segment 0 on the tables of Fig.11A, 11B, 11C and 11D.

However, the character data following immediately after the synchronization segment is eating for synchronizing block data segment, is a symbol E4 corresponding to the trellis encoder four. Following the data symbols in the data segment in order is E5, E6, E7, E8, e, E10, E11, E0, E1, E2 and E3, as shown by the group (n) symbols in Fig.5. This structure is repeated throughout the data segment (segment one), as shown lattice column for segment 1 in the tables of Fig.11A, 11B, 11C and 11D.

Similarly, the character data following immediately after the synchronization segment symbols (i.e., the synchronization segment of the symbols S0, S1, S2 and S3) in the third segment of the data following the sync block data segment is a symbol E8 corresponding to the trellis encoder eight. Following the data symbols in the data segment in order is e, E10, E11, E0, E1, E2, E3, E4, E5, E6 and E7. This structure is repeated throughout the data segment (segment two), as shown lattice column for segment 2 in the tables of Fig.11A, 11B, 11C and 11D.

Converter "byte-symbol" and trellis encoder 106, which are shown in detail on Fig.6, converts the alternating flow of bytes from the coagulation device 105 alternating bytes into characters with the correct sequence symbol, which should properly handle the second station l 202 bytes multiplexers 203 type "byte-pair bit, pre-coding and trellis encoders 204, rotator characters multiplexer 205 and 206 characters.

The alternating flow of bytes from the coagulation device 105 interleaving of bytes supplied to the demultiplexer 201 bytes. Bytes are grouped by the demultiplexer 201 bytes in groups of bytes, containing twelve bytes per group. These twelve bytes appear at the outputs B0-B11 of the demultiplexer 201 bytes. Each group of twelve bytes alternates between a rotator 202 bytes. Rotator 202 bytes contains the outputs C0-C11 and interleaves the bytes on the outputs B0-B11 of the demultiplexer 201 bytes according to the table shown in Fig.7. As shown in the tables of Fig.11A, 11B, 11C and 11D, the order of the bytes in the flow of alternating bytes fed to the Converter "byte-symbol" and trellis encoder 106, changing due to rotation (rotation) of the characters, which is realized by synchronizing the segment characters at the beginning of each data segment. The alternation of bytes in each group of bytes generated by the demultiplexer 201 bytes to the rotator 202 bytes, it is desirable to restore the order of the bytes as a result of adjustments made due to the synchronization segment characters.

This alternation of bytes shown in Fig.11A, 11B, 11C and 11D. Fig.11A, 11B, 11C and 11D show the first five segments of data following the sync block data segment of the data block. The last eight characters of the data of the data segment zero (i.e., the data symbols 816-827 in Fig.11D)'s one. 828 data symbols in the data segment zero and the first 36 characters of the data in the data segment one are the first eighteen groups of twelve bytes of data processed by the rotator 202 bytes. As mentioned above, the rotator 202 bytes applies a zero alternation to these first eighteen groups of twelve bytes. These first 216 bytes are served in the order (without rotation) to the corresponding trellis encoders E0-E11.

Then the rotator 202 bytes applies the rotation to the following four seventeen groups of data bytes accepted by the rotator 202 bytes to return the bytes in their initial byte-order. These bytes are bytes 216-419. This alternation of four makes these bytes to encode the corresponding trellis encoders E4-E3. Thus, the data symbol thirty-six in one data segment corresponding to bits 7, 6, is 216 bytes and corresponds to the trellis encoder four. Accordingly, the byte order is restored in the data segment one, starting with the character data thirty-six. These seventeen groups of twelve bytes end with data twenty-three data segment two.

Then the rotator 202 buy the m 202 bytes to return the bytes in their initial byte-order. These bytes are bytes 420-623. This alternation eight makes these bytes to encode the corresponding trellis encoders E8-E7. Thus, the character data twenty-four in the data segment two corresponding bits 7, 6, is 420 bytes and corresponds to the trellis encoder eight. Accordingly, the byte order is restored in the data segment two, starting with the character data twenty-four. These seventeen groups of twelve bytes end with eleven data of the data segment three.

Then the rotator 202 bytes applies the alternating zero for the next seventeen groups of twelve bytes taken by the rotator 202 bytes to return the bytes in their initial byte-order. These bytes are bytes 624-827. This zero alternation makes these bytes to encode the corresponding trellis encoders E0-E11. Thus, the twelve data symbols in the data segment three corresponding bits 7, 6, is 624 bytes and corresponds to the trellis encoder zero. These seventeen groups of twelve bytes out of the data symbol 827 data segment three. Accordingly, the order slithery 203 "bytes-pair bit multiplexers each byte of data, supplied on output lines C0-C11 rotator 202 data, four corresponding sequence of pairs of bits. These bits are issued by the multiplexer 203 "bytes couple of bits on outputs D0-D11 and processed by the pre-coding and trellis encoders 204. Pre-coding and trellis encoders 204 converts the bit pair outputs D0-D11 in matching sets of three output bits and convert the three sets of output bits in the data symbols. Thus, each data symbol has one of eight possible levels defined by three bits. Pre-coding and trellis encoders 204 include pre-coding and trellis encoders E0-E11, which give the character data through the respective outputs E0-E11.

In Fig. 9 shows the pre-coding and trellis encoder. The pre-coding and trellis encoder of Fig.9 it is possible to duplicate twelve times to separately encode each stream of pairs of bits corresponding to the outputs D0-D11 multiplexer 203 "bytes couple of bits". In this case, the delay elements of the pre-coding and trellis encoder of Fig.9 is elementnode encoding device pre-coding and trellis encoder E0 as output bits Z2, and bits of X1 pair of bits in the stream D0 bit pairs are encoded trellis encoder device pre-coding and trellis encoder E0 as output bits Z1 and Z0. Conversion device (display) symbols (not shown) pre-coding and trellis encoder E0 converts the output bits Z2, Z1, Z0 into a corresponding data symbol. Similarly, bit x2 pairs of bit stream D1 pairs of bits encoded by the pre-coding device pre-coding and trellis encoder E1 as output bits Z2, and bits of X1 pair of bit stream D1 bit pairs are encoded trellis encoder device pre-coding and trellis encoder E1 as output bits Z1 and Z0. A device of the character conversion device pre-coding and trellis encoder E1 converts these output bits Z2, Z1, Z0 into a corresponding data symbol. Other streams of bytes are similarly processed by other devices preliminary coding and trellis encoders E2-E11.

The character data on the output lines E0-E11 pre-coding and trellis encoders 204 alternate rotator 205 characters according to the table shown in Fig.10. the encoded stream of symbols within the segment and synchronization symbols of the segment. Each alternation applies to all sixty-nine groups of twelve data symbols in the plot data of the data segment. Accordingly, the data symbols in the plot data of the first data segment (segment zero) following the sync block data segment, alternate with zero, the data symbols in the plot data of the second data segment (segment one) alternate on four data characters in the plot data of the third data segment (segment two) alternate on eight data characters in the plot data of the fourth data segment (segment three) alternate with zero, and so on for all 312 data segments of the data block.

Thus, with reference to Fig.10, and Fig.11A, 11B, 11C and 11D, the symbols of the data segment zero (the first segment of data following the sync block data segment) alternate with zero. Accordingly, the coded symbols from the encoder E0, E1, E2,... E11 in Fig.6 appear at the outputs F0, F1, F2... F11 rotator 205 symbols and are transmitted in the order E0-E11. However, the symbols in one data segment (second segment of data following the sync block data segment) alternate four. Thus, the coded symbols from the encoder E4, E5, E6,... E11, E0... E3 in Fig. 6 pmole data in the data segment two (the third data segment, following the synchronizing block data segment) alternate eight. Thus, the coded data characters from coders E8, e, E10, E11, E0... E7 in Fig.6 appear at the outputs F0, F1, F2... F11 rotator 205 symbols and are transmitted in the order of the E8 . .. E7. The data symbols in the data segment three (the fourth segment of the data following the sync block data segment) alternate with zero. Accordingly, the coded symbols from the encoder E0, E1, E2,... E11 in Fig.6 appear at the outputs F0, F1, F2... F11 rotator 205 symbols and are transmitted in the order E0-E11.

In such a distribution of rotation of the first character of data in one data segment (i.e., character data corresponding to the bits 5, 4 bytes 208) is treated with a symbol, which is transmitted to twelve characters before (i.e., character data corresponding to bits 7, 6 bytes 208). Similarly, the second character data in one data segment (i.e., character data corresponding to the bits 5, 4 bytes 209) is treated with character data, which is transmitted to twelve characters before (i.e., character data corresponding to bits 7, 6 bytes 209). Similarly, each of the data symbols corresponding to the bits 5, 4 bytes 210-215, is processed at the second station 109 bits 7, 6 LASS="ptx2">

However, the character data corresponding to the bits 5, 4 bytes 204 is separated twenty-three other character data from the character corresponding bits 7, 6 bytes 204. Accordingly, as will be discussed below, the ninth, tenth, eleventh and twelfth data symbols in the data segment, for the next four synchronization segment characters at the beginning of the data segment, there are twenty-four characters after the last character of data from the corresponding trellis encoders. Therefore, this delay of twenty-four character should be taken into account that these data symbols corresponding to the bits 5, 4 in these bytes 204-207, could be treated with symbols corresponding to the bits 7, 6 of the respective bytes 204-207 near the end of the data segment zero. After that, the data segment one delay of twelve characters can be used again in the second station 109.

Accordingly, the rotator 205 characters together with a delay of twelve and twenty-four characters, superimposed second station 109, ensures that the data symbols are the same bytes are processed the same lattice encoder and therefore are processed together. Similarly rotator 202 bytes PR who were in ascending order, and not in mixed order.

The multiplexer 206 multiplexes the data symbols generated by the rotator 205 characters back into the stream of data characters, which is served in the input device 107 in the structure of the data block (Fig.1). The input device 107 in the structure of the data block does an insert into the structure of the data block by adding the sync block data segment synchronization segment symbols to the data symbols in the data structure, which was discussed above and shown in Fig.12. Accordingly, the data block includes the sync block data segment (which is the first segment in the data block) and 312 data segments. The beginning of each segment includes four synchronization segment of a character. The transmitter 108 receives the data blocks from the input device 107 in the structure of the data block, performs a coordination device for signal levels on the data contained in the data blocks, and sends the blocks of symbols in the structure of the data block shown in Fig. 12.

The second station 109 receives the information transmitted by the first station 100 to decode the symbols to their corresponding pairs of bits x2/X1. The second station 109 includes, among other things, is Rovny signal, such as demodulation. Comb filter and lattice decoder 111 is filtered interference from adjacent stations NTSC and decode the symbols to recover the initial bit.

Comb filter 1300, which is the section of the comb filter and lattice decoder 111, shown in Fig.13. This site lattice decoder comb filter and lattice decoder 111 may be a conventional Viterbi decoder.

Comb filter 1300 includes a first section 1302 of the filter, which has a delay element 1304 to impose a delay of twelve characters of data processed comb filter 1300. Comb filter 1300 also includes a second section 1306 of the filter, which has an additional delay element 1308 for applying a second delay in the twelve characters of data processed comb filter 1300. The first and second filters 1302 and 1306 may be separated in the usual equalizer. The multiplexer 1310 selects the first section of the filter 1302 for all data symbols in the data segment except from the ninth to the twelfth data characters followed by four synchronization segment characters at the beginning of each segment danw data after four synchronization segment characters at the beginning of the data segment is processed with a delay of twelve characters. Otherwise, the multiplexer 1310 selects the second section of the filter 1306 for from the ninth to the twelfth data characters followed by four synchronization segment characters at the beginning of the data segment. Accordingly, from the ninth to the twelfth data characters followed by four synchronization segment characters at the beginning of the data segment is processed with a delay of twenty-four characters.

Certain modifications of this invention have been discussed above. Other modifications will appear to those who practically implementing this invention. For example, you can use the same pre-coding and trellis coder for pre-coding and trellis encoders 204 (E0-E11), if the delay components in the pre-coding and trellis encoder shown in Fig.9, are members of a delay of twelve bits. Since the delay element has a length of twelve bits, the pre-coding and trellis encoder shown in Fig. 9 is the equivalent of twelve pre-coding and trellis encoders 204 (E0-E11), shown in Fig.6. For example, the pre-coding and lattice 4 (X1) bytes of zero. Similarly, the pre-coding and trellis encoder shown in Fig.9, process bits 7 (x2) and 6 (X1) bytes one and twelve characters later manipulate the bits 5 (x2) and 4 (X1) of one byte. If you are using the pre-coding and trellis encoder shown in Fig.9, with a delay of twelve characters, demultiplexer 201 bytes can be excluded rotator 202 bytes may contain, for example, memory and arrestor that writes the bytes in memory and reads from it, so that the bytes are interleaved, as mentioned above, the multiplexer 203 type "byte-pair bit" can be omitted rotator 205 characters can contain, for example, memory and arrestor that writes characters to the memory and reads from it, so that the symbols are interleaved, as described above, and the multiplexer 206 characters can be deleted.

Moreover, although this invention has been here specifically disclosed in terms of data characters with the corresponding one of the eight possible signal levels, it is possible that the transmitted data may be data elements having any number of possible signal levels. In addition, there has been disclosed a specific encoders and decoders. However, e is 02 bytes. If so, then the second station 109 can be arranged so that it detects the correct correspondence between data characters and bytes. The function blocks described here can alternatively implement programmatically.

Accordingly, the present invention should be interpreted only as an illustration and as an explanation for the experts to be the best way of carrying out the invention. Details can be considerably modified without departing from the invention, and negotiated the exclusive use of all modifications that are included in the scope of the attached claims.

1. The processing device of the data elements to be included in the data block having the number of data segments, each of which has a clock section of the site and the data containing the means of encoding data as data elements, the processing device of the data elements includes means cyclic shift of data elements providing such an organization of the data elements corresponding to each other for synchronization section of the segment that they are treated together, and the tool insert shear data elements in the areas of data in the data block.

3. The processing device under item 2, characterized in that the byte of data elements contains D data elements, and data elements in bytes of the data elements interspersed, and DB is a group of data elements, and the tool insert allows the insertion of N data elements in the plot data of the first segment, so that the first segment contains N/DB groups of data items, and N/DB gives the rest of the R data elements, and the tool insert allows the insertion of N data elements in the second segment, so that the first DB-R data items inserted in the plot data of the second segment, come from a group of data items inserted in the first segment, and a means of cyclic shift provides a cyclic shift of the bytes of data elements that are inserted into the first segment to zero, a cyclic shift of the bytes of the elements of the Torah segment, and means cyclic shift provides a cyclic shift of the bytes of data elements, inserted in the third segment, at 2S after the first DB-2R the data elements to be inserted into the third segment.

4. The processing device under item 1, characterized in that the means of cyclic shift provides a means of cyclic shift of the bytes and the tool rotated characters.

5. The processing device under item 4, characterized in that the data elements are data characters and the synchronization section of each segment of the data block contains S of synchronizing symbols, and the means of cyclic shift characters made with the possibility of cyclic shift data characters to be inserted in the first segment, to zero cyclic shift data characters to be inserted into the second segment, S, cyclic shift data characters to be inserted in the third segment, on 2S, and the first, second and third segments successively appear in the data block.

6. The processing device under item 4, wherein the bytes of character data D contains character data, the character data In bytes character data interspersed and DB is the group of characters of data the segment contains N/DB groups of data characters, moreover, N/DB gives the remaining portion R of the data characters, and the tool insert allows the insertion of N data symbols in the second segment, so that the first DB-R data symbols are inserted in the plot data of the second segment, come from a group of data symbols are inserted in the first segment, and a means of cyclic shift of the bytes is made with the possibility of cyclic shift of the bytes of character data to be inserted into the first segment to zero, a cyclic shift of the bytes of character data to be inserted into the second segment, on the S after the first DB-R data symbols, inserted in the second segment, and with the possibility of cyclic shift of the bytes of data characters to be included in the third segment, at 2S after the first DB-2R symbols of data to be inserted into the third segment.

7. The processing device under item 6, wherein the synchronization section of each segment of the data block contains S characters, and a means of cyclic shift characters made with the possibility of cyclic shift data characters to be inserted in the first segment, to zero cyclic shift data characters to be inserted into the second segment, S, cyclic shift data characters to be inserted in TX2">

8. A receiver for receiving data symbols are organized into a data block having a number of data segments, each of which has a clock section of the site and data, each of the synchronizing section contains S of synchronizing symbols, and each section of data contains N characters of data containing a receiving means for receiving data characters of the data block, the data symbols are cyclically shifted so that the data symbols are the same bytes divided clock plot of the data segment are arranged so that they are treated together, and a receiver for receiving data symbols comprises means of processing the corresponding pairs of data symbols of the same bytes together, even if the data symbols are the same bytes separated synchronizing sections of each data segment.

9. The receiver under item 8, wherein the data symbols of the data block is cyclically shifted so that the processing means processes the corresponding pairs of data symbols of the same bytes together, even if the data symbols are the same bytes separated synchronizing sections of each data segment.

10. The receiver under item 9, characterized in that sinhronizirutsya in the first segment, cyclically shifted by zero is inserted in the second segment, cyclically shifted by S, is inserted in the third segment, cyclically shifted by 2S, and the first, second and third segments successively appear in the data block.

11. The receiver under item 9, characterized in that byte contains D character data and the character data In bytes interspersed, and DB is the group of characters of data, with N data symbols are inserted in the plot data of the first segment, so that the first segment contains N/DB groups of data symbols, and N/DB gives the remaining portion R of the data symbols and N data symbols are inserted in the second segment so that the first DB-R data symbols are inserted in the plot data of the second segment, come from a group of data symbols are inserted in the first segment, moreover, the bytes of the character data inserted into the first segment, cyclically shifted to zero bytes of data symbols are inserted in the second segment, cyclically shifted by S after the first DB-R data symbols are inserted in the second segment, and the bytes of the character data inserted in the third segment, cyclically shifted by 2S after the first DB-2R symbols of data to be inserted into the third segment.

12. The receiver on the x characters moreover, the data symbols are inserted in the first segment, cyclically shifted by zero is inserted in the second segment, cyclically shifted by S, is inserted in the third segment, cyclically shifted by 2S, and the first, second and third segments successively appear in the data block.

13. The receiver under item 8, characterized in that S= 4, N= 828, and the corresponding data symbols in a first set of data symbols separated by eleven symbols and the data symbols in a second set of data symbols separated by twenty-three characters.

14. The receiver under item 13, wherein the data symbols of the first data segment cyclically shifted to zero, the data symbols of the second data segment cyclically shifted by four characters of data of the third data segment cyclically shifted by eight, and the first, second and third segments successively appear in the received data block, and the means of processing executed with the possibility of processing the ninth, tenth, eleventh and twelfth data characters in the plot data of the second data segment as the second set of data characters and the treatment of all other character data area da is eat, which bytes of character data contains four data symbols and the data symbols in each of the twelve bytes of character data interspersed, and the group of characters of data contains 48 bytes of data characters, and the last twelve symbols of the data in the area data of the first data segment and the first thirty-six data characters in the plot data of the second data segment belong to the same twelve bytes of data characters, and the first eighteen groups of twelve bytes of data symbols from the first data segment, cyclically shifted to zero, the following seventeen groups of bytes of data symbols are cyclically shifted by four the following seventeen groups of bytes of data symbols are cyclically shifted by eight, and the following seventeen groups of twelve bytes of data symbols are cyclically shifted to zero, and the next eighteen groups of twelve bytes of data symbols are cyclically shifted by four.

16. The receiver under item 15, wherein the data symbols of the first data segment cyclically shifted to zero, the data symbols of the second data segment cyclically shifted by four characters of data of the third data segment cyclically shifted data, and the means of processing executed with the possibility of processing the ninth, tenth, eleventh and twelfth data characters in the plot data of the second data segment as the data characters of the second set and the processing of all other data characters in the plot data of the second data segment as the data symbols of the first set.

17. The receiver under item 8, wherein the corresponding data symbols in the first set of data symbols separated by eleven characters, with the corresponding data symbols in the second set of data symbols separated by twenty-three characters, and the means of processing executed with the possibility of processing the corresponding data symbols in the first set with a delay of twelve characters and work out the corresponding character in the second set with a delay of twenty-four characters.

 

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The invention relates to turopereiting /facing the interleaver in communication system

FIELD: coding in communication systems.

SUBSTANCE: proposed partial reverse bit-order interleaver (P-RBO) functions to sequentially column-by-column configure input data stream of size N in matrix that has 2m lines and (J - 1) columns, as well as R lines in J column, to interleave configured data, and to read out interleaved data from lines.

EFFECT: optimized interleaving parameters complying with interleaver size.

4 cl, 7 dwg, 3 tbl

FIELD: communication systems.

SUBSTANCE: proposed interleaver with partial reverse order of bits provides for sequential column-by-column configuring of size N input data stream in matrix that has 2m lines and J - 1 columns, as well as R lines in column J, interleaving of configured data, and line-by-line reading of interleaved data.

EFFECT: optimized parameters of interleaver.

5 cl, 7 dwg, 2 tbl

FIELD: communications engineering.

SUBSTANCE: method includes continuously controlling quality of communication channel, on basis of results of which value of depth of alternation of word symbols of interference-resistant code is selected, interference-resistant code symbols alternation, interference-resistant code words and information packet, composed of symbols of several interference-resistant code words is transferred to communication channel, on receiving side symbols are shifted back as they were and words of interference-resistant code are reproduced, while average number of errors in interference-resistant code words is estimated, and selective dispersion of errors number in interference-resistant code words of received information packet is determined, and after receiving another information packet alteration of previous value of alternation depth is performed on basis of deviation of selective dispersion of errors allocation in words of received information packet from dispersion of binomial allocation law.

EFFECT: higher trustworthiness of information receipt and decreased time of information receipt delay.

FIELD: communications engineering.

SUBSTANCE: proposed interleaving device and method are designed for evaluating new size N' = 2mx(j + 1) of interleaver and addresses from 0 to N - 1 in case desired size N of interleaver is greater than 2mxj and smaller than 2mx(j + 1), where m is first parameter pointing to number of serial zero bits from least significant bit (LSB) to most significant bit (MSB); j is second parameter corresponding to decimal value of bits other than serial zero bits. These interleaving device and method provide for saving N bits of input data in interleaver memory with new interleaver size N' from 0 address to N - 1 address. Then interleaving device and method execute interleaving involving partial bit reversal operations (PBRO) in memory with new interleaver size N' and read data out of memory by erasing addresses corresponding to addresses N to N' - 1 prior to interleaving.

EFFECT: enhanced effectiveness of interleaver memory.

10 cl, 6 dwg, 7 tbl

FIELD: communication systems for high-speed burst data transfer.

SUBSTANCE: proposed method and device are intended for receiving interleaved data and reading recorded characters by way of interleaving in mobile communication system receiver and provide for simultaneous decoding of set of sub-blocks. Interleaved coding burst has m value of bit shift, upper limiting value J, and residue R; character stream of coding burst is recorded in column-line order and in the process intermediate addresses is generated by inverting bit order assuming that residue R equals 0 for characters received; address correction factors are calculated for correcting intermediate address including column produced with residue; read address is generated by adding intermediate address to address correction factor for desired character decoding; character recorded in generated reading address is read out.

EFFECT: enhanced decoding and data transfer speed.

32 cl, 15 dwg

FIELD: method for receiving/transmitting control signal in client block of wireless communication system.

SUBSTANCE: in the method, signal of first channel is modulated with usage of first short Walsh code, modulated signal of second channel is added to control signal, total signal and modulated signal of first channel are multiplied by complex pseudo-noise code. Usage of short orthogonal codes ensures suppression of mutual interferences, which is inherent in ground-based wireless systems. A set of sub-channel codes is formed using four mutually orthogonal short Walsh codes, but usage of longer codes is acceptable. It is preferred that control data is transferred through first transmission channel, and power control data is transferred through second transmission channel. Length, and number of elements, in each channel code may be different, to additionally reduce ratio of peak transmission power to average transmission power during transmission at higher speeds.

EFFECT: increased efficiency.

6 cl, 14 dwg, 7 tbl

FIELD: encoding technology for communication systems, in particular, turbo-decoders.

SUBSTANCE: in accordance to the invention, turbo-code interleaving device (100), which uses linear congruent series, may be used as two-dimensional interleaving device (16) in turbo-coder (10), which also contains first and second composite coders (12, 14). Interleaving device (16) and first coder (12) are made with possible receipt of input bits. First coder (12) creates output symbols (22, 24) using aforementioned bits. Interleaving device (16) receives input bits (20) serially and row-wise. Algorithm for recursion of linear congruent series in interleaving device (16) is used for pseudo-random ordering, or shuffling, bits in each row of interleaving device (16). Bits (26) are then outputted from interleaving device serially and column-wise. Second coder (14) is made with possible receipt of interleaving bits from interleaving device. Second coder (14) creates output symbols (28) using these bits. Two streams of output symbols (22, 24) are multiplexed together with appropriate puncturing. If required, linear congruent recursive series may be generated in special form. Also, if needed, method for inversion of bits may be used in interleaving device (16) for ordering, or shuffling, rows of interleaving device (16).

EFFECT: increased probability of error correction.

6 cl, 3 dwg, 4 tbl

FIELD: communications engineering, methods for packet transmission of messages, possible use for transferring discontinuous information protected with interference-resistant code.

SUBSTANCE: in accordance to the invention, at transmitting side a message is divided onto blocks, length of which is equal to number of packets in a message, each block is encoded with interference-resistant code, block interleaving of interference-resistant code symbols is performed at interleaving depth equal to packet length, then symbols of interference-resistant code are divided onto packets in such a way, that each code symbol is positioned in its own packet, while in each packet control group is created for detection of errors, and then packets are transmitted to receiving side through a multidimensional route. At receiving side control group is checked for each packet, and packets with found errors are deleted, deinterleaving of symbols in received packets is performed, interference-resistant code is generated, which is then decoded with correction of deletions and received message is produced. As interference-resistant code, Reed-Solomon code is used.

EFFECT: reduced message delivery time.

2 cl, 1 dwg

FIELD: physics, radio.

SUBSTANCE: invention is related to the field of radio engineering, in particular, to class of data interleavers. Device contains memory unit, which represents delay line with length of (I-1)×(I-1)×M with (1-1) taps, where (I-1) - interleaver depth, M - unit delay, multiplexer, control device arranged in the form of counter, which works at the frequency of input pulses.

EFFECT: simplification of realisation and reduction of device computational complexity.

1 dwg

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