A device for converting ac voltage into the code

 

(57) Abstract:

The invention relates to techniques for electrical measurements and can be used in data acquisition systems for converting the AC voltage into the code. The technical result is to increase the accuracy. The device comprises a switching unit, the power lock switch, buffer, rectifier, the setting unit gain, integrator, ADC, block addressing. 4 C.p. f-crystals, 5 Il.

The invention relates to techniques for electrical measurements and can be used in data acquisition systems for converting the AC voltage into a digital code.

Improving the accuracy of performing analog-to-digital operations is essential to improve the quality of multi-channel data acquisition systems. In this regard, the development of a device for converting alternating current into the code should be aimed at reducing the error of the normalization of analog signals, including errors due to mutual influence channels.

A device for converting AC voltage into the code [1] , containing the switch, comparator, key, differential amplifier, the voltage Converter is often ucen to the first input key and to the comparator input, the exit key is connected to the input of the differential amplifier and a second input connected to the output of the comparator, which is also connected with the control input of the counter, the output of the differential amplifier is connected to the input of the Converter voltage frequency, the output of which is connected with the information input counter output through the communication unit connected to an external information bus.

In this device, the analog signals through the switch is fed to the input key, and a comparator. The latter produces the control signal for the key, so that one input of the differential amplifier highlighted the positive half wave of the AC voltage, and the other negative. At the input of the Converter voltage - frequency comes pulsating voltage, which is using the integrator of the specified Converter is integrated and then converted into a digital code.

The main disadvantage of this device is the low accuracy of the conversion of the input signal due to the nonlinearity of the transfer characteristic of the rectifier due to the initial offset of the comparator and its drift, and also due to the unstable operation of the comparator when the input signal is voltage AC code [2], contains the Converter voltage-current (PNT), the switch, the Converter current-voltage (Fri), the rectifier unit job gain (BSCU), consisting of n adders and switch, an integrator, an analog-to-digital Converter (ADC), the control unit, block addressing, consisting of a register, the demultiplexer. Inputs PNT input device and connect to the sensor signals, the switch is designed for the implementation of the survey sensors connected to the signal inputs of the device. Fri is designed for converting current from the output of the switch voltage with the specified gear ratio. The rectifier serves to highlight the positive half cycles of the input voltage. BSCU is designed to scale the output signal of the Fri and rectifier. Adders are a chain of weighting resistors, specifying the number of values of the gain of the integrator. Switch BSCW provides the required gain of the latter. The integrator is designed for accumulation of the analog signal, and the ADC is to convert accumulated by the integrator signal into a digital code. The ADC output is the output device. The control unit is gleen for storing control codes, coming from the external device. The demultiplexer is used to control the switch BSCU.

Analog signals via PNT arrive at the inputs of the switch. The latter, in accordance with the address code channel, recorded in the register, and connects the output of the respective sensor to the input of the Fri. With the release of Fri signals arrive at the input of the rectifier and the input of BSCW. Using the latest gain of the integrator is set in accordance with the code of the gain stored in the register. After scaling the signals fed to the input of the ADC. The conversion cycle of the device begins with the discharge of the capacitor of the integrator to "zero". For this purpose, the control unit generates the gate of the reset. Simultaneously, the control unit generates a pulse, which is the change-of-address of the channel. Under the effect of this code, the switch connects the corresponding output pot to the input of the Fri. On Fri output is set to a voltage proportional to the input signal. This voltage is fed to the input of the rectifier and the first input of BSCW. If at the first input of BSCW goes positive half-wave of the input voltage, the second input will receive the inverted positive half-wave. Since the coefficient is of ntegrator negative, on its output U>0. When a negative half-wave of the input voltage at the output of the rectifier U=0. At the first input of BSCW enters the negative half-wave of the input voltage, and the output of the integrator U>0.

The code of the gain stored in the register is supplied to the address input of the demultiplexer. Under the influence of the specified code last connects the output of the control unit to the respective control inputs of the switch BSCU. The gate of the savings generated by the control unit, outputs of the demultiplexer is supplied to the control inputs of the switch BSCU. Recent changes the gain of the integrator within the prescribed limits so as to ensure the coordination level between the input signal and the dynamic range of the ADC. Upon receipt of the strobe accumulation on the control inputs of the switch BSCU, the integrator performs the accumulation of the signal for a time equal to or a multiple of a whole number of periods of the mains voltage supply. After the end of the gate accumulation integrator is in the storage mode of the accumulated signal until the end of ADC conversion cycle, i.e. before the next strobe reset. The ADC converts the accumulated signal into a digital code according to the start signal, pose device has insufficient accuracy of the conversion of the AC voltage due to the residual resistance of the open channel switch, while increasing the number of channels decreases the attenuation of the interference caused by passing the input signal through the closed channels.

The present invention solves the problem of increasing the accuracy of the device. The technical result is to reduce uncertainty switching, including by increasing the attenuation of the interference caused by passing the input signal through the closed channels.

In a device containing a switch, a rectifier, a setting unit gear ratio (TCIS), integrator, ADC, block addressing entered switching units, a lock block, buffer, and signal inputs switching blocks are connected to signal inputs of the device. The outputs of the switching blocks connected to the signal inputs of the block lock signal outputs which are connected to signal inputs of the switch. The yield of the latter is connected with an input buffer and an output buffer connected to the input of the rectifier and to the first information input TCIS. The output of the rectifier is connected to the second information input TCIS, the output of which is connected to the information input of the integrator. The output of the integrator is connected to the ADC input, the output of which is an output device. Adresinden which is connected to the address inputs of the TCIS. Control outputs of the unit block is connected to the control inputs of the switching blocks, the address inputs of which are connected with the third group of outputs of block addressing. Control inputs of the integrator block addressing, ADC, TCIS are the inputs of the device and is connected to the output of the external control unit.

In Fig. 1 shows a structural diagram of a device for converting AC voltage into the code, where 1 - switching unit, 2 - unit lock, 3 - switch 4 - buffer, 5 - rectifier, 6 - unit gear ratio (TCIS), 7 - integrator, 8 - analog-to-digital Converter (ADC), 9 - block addressing.

In Fig. 2 shows time diagrams of 1 - signal AC from the mains, 2 - gate accumulation, 3 - gate reset, the 4 - momentum of change of address, 5 - output signal of the integrator 6 - pulse start ADC.

In Fig.3 shows a block diagram of the lock block.

In Fig.4 shows a structural diagram of the locking element, in the form of key.

In Fig.5 shows a structural diagram of the locking element, in the form of switch.

As shown in Fig. 1, the signal input units switching westline survey sensors, connected to the signal inputs of the device. The lock block 2 is designed to disable all channels n-1 switching blocks 1 and connection of n-1 inputs of the switch 3 to the shared bus device. Switch 3 is used to carry out the survey of groups of sensors. Buffer 4 is designed to eliminate the effect of subsequent stages in the operation of the switch 3, providing a high input and low output impedance. The rectifier 5 is designed to highlight the positive half cycles of the input voltage and performed by well-known circuit including operational amplifier (op-amp), two resistors, two diodes. TCIS 6 consists of k resistive adders, switch demultiplexer (Fig.1 not shown) and is designed to scale the output signal of the buffer 4 and the rectifier 5. Adders are a chain of weighting resistors, specifying the number of values of the transfer coefficients of the integrator 7, and the switch TCIS 6 provides the connection of the outputs of the adders to the entrance of the latter. Install the required gear ratio is controlled by the demultiplexer TCIS 6. The integrator 7 is executed on the OS with the condenser and the key in the feedback circuit. The OS is an active element of the integrator 7, provided naznachen to convert accumulated by the integrator 7 signal into a digital code. Block addressing 9 generates an address code channel to control the switching blocks 1, address code channel group for control of the lock block 2 and switch 3, code gear ratio to control TCIS 6. If the data collection system uses a survey with a random sample, then in block 9 case is used. The write control codes in the specified register from the external storage device with pulses of a change of address received from the external control device, with the control code consists of three parts. The first part represents the address code channel group, the second code gear ratio, the third address code channel. If the data acquisition system uses the principle of progressive polling channels, the block 9 is used, the counter and logic circuit forming the codes of the transmission coefficient. Low-order bits of the counter represent the address code channel, and the high address code group. Under the influence of these codes address logic circuitry generates the necessary codes transfer coefficient. Management counter provides an external control device with pulses of the address change. The control signals mode 8, also formed by the external control device according to the chart of the operation of the claimed device (Fig.2).

As shown in Fig.3, the lock block 2 includes a decoder 10, the locking elements 11, and the first inputs of the latter are the signal inputs of the lock block 2, second input connected to the shared bus device and the outputs are the signal outputs of the lock block 2. The address inputs of the decoder 10 are the address input unit 2, and outputs connected to the control inputs of the locking elements 11 and are the control outputs of the unit 2. The locking element 11 may be made in the form of a key or switch, while the control input is a control input of the locking element 11. When using the key as the locking element 11 (Fig.4), its input connected to the first input and output of the locking element 11 and the output to the second input. When using the switch as the locking element 11 (Fig.5), its first input is connected to the first input element 11, the second input to the second input and the output to the output of the locking element 11. The choice of a specific implementation of the locking element 11 is determined by the block structure is the switching unit 1, in the corresponding signal circuit block lock 2 key is used. When implementing the switching unit 1 in the form of a switch output connected to the input of the scaling element is executed on the OS, the corresponding signal circuit block lock switch 2 is used. The output of the specified element is the output of the block 1.

The device operates as follows. The analog signals are sent to the inputs of switching blocks 1. The first switching unit 1, in accordance with the address code of the channel set by the block 9, connects the output of the respective sensor to the input of the switch 3 through the first locking element 11 of block 2 (Fig. 3), the key of this element is in the open state (Fig. 4). The key remaining elements 11 are in closed condition, samarajiva n-1 inputs of switch 3 on a common bus device. It is obvious that interference from the input analog signals to the other blocks 1 are bridged by a common bus device. If the locking element 11 is made in the form of a switch (Fig.5, the first switching unit 1, the switch is in position "a", and the output signal of the first switching unit 1 receives che is ogenyi "b", samarajiva n-1 inputs of switch 3 on a common bus device. The switch 3, in accordance with the address code channel group, established by the block 9, connects the outputs of blocks 1 to the input buffer 4, the output signal of the latter is fed to the input of the rectifier 5 and the input unit 6. With the help of block 6, the gain of the integrator 7 is installed in accordance with the code of the gain generated by the block 9. After scaling the signals fed to the input of the ADC 8. The conversion cycle of the device begins with the installation of the integrator 7 to its original state, i.e., the cumulative discharge of the capacitor of the integrator 7 to "zero". For this purpose, the control input key integrator 7 is supplied to the reset gate (Fig.2, chart 3). Simultaneously to the input of block addressing 9 enters the momentum change of address, which is the installation code control (Fig.2, chart 4). The control code is supplied to the address inputs of blocks 1, switch 3, block 2, TCIS 6. Under the influence of the code address of the channel includes corresponding channels of the blocks 1. Under the influence of the code addresses the group channel decoder 10 generates a signal block for blocks 1 and the locking elements 11. In the absence of a blocking signal on the control input is adequate input switch 3 from the shared bus device and provides passing the analog signals to the input of the switch 3. Under the influence of the code addresses the group of channels included in the channel 3 switch. It is obvious that the inclusion of the selected channel inputs of the remaining channels of the switch 3 is connected to the shared bus device via the locking elements 11. Through the buffer 4, the AC voltage is fed to the input of the rectifier 5 and the first input unit 6. When processing input signals of a high level function buffer 4 performs a voltage follower. Using the proposed device for processing signals of a low level function of the buffer amplifier 4 does. If the first input unit 6 receives the positive half-wave of the input voltage, the second input will receive the inverted positive half-wave. Since the transfer ratio of the second input unit 6 at 2 times the gear ratio at the first input, and the gain of the integrator 7 is negative, then at the output U7>0. When a negative half-wave of the input voltage at the output of the rectifier 5 U5=0. At the first input unit 6 receives the negative half-wave of the input voltage and the output of the integrator 7 U7>0. Code gear ratio from the output of block addressing 9 is supplied to the address input TCIS 6. Under the influence of the criminal code which moves the switch unit 6. The specified switch, connecting the respective outputs of the adders unit 6 to the inverting input of the shelter of the integrator 7, changes the gear ratio of the latter in predetermined limits in such a way as to ensure the coordination level between applicants with different types of sensors, signals and dynamic range of the ADC 8. Upon receipt of the strobe accumulation control input unit 6, the integrator 7 performs signal accumulation time is equal to or a multiple of a whole number of periods of the mains voltage supply (Fig.2, chart 1). During this time there is a charge of the capacitor 7 to a certain voltage level. After the end of the gate accumulation this value is stored by the integrator 7 during the conversion time of the ADC 8 until the end of the conversion cycle, i.e. before the next strobe reset (Fig.2, chart 5). ADC 8 converts the accumulated signal into a digital code by the start signal (Fig.2, chart 6).

Compared with the prototype of the proposed device, there is virtually no error due to the residual resistance of the open channel switch. When using switches type CT this resistance is rOTC=100 Ohms. If resistance, good discharge performance is B>to=100% 100 Ω/500000 Ω=0,02%.

In the proposed device when the input impedance of the buffer is equal to 500 Mω, the error will be 1000 times less. In addition, the attenuation of the input signal when open keys, which characterizes the degree of mutual influence channels,

To=20 lg UI/Up,

where UItest the input voltage,

Upthe voltage noise,

in the prototype is To=20 lg 6000 mV/12 mV=54 dB

The calculation of Upmade taking into account migratory capacities of open channelsCR=0,5 pF, rOTC=100 Ω, f=400 Hz, the total number of channels is 64.

In the proposed device

To=20 lg 6000 mV/1 mV=76 dB,

given m=4 (m is the number of channels unit 1), n=16 (n is the number of channels 3 switch). Let the basic error of conversion in the prototype 0.3% additional error switching due to the mutual influence channels

K1=100% Up/UI=0,2%.

The total error of conversion will be

1= 0,3%+to+K1= 0,52%.

With the same basic error converting the combined error of the proposed device will be

=0,3% + 100% 1 mV/6000 mV MX 0.317%.

Thus, when obrabotannykh above description and graphic materials, the proposed device is compared with the prototype has a higher conversion accuracy by reducing errors switching, which is implemented by using a buffer with high input impedance, and the lock block, which increases the attenuation of the input signal over secure channels. An additional advantage of the device is the possibility of increasing the number of channels of the device without increasing the error due to interference with the TV and high noise immunity, allowing the use of an ADC with higher resolution.

The proposed device for converting the AC voltage into the code implemented on the 590 chipset, 140, 564, 572 series.

SOURCES OF INFORMATION

1. U.S. patent 4190823, NCI 340/347 NT.

2. USSR author's certificate 1795543, H 03 M 1/12, G 01 R 19/22.

1. A device for converting AC voltage into the code, containing a switch, a rectifier, an input connected to the first input unit gear ratio, the second input is connected to the output of the rectifier, and the output to the input of the integrator, the output of which is connected to the input of analog-to-digital preobrazovatelei to the address inputs of the switch, and the second group of outputs to the address inputs of the mounting block transfer coefficient, characterized in that the device entered switching units, a lock block, a buffer, an input connected to the output switch and the output with the input of the rectifier, the signal inputs of the switching blocks are the device inputs and outputs connected to the signal inputs of the block lock signal outputs which are connected to the inputs of the switch, and control outputs - control inputs of the switching blocks, the address inputs are connected to the third group of outputs of block addressing, the first group of outputs of which are connected to the address inputs of the lock block, synchronization input block addressing is the first Manager of the input device, the control input setting unit gear ratio is the second managing input device, the control input of integrator - third managing input device, the input of the start of analog-to-digital Converter - fourth managing input devices.

2. The device under item 1, characterized in that the lock block includes a decoder and a set of locking elements, with the first inputs of the locking elements are the signal inputs is Locka lock the inputs of the decoder are the address inputs of the latter, and outputs connected to the control inputs of the locking elements and are the control outputs of the lock block.

3. The device according to p. 2, characterized in that the locking elements used keys, and the input of each key is connected to the first input and output of the corresponding locking element, and the output is the second input of the specified element, the control input key is a control input of the locking element.

4. The device according to p. 2, characterized in that the locking elements used in the switches, and the first input of each switch is the first input of the corresponding locking element, the second input of each switch is the second entry of the specified element, and the output of each switch is the output of the corresponding locking element, the control input switch is a control input of the locking element.

5. Device according to any one of paragraphs. 2 and 3, characterized in that at least one locking element used in the switch, and the first input of the switch avsecom switch is the output of the locking element, control input switch is a control input of the latter.

 

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