Powerful microwave mos transistor

 

(57) Abstract:

Use: electronic semiconductor technology, in particular when designing powerful silicon field-effect transistors designed for amplification and power generation in RF and microwave wavelengths. The inventive design of high-power microwave MOS transistor-containing semiconductor substrate with a high resistance and high-alloy layer of the first conductivity type, the elementary transistor cells stokovoj region of the second conductivity type, stock region of the second conductivity type, a channel region of the first conductivity type in the volume of the high-resistance layer of the substrate and the metal electrodes of the drain, source, gate on its front surface, V-groove in the high-resistance layer of the substrate, the metal wire connecting the source electrodes of the transistor cells through grooves with high-alloy layer of the substrate, the common electrode metal source on the back side of the alloyed layer of the substrate, grooves formed directly in stokovyh regions of the transistor cells and the angle of inclination of the side walls of the grooves with respect to the front surface of the high resistance layer pogloscyenii the side walls of the grooves are connected with each other in the plane spaced from the front surface of the high resistance layer of the substrate at a distance of 0,5...0,7 thickness of the high resistance layer of the substrate. In the high-resistance layer of the substrate along the vertical side walls of the grooves formed more highly alloyed region of the first conductivity type. The technical result of the invention is the improvement of frequency characteristics and power parameters powerful generator of MOS transistors. 1 C.p. f-crystals, 2 ill., 3 table.

The invention relates to electronic semiconductor technology, in particular to designs powerful silicon field-effect transistors designed for amplification and power generation in RF and microwave wavelength range.

Known power silicon n-channel UHF MOS transistor of the Japanese firm "Fujitsu" (article Y. Morita, H. Takahashi, H. Matayoshi, M. Fukuta"Si UHF MOS High-Power FET"-IEEE Transactions on Electron Devices, 1974, v. ED-26, 11, p. 733-734), comprising: a silicon substrate with a high resistance and high-alloyed layers of p-type conductivity; elementary transistor cells with n+-stokovoj and n-n+-stock areas in the volume of the high-resistance layer of the substrate and the metal electrodes of the drain, source, gate on its front surface; through-diffused p+-jumper in the high-resistance layer of pontoisemore function of the total area of the source; common metal electrode of the source on the back side of the alloyed layer of the substrate. The disadvantages of this design should include the complexity of the implementation of small (about 1....1.5 mm) lengths of the induced channel and providing a normally closed condition of the device at zero voltage on the gate.

Known power silicon n-channel UHF MOS transistor of the company "Ericsson" (catalogue of the firm "RF power transistors", June 1997, p. 733-734), in which the above disadvantages are eliminated by changing the configuration of the stock n-n+-region of the transistor cells and the introduction of their structure additional p-channel region with increased in comparison with the high-resistance layer of the substrate concentration of the acceptor impurities. However, in both of these devices are analogous to the strongest negative impact on the final electrical parameters have a connection diffused p+-jumpers. Indeed, being part of each elementary transistor cells and with decent size (not less than 1...1.6 times exceeding the thickness of the high resistance layer of the substrate) and a significant flow resistance, junction diffused p+-jumpers make a significant additional contribution to the step with the second structure, increase its interelectrode capacitances, to reduce the operating current flow, and as a result, deterioration of the frequency and power parameters of the device. In addition, the process of forming the diffusion of the p+-jumper accompanied by undesirable redistribution of dopants in silicon p-p+-substrate, which also should be attributed to the shortcomings of the aforementioned constructions.

As a prototype of the selected design microwave power silicon MOS transistor in which the source electrodes of the elementary transistor cells are connected with high-alloy layer of the substrate by means of additional metal tyre through cross-cutting V-shaped grooves formed in the high resistance layer of the substrate outside stokovyh regions of the transistor cells in front of one of their ends (the article "A 2.45 GHz power LD-MOSFET with reduced source inductance by V-groove connections," in proceedings of "International Electron Devices Meeting, Washington, 1985, December 1-4, p. 166-169). In the prototype, as well as in devices-analogues, high substrate layer performs the functions of the General area of the source, and the metal electrodes of the drain, source and gate elementary transistor cells are made in the form of narrow longitudinal stripes. The absence in the prototype connective difflock and their location in the transistor structure of the prototype due to:

the relatively large size of the base of the grooves (10 mkm μm), and, for this reason, the inappropriateness of placing them directly in the core of elementary transistor cells;

- elongation metal tires, connecting the drain electrodes of the elementary transistor cells with a common pads flow intended for connection to a transistor structure external wire leads;

- elongation metal tires, connecting the source electrodes of the elementary transistor cells with lower alloyed layer of the substrate;

- increase the total area of the transistor structure and increase its interelectrode capacitances;

- uneven transfer of potential from the common metal electrode of the source on the rear side of the alloyed layer of the substrate, to various parts istokpoga electrode elementary transistor cells;

and, as a result, the deterioration of frequency characteristics and power parameters of the device.

The aim of the present invention is to improve frequency characteristics and power parameters of the device.

This objective is achieved in that in the known construction the powerful microwave TIR-tramadoli, elementary transistor cells stokovoj region of the second conductivity type, stock region of the second conductivity type, a channel region of the first conductivity type in the volume of the high-resistance layer of the substrate and the metal electrodes of the drain, source, gate on its front surface, V-groove in the high-resistance layer of the substrate, the metal wire connecting the source electrodes of the transistor cells through grooves with high-alloy layer of the substrate, the common electrode metal source on the back side of the alloyed layer of the substrate, grooves formed directly in stokovyh regions of the transistor cells and the angle of inclination of the side walls of the grooves with respect to the front surface of the high resistance layer of the substrate 50...70oin the upper part of the high resistance layer and substrate 90oin its lower part, and inclined and vertical side walls of the grooves are connected with each other in a plane spaced from the front surface of the high resistance layer of the substrate at a distance of 0,5...0,7 thickness of the high resistance layer of the substrate, and, in addition, a high-resistance layer of the substrate along the vertical side walls of the grooves formed more highly alloyed region of the first type Prov is I: the new location of the grooves in the active region of the transistor structure; the new configuration of the grooves; a new, strictly regulated, the profile of the side walls of the grooves; the presence transistor structure additional diffusion regions arranged along the vertical side walls of the grooves. Thus, the claimed design meets the criteria of the invention of "novelty."

Accommodation grooves directly in stokovyh areas of elementary transistor cells allows you to:

- reduce the length and inductance of the metal tyres, connecting the source electrodes of unit cells through the slots with lower alloyed layer of the substrate, performing in a transistor structure (chip-chip) function of the total area of the source;

- reduce the length and inductance of the metal community, connecting the drain electrodes of unit cells with a total pads flow intended for connection to a transistor structure external wire leads;

- to reduce the total area of the transistor structure and reduce the value of its interelectrode parasitic capacitances;

to ensure uniform transfer of potential from the common electrode of the source through a high layer of the substrate and shortened sedentary transistor cells. The result of the above design changes is to improve the frequency and power parameters of the device.

The new configuration of the grooves enables the realization of the aforementioned advantages of the claimed design. Indeed, as will be shown in the following example, when regulated by the claims profile of the side walls of the grooves of their cross-section from the front surface of the high resistance layer of the substrate is narrowed 1.5...2 times compared with the same depth and size of the bottom V-shaped grooves used in the prototype, and such upgraded grooves is already possible topologically fit directly in place of dislocation stokovyh areas of elementary transistor cells almost without altering the pitch patterns.

When the inclination of the side walls of the grooves with respect to the front surface of the high resistance layer of the substrate under an angle of <50cross-section of the grooves in the front surface of the transistor structure significantly increases and becomes comparable with the dimensions of V-shaped grooves used in the prototype. This will significantly increase the step patterns with all the ensuing negative passedst and vertical side walls of the grooves in the plane spaced from the front surface of the transistor structure at a distance greater than 0.7 thickness of the high resistance layer of the substrate even when the optimal value of the angle 60..650.

When the inclination of the side walls of the grooves at an angle >70oto the front surface of the high resistance layer of the substrate occurs, the probability of a "shadow effect" during the deposition of the metal on the steep side walls of the grooves, which can lead to breakage of the connecting metal tire in the groove, and the lack of a dense communication stokovyh electrodes of the transistor cells with high-alloy shunt layers. In addition, if the angle >70osignificantly reduced and the area of contact stokovyh electrodes with shunt layers, which together may lead to insufficient neutralization in the inventive high-power microwave MOS transistor associated parasitic bipolar structure, and, as a result, decrease operational reliability of the device.

When the pair of inclined and vertical side walls of the grooves in a plane spaced from the front surface of the transistor structure at a distance of less than 0.5 of the thickness of the high resistance layer policiesa tires on the vertical walls of the grooves.

More highly alloyed region of the first conductivity type, located in the inventive high-power microwave MOS transistor along the vertical side walls of the grooves that are designed for a high-quality ohmic contact between the connecting metal tires and a high resistance layer of the substrate over the entire area of the side walls of the grooves, thereby facilitating more complete neutralization of concomitant parasitic bipolar structure, and consequently, improvement of the operational reliability of the device. In addition, the data region may store the operability of the inventive transistor structure even in case of breakages connecting metal tire on the vertical walls of the grooves.

In the present invention, a new configuration of the grooves, a new topological construction of the transistor structure, the presence of additional high-alloyed regions arranged along the vertical side walls of the grooves, provide the ability to create a powerful generator of MOS transistors, having compared with the prototype and analogues with enhanced functionality - higher gain, better frequency and the CN property. Therefore the claimed design meets the criterion of "inventive step".

This invention also essential, as it provides a significant technical effect consists in the possibility of creating a new generation of powerful microwave generator field-effect transistors with operating frequencies up to 2... 3 GHz and given in the load capacity of up to 100...150 W, opening new perspectives in the solution of important problems of complex microminiaturization electronic equipment, the improvement of its feasibility and mass-dimensional characteristics, in the solution of problems of electromagnetic compatibility of radio equipment working in confined spaces in a dense signal environment.

In figures 1 and 2 shows a cross-section structure of the inventive high-power microwave MOS transistor and a fragment of a cross-section of the inventive transistor structure according to the invention, where we have introduced the following notation:

1 is a semiconductor substrate;

2 - high resistance layer of the substrate;

3 - alloyed layer of the substrate;

4 - ishikawae the field of elementary transistor cells;

5 - stock area elementary transistor cells;

6 - to zithornah cells;

8 - insulator gate (gate dielectric);

9 - gate electrode elementary transistor cells;

10 - stokowy electrode elementary transistor cells;

11 is a drain electrode of elementary transistor cells;

12 - groove is in the high resistance layer of the substrate;

13 - sloping side walls of the grooves;

14 is a vertical side walls of the grooves;

15 - plane interface of inclined and vertical side walls of the grooves;

16 is a bottom of the grooves;

17 - the metal wire connecting ishikawae electrodes elementary transistor cells with high-alloy layer of the substrate;

18 - the common electrode and source of the transistor structure;

19 - additional high-alloyed region along the vertical side walls of the grooves;

20 - induced channel;

21 profile of the side walls of the grooves in the prototype;

hp- the thickness of the high resistance layer of the substrate;

Lto- the length of the induced channel;

Hto- the depth of the grooves;

dm- the distance between the vertical side walls of the grooves;

Dto- the distance between the inclined side walls of the grooves in a plane coincident with the outer surface of the transistor structure (sisternas structure and the plane of the pair of inclined and vertical side walls of the grooves;

Yjpthe depth of the channel regions of the elementary transistor cells in the high resistance layer of the substrate;

- the angle between the inclined side walls of the grooves and the outer surface of the transistor structure;

*- the angle of the side walls of the grooves to the front surface of the transistor structure in the prototype (54o44');

and the deviation of the line pair of inclined side walls of the grooves with the outer surface of the transistor structure from the vertical in the claimed high-power microwave MOS transistor;

b - deviation line pair of the side walls of the grooves with the outer surface of the transistor structure from the vertical in the prototype.

EXAMPLE

Based on the proposed structures were designed and fabricated experimental samples of high-power silicon n-channel MOS transistor with a step structure 27 μm (in this case, at the step structure refers to the distance between the centers stokovyh or stock areas unit cells) and the length of the induced channel Lto=of 0.9-0.95 microns, designed to operate at a supply voltage on the drain UcPete=28...35 V at frequencies up to 2.0.. . 2.5 GHz prototype with the same step patterns and length induzirovannom as source material oriented in the plane of (100) silicon p-p+-substrate thickness and resistivity high resistivity epitaxial R-layer, respectively, hp=7 μm andp-= 15 ASM. Constructive and technological features of the inventive transistor structure and prototype are presented in table 1. The design and topology of the structure was carried out on the basis of previously performed calculations, the results of which are shown in table 2. Given that under optimal for devices of this class the values of hp=7 μm, Nto=1,1 1,0... hpdm=30,1 μm, the implementation of step patterns in 27 microns is possible only if the width of the base of the grooves Dto...8,5 8,0 µm, and Dto=2A+d (see Fig.2), for the formation of grooves with Dto<8,5 µm line pair of the side walls with the front surface of the transistor structure should not deviate from the vertical by a distance a>of 2.6 μm. Presented in table 2 data (outlined contour) clearly show that the value of the parameter a>of 2.6 μm as time and is achieved when the slope of the side walls of the grooves to the face of the high-resistance layer of the substrate at an angle =50...70oand the pair of inclined and vertical side walls of the grooves at the level of THEt=0,5...0,7 hpfrom the front surface of the transistor structure. The smallest step structure is implemented in the 70othe front surface of the high resistance layer of the substrate at an angle*=54o44'. Base width of the grooves in this case, for the same value of hp=6...8 mm, Hto=1,0.. . 1,1 hpdg= dm=3 μm (the width of the bottom of the groove in the direction of the axis x in Fig.2 ) will be equal to: Dto=2b+dg2(hp/tg)+313...14 µm. When the step structure 27 μm to enter such groove directly in the locations of stokovyh regions of the elementary cells is not possible,

Ishikawae (5) and a drain (6) the field of elementary cells in the inventive microwave MOS transistor and the prototype was created by implantation of arsenic ions into the substrate, and channel R+- region (6) and shunt R+- interlayer (7) - implantation of boron ions. Additional high-alloyed p+- region (19) along the vertical side walls of the grooves in the proposed designs were formed by implantation of boron ions with subsequent diffusion justify embedded impurities at elevated temperatures. Insulator bolt (8) with a thickness of 0.16...of 0.18 μm was formed by thermal oxidation of silicon in an environment of dry oxygen and water vapor at a temperature of 950owith subsequent passivation formed of oxide of phosphorus-silicate glass. The electrodes of the shutter (9) of the elementary cells in the form of metal was formed by magnetron sputtering of molybdenum by photolithography. Grooves (12) in the inventive microwave MOS transistor with inclined (13) and vertical (14) side walls, paired in the plane (15), was created by the method of ion-plasma etching of silicon. In the prototype grooves with a uniform side walls, inclined to the front surface of the transistor structure at an angle*= 54o44' formed outside stokovyh p+- areas of elementary cells by the method of anisotropic etching of silicon in alkaline solution (KOH + isopropyl alcohol + H2O). The electrodes of the source (10), flow (11) of the elementary cells, the connecting bus (17) and the contact areas of the drain and gate were fabricated by photolithography from a pre-printed on the front surface of the high resistance layer of the substrate layer of aluminum with a thickness of 0,8...1,0 μm or three-layer metallic coating Ti-Pt-Au. A common source electrode (18) formed by the brazing transistor structure (crystal) to heat the surface of the metal housing of the CT-55 with a gold strip with a thickness of 20 μm at a temperature of 400...430oC. Channel p-type conductivity (20) were induced at the ends of the p-channel regions (6) adjacent to the front surface of the transistor structure, when applying Pooley in table 3. Analysis of the data given in tables 1 and 3 shows that for the same lengths of the induced channel, step patterns, the crystal sizes, quantities and sizes of the contact areas of the drain and gate on chip:

- proposed-transistor structure is implemented in 1.5 times more total channel width (the length of the shutter), 1.6 times higher slope S, 1.2 times higher ratio of slope to the input capacity (S/S11and), 1.3 times higher ratio of slope to the amount of input, loop through and output capacitances (S/(S11and+C12+Si)) compared with the prototype;

samples of the transistors of the proposed design give the load in continuous mode 1.5 times higher power pout with 1.55 times higher gain power Chickens and approximately 1.47 times higher efficiency stock chaincthat is the best frequency and power settings compared to the prototype. Higher values Chickens,cS/S11AndS/(S11And+C12+C22Iin the proposed design as time and provided their smaller length and inductance metal Tajinaste and inductance metal tires, connecting the drain electrodes of unit cells with a total pads runoff, more uniform transfer of potential from the common electrode of the source to istokov electrodes of unit cells.

Technical and economic efficiency of the proposed design compared to the prototype consists of:

a) create a powerful generator of MOS transistors with improved frequency and power settings;

b) reducing the size of the transistor structure and increasing thus the number of crystals on the plate at identical levels given in the load capacity;

) create a new generation of powerful generator MOS transistors L and S - band frequencies, opening new perspectives in the solution of important problems of complex microminiaturization electronic equipment, the improvement of its feasibility and mass-dimensional characteristics, in the solution of problems of electromagnetic compatibility of radio equipment working in confined spaces in a dense signal environment.

Sources of information

1 Si UHF high power MOS FET - journal "IEEE Transactions on Electron Devices", 1974, ED-21, No. 11, p. 733-734 (analog).

2. RF poweions - the collection of articles "International Electron Devices Meeting". 1985, December 1-4, R. 166-169 (prototype).

1. Powerful microwave MOS transistor-containing semiconductor substrate with a high resistance and high-alloy layer of the first conductivity type, the elementary transistor cells stokovoj region of the second conductivity type, stock region of the second conductivity type, a channel region of the first conductivity type in the volume of the high-resistance layer of the substrate and the metal electrodes of the drain, source, gate on its front surface, V-groove in the high-resistance layer of the substrate, the metal wire connecting the source electrodes of the transistor cells through grooves with high-alloy layer of the substrate, the common electrode metal source on the back side of the alloyed layer of the substrate, characterized in that that groove is formed directly in stokovyh regions of the transistor cells and the angle of inclination of the side walls of the grooves with respect to the front surface of the high resistance layer of the substrate 50. . . 70oin the upper part of the high resistance layer and substrate 90oin its lower part, and inclined and vertical side walls of the grooves are connected with each other in a plane spaced from the front surface wisp transistor on p. 1, characterized in that a high resistance layer of the substrate along the vertical side walls of the grooves formed more highly alloyed region of the first conductivity type.

 

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