Device sync cycles

 

(57) Abstract:

The invention relates to communication technology and can be used for receiving data from a downhole telemetry system using looped packets of digital data. The technical result is to increase the reliability of data reception by reducing the error in determining the phase of the signal caused by the difference of the frequencies of the signal generator at the transmitting and receiving ends of the link. The device further comprises four elements And two elements are NOT the source of the reference voltage, the comparator level, the counter signals, the tick count, the count interval correction. 1 Il.

The device relates to communication technology and can be used for receiving data from a downhole telemetry system using looped packets of digital data.

It is known device sync cycles, which is the closest to the technical essence and the achieved result (copyright certificate 1755387, published in bull. 30 for a 1992 MCI H 04 L 7/08), which contains a clock pulse, two pulse distributor, two block elements And the block decoding clock, gain taccom of the known device is the fact that what this device does not provide reliable data reception when the difference frequency of the transmitter and receiver, as well as receive data from the downhole telemetry system are unreliable.

The technical result, which directed the establishment of this invention is to increase the reliability of data reception by reducing the error in determining the phase of the signal caused by the difference of the frequencies of the signal generators on the sending and receiving ends of the link.

The technical result is achieved that the device sync cycles containing serially connected clock generator pulses, the first pulse distributor, the first block element And the second input of which is an information input device, the block decoding clock, the element OR the second pulse distributor, the second block elements And memory, shift register, an information input connected to a second input of the first block element And the output of the shift register is connected via the second block elements And inputs of the memory, the input signal is read which is associated with the corresponding output vetelino introduced four elements And, two elements are NOT the source of the reference voltage, the comparator level, the counter signals, the tick count, the count interval correction computing unit and a single-byte register, and the output element OR connected to the first input of the comparator and the first inputs of the first and second elements, And the output voltage reference is connected to the second comparator input level, the output of which is connected with the second input of the first element And through the first element is NOT - with the second input of the second element And the outputs of the first and second elements And is connected to the inputs of counter signals, the generator output clock pulses connected to the first input of the stroke counter and to the first input of the counter interval correction, the second input of the stroke counter is connected with the second output of the counter signals and the second input of the counter interval correction is connected to the first output of the computing unit, one input of which is connected with the output of the stroke counter and the other input of the computing unit connected to the first output counter signals, while the second output of the computing unit is connected to the input of register byte, the output of which is connected to a second input of the third element And to the input of verval correction is connected with the first inputs of the first and second elements, And the outputs are connected respectively to one and another corrective inputs of the clock.

The drawing shows a block diagram of a synchronization device in cycles.

Device sync cycles comprises a generator of clock pulses 1, two of the pulse distributor 2 and 3, two block elements And 4 and 5, the shift register 6, the block decoding clock 7, the memory 8, the element OR 9, reference voltage source 10, a comparator 11, the elements And 12,13, 14 and 15, the tick count 16 register 17 single-byte counter 18 interval correction computing unit 19, the counter 20 signals, the elements are NOT 21 and 22.

Clock 1 is connected to the input of the first distributor 2 pulses, the output of which is connected to the input of the first block 4 elements And the outputs of the latter is connected with the input of block decoding 7, whose output is connected to the inputs of the OR element 9.

Thus the output of the OR element 9 is connected to the input of the second dispenser 3 pulses, the output of which is connected to the input of the second block elements And 5, the other input of the latter is connected with the output of the shift register 6.

The output of the second block elements And 5 is connected to I is 11 and to the first inputs of the elements 12 And 13.

The outputs of the elements 12 And 13 are connected to the inputs of the counter 20 added.

And the output of the generator 1 clock pulses connected to the first input of the counter 16 measures and to the first input of counter 18 interval correction.

The second input of the counter 16 bars connected with the second output of the counter 20 signals, and the output of counter 18 interval correction is connected with the first inputs of the first 14 and second 15 elements And the outputs are connected respectively to one and another corrective inputs clock pulse 1.

One input of the computing unit 19 is connected to the input of the register 17 single-byte, the output of the latter is connected with the second input of the third element And 14 directly, and through the element is NOT 22 with a second input of the fourth element And 15. The outputs of the And elements 14 and 15 are corrective input generator 1 clock pulses.

The device operates as follows.

An information signal is fed to the input of the first block And 4. The first pulse distributor 2 is in a random state until the detection of the synchronization signal block 7 decode the signal. At the moment of detection of the synchronization signal of the second dispenser 3 pulses p 6 through the second block elements And 5 it is the second dispenser 3 pulses, listed in the in-phase condition with the received signal.

At the time of receipt of the synchronization signal from the output of the OR element 9 receives the signal through the elements 12 And 13 shall increase the content of counter 20 added to 1 or reset depending on the ratio of the signals at the comparator 11 is supplied from the output element OR 9 and the reference-voltage source 10.

From the comparator 11, the signal is applied to the element And 12 directly, and on an item And 13 through the element is NOT 21.

However, if the clock is less than a specified source 10 of the reference voltage threshold, the counter 20 is reset signals. If the level of the clock more set in the source 10 of the reference voltage threshold, the counter 20 signals recorded 1. Until then, until the counter 20 signals is in state 0, i.e., reset, at its first output connected to the input of the counter 16 bars, tension is holding the counter 16 bars in position "reset".

With the receipt of the counter 16 cycles of the generator 1 of the first clock is running counter 16 clock pulse from the counter 20 clock.

Once in the while the other output of the counter 20 signals, associated with the input of the computing unit 19, is formed triggering pulse of the computing unit 19, which is the accumulated number of cycles in the counter 16 bars.

In the computing unit 19 calculates the correction code according To the formula

< / BR>
where N is the number of accumulated signals in the counter 20 signals;

T - the expected number of cycles of the generator 1 clock pulses;

With the number of ticks recorded in the counter 16 bars.

The obtained correction code module To be written into the counter 18 interval correction, clocked by the pulse generator 1 clock pulses.

After that, the counter 18 interval correction on the output begins to develop momentum To every tick of the clock generator 1 pulse.

The pulse from the counter 18 interval correction through the elements And 14 or 15 is supplied to the corrective input generator 1 clock pulses.

This pulse passes either through the element And 14, or an item And 15 depending on the state of the register 17, the output of which is connected to the input element And 14 directly, and with the input element And 15 through the element is NOT 22.

With the computing unit 19 in the register 17 single-byte zapisyvaete the ode item And 14, at the output of the generator 1, an additional pulse. And when it arrives at the other corrective input generator 1 pulse from the output element And 15 at the output of the generator 1 next output pulse is suppressed.

Thus, the average frequency of the generator 1 is driven in accordance with the oscillator frequency shaper data transmitter (not shown) which leads to the reduction of errors of determination of the phase of the signal, and, consequently, increases the reliability of data reception.

Device sync cycles containing serially connected clock generator pulses, the first pulse distributor, the first block element And the second input of which is an information input device, the block decoding clock, the element OR the second pulse distributor, the second block elements And memory, shift register, an information input connected to a second input of the first block element And the output of the shift register is connected via the second block elements And inputs of the memory, the input signal is read which is associated with the corresponding output of the second pulse distributor, and the outputs of the block decoding is connected to the inputs pornoho voltage, the comparator level, the counter signals, the tick count, the count interval correction computing unit and a single-byte register, and the output element OR connected to the first input of the comparator and the first inputs of the first and second elements, And the output voltage reference is connected to the second comparator input level, the output of which is connected with the second input of the first element And through the first element NOT with the second input of the second element And the outputs of the first and second elements And is connected to the inputs of counter signals, the generator output clock pulses connected to the first input of the stroke counter and to the first input of the counter interval correction, the second input of the stroke counter is connected with the second output of the counter signals and the second input of the counter interval correction - with the first output of the computing unit, one input of which is connected with the output of the stroke counter and the other input of the computing unit connected to the first output counter signals, while the second output of the computing unit is connected to the input of register byte, the output of which is connected to a second input of the third element And to the input of the second element, the output of which is connected to a second whodo the cerned elements And, the outputs are connected respectively to one and another corrective input generator of clock pulses.

 

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