The unit of measurement errors in the channel

 

(57) Abstract:

The invention relates to telecommunications systems and computer engineering and can be used for measurement errors that distort the data in the channels of transmission or reproduction of information with inserts/deposition bit. The technical result is the determination of the size and location of inserts and deposition of bits in the data stream from the channel, minimizing the impact of adjacent additive errors and more accurate restoration of the flow of additive errors, minimizing the impact of inserts and deposition bit. For this purpose, the device parameters measurement error contains shift registers, the Converter singlesymbol in locators, myCitadel, counter, buffer relative locators, the comparison circuit codes, block finding significant relative locator, buffer substantial relative locator, buffer weights significant relative locators, the unit of decision errors, the block forming stream of the channel state. 16 Il., table 1.

The invention relates to telecommunications systems and computer engineering and can be used for measurement errors that distort given to the device, designed for testing of communication channels using a pseudorandom sequence (PN-sequence) [1] / reception part which contains two generator PN-sequence, two patterns of sequence comparison, the counter keeps count of the number of matching bits, four trigger and logic gates AND, OR, NOT.

The known device generates a stream of bits with errors detected in a received from channel test signal, by comparing the bit sequence of the test signal with the bits of the PN sequence is restored by the first generator. The device detects loss of synchronization (due to insertions or deposition bit) between the bit sequence of the test signal and the recovered PN sequence and then perform a second synchronization to prevent an incorrect formation of a stream of bits with errors. Determination of violation synchronization is performed using the second generator PN sequence by identification in the flow of erroneous bits shifted in phase PN sequence.

The drawbacks:

is a relatively high probability of an erroneous determination sync problems due to the small length of the analysis is isogo the number of false erroneous bits in the generated stream of bits with errors due to sync problems, due to the relatively large delay a decision on the restoration of synchronization;

- the inability of the measurement of the inserts or depositions of the bits and their location.

A device for measuring the level of errors in the channel [2], measuring the level of error in the data transfer process using PN-sequence. The device contains a serial-to-parallel Converter, the network correlator, the multiplier in a finite field, the comparison circuit, the buffer memory data, the number of additional blocks.

Device [2] as well as the device [1], generates a stream of bits with errors by comparing the bit sequence of the test signal with bits of the reconstructed network correlator PN-sequence. Network correlators maintains proper synchronization between the bit sequence of the test signal and the reconstructed PN sequence even in the presence of insertions or deposition of bits in the test signal. In the device [2] fixed adding false erroneous bits in the generated stream of errors due to sync problems.

The disadvantages of the device [2] are:

additive errors that are possible after stabilnosti the network output of the correlators, and therefore, to add to the stream of bits with errors of a certain number of incorrectly defined errors;

- the inability of the measurement of the inserts or depositions of the bits and their location.

It is known device [3] to determine violations of synchronization between the bit sequence of the test signal and recovered in the receiver PN sequence, providing for the restoration of synchronization to prevent an incorrect formation of a stream of bits with errors. The device comprises a generator PN-sequence diagram of the comparison of sequences of bits, i correlators, i threshold detector, the analyzer amounts mutually correlation functions, the tool bit slippage, parser error level.

To determine the sync problems i used correlators, each of which computes a mutually correlation function between one of the first segments of the reference PN sequence and adopted from channel test sequence. The output signals of the correlators are processed threshold detectors and added. The shift of the peaks in the received sum mutually correlation functions indicates a violation of synchronization. For agreda for each selected maximum.

The drawbacks:

- adding a sufficiently large number of false erroneous bits in the generated stream of bits with errors due to sync problems as possible a relatively large value of the time interval between insertion (loss) bits and re-sync generator PN sequence, which is discrete (i time period PN-sequence);

- the impossibility of sufficiently precise insertions or drop bits (only possible to determine the interval between two peaks in which they occurred).

The closest to the technical nature of the claimed invention is selected as a prototype device designed to measure the level of bit errors in the channel [4], contains two generator PN-sequence, two schemes compare sequences of bits, four shift register for delaying frames, four detector slippage (inserts or deposition) frames, counter erroneous bits, the counter slippage, the controller, different logic.

The device is a prototype for similar devices [1, 2, 3] generates a stream of bits with errors detected in a received from channel test signal by the PN generator. The device also detects loss of synchronization (due to insertions or dropped frames) between the bit sequence of the test signal and the recovered PN sequence and then perform a second synchronization to prevent an incorrect formation of a stream of bits with errors. The slippage detection and determination of their values is carried out using four detectors slips, each of which compares the recovered PN-sequence with one of the four interleaved sequence of bits of the test signal.

In contrast to the previously discussed devices [1, 2] device-prototype implemented by counting the number of slippages.

The disadvantages of the prototype include:

- determined by the slippage only a small number of frames (one or two);

additive errors that are possible after slippage, can lead to significant delays in the detection of synchronization and, thus adding to the count of erroneous bits a number incorrectly defined errors;

- lack of ability to measure the location of the erroneous bit and slips in the data stream.

Technical task Fig minimizing the influence of adjacent additive errors as well as a more accurate restoration of the flow of additive errors, minimizing the impact of inserts and deposition bit.

The technical problem is solved by the fact that in the known device, containing the first shift register, a second shift register, the comparison circuit sequence, and the input of the first shift register is an input device for the analyzed bit sequence, the first output of the first shift register connected to the input of the second shift register, the output of the second shift register connected to the first input of the comparison circuit of the sequences according to the invention introduced the Converter singlesymbol in the locators, the first myCitadel, the first counter, the buffer relative locators, the first comparison circuit codes, block finding significant relative locator, buffer substantial relative locators, the buffer weights significant relative locators, the unit of decision errors, the block forming stream of the channel state, and the inputs of the Converter singlesymbol in locators connected to the second outputs of the first shift register, the first inputs of the first vicites connected to the outputs of the Converter singlesymbol in locators, Deut what ml buffer relative locators, with the first inputs of the first circuit comparing the codes with the first inlet of finding significant relative to the locator, the outputs of the buffer relative locators connected with the second inputs of the first circuit comparing the codes with the second inlet of finding significant relative to the locator, the first output of the comparison circuit codes connected with the third input of block finding significant relative to the locator, the first output unit finding significant relative locator connected to the inputs of buffer substantial relative locators and with the first unit of decision-making errors, the second outputs of block finding significant relative locator connected to the inputs of buffer weights significant relative locators with the second inlet of decision errors, the outputs of the buffer substantial relative locators connected to third inputs of the unit of decision errors, the outputs of the buffer weights significant relative locators connected to the fourth inputs of the unit of decision errors, the first output unit decision errors connected to the first input of the processing unit thread States Cana of the channel state, the third output unit decision errors connected with the third inlet flow formation of the channel state, the fourth output unit decision errors connected with the fourth input unit of flow formation of the channel state, the fifth output unit of decision errors is the output of "Refusal of measurement devices, the first output block flow formation of the channel state is output, Strobe write", the second outputs of the block forming the flow channel States are outputs "error Type" device, the third output unit forming a flow channel States are outputs "Size error" the device, moreover, the block finding significant relative locator contains the first multiplexer, the first-eleventh bus shapers, first-sixth buffer registers, the first selector code of zero, random access memory, the first element And device initialization, the control unit, and the first inputs of the first multiplexer are the first inputs of block finding significant relative to the locator, the second inputs of the first multiplexer are the second inputs of block finding significant otia significant relative locator, the control input of the first multiplexer is connected to the first output control unit that outputs a first multiplexer connected to the data inputs of the first bus driver and inputs data of the second bus driver, the control input of the first bus driver connected with the second output control device, the control input of the second bus driver is connected to the third output control unit outputs the first bus driver connected to the address bus, the outputs of the second bus driver connected to the data bus, the first address inputs of the memory devices connected to the address bus, the second address input of random access memory connected to the third input of the first element And with the fourth output of the control device and the third output device initialization, the third address input of random access memory connected with the second input of the first element And the fifth output control device and the fourth device output device initialization, the control input read/write random access memory device connected to the first input of the first element And the sixth output control device, the input vyihodi data memory device connected to the data bus, the inputs of the first selector code of zero is connected to the address bus, the output of the first selector code of zero is connected to the fourth input of the first element And the data inputs of the first buffer register connected to the data bus, the first control input of the first buffer register is connected to the eighth output control device, the second control input of the first buffer register is connected to the ninth output control device, the outputs of the first buffer register connected to the data inputs of the third bus driver and inputs data fourth bus driver, the control input of the third bus driver is connected to the tenth output control device, the outputs of the third bus driver connected to the address bus, the control input of the fourth bus driver is connected to the eleventh output control unit outputs the fourth bus driver connected to the data bus, the data inputs of the second buffer register connected to the data bus, the first control input of the second buffer register is connected to the twelfth output control device, the second control input of the second buffer register is connected to the thirteenth output control device, rubs the years of the second buffer register connected to the data inputs of the fifth bus driver and inputs data sixth bus driver, the control input of the fifth bus driver is connected to the fifteenth output control unit outputs the fifth bus driver connected to the address bus, the control input of the sixth bus driver is connected to the sixteenth output control device, the outputs of the sixth bus driver connected to the data bus, the data inputs of the third buffer register connected to the data bus, the control input of the third buffer register connected to the seventeenth access control devices, the outputs of the third buffer register connected to the data inputs of the seventh bus driver and inputs data of the eighth bus driver, the control input of the seventh bus driver connected with eighteenth-output control device, the outputs of the seventh bus driver connected to the address bus, the control input of the eighth bus driver connected with nineteenth-output control unit that outputs an eighth bus driver connected to the data bus, the data inputs of the fourth buffer register connected to the data bus, the first control input of the fourth buffer register is connected with the twentieth access control device, the second control input h is atmospheric register connected to the data inputs of the ninth bus driver and with the inputs of the tenth data bus driver, the control input of the ninth bus driver is connected to the twenty-second output control unit that outputs the ninth bus driver connected to the address bus, the control input of the tenth bus driver is connected to the twenty-third output control unit outputs the tenth bus driver connected to the data bus, the data inputs of the fifth buffer register connected to the data bus, the control input of the fifth buffer register connected to the output of the first element And the outputs of the fifth buffer register connected to the data inputs of the eleventh bus driver and are the first outputs of block finding significant relative to the locator, the outputs of the eleventh bus driver connected to the address bus, the control input of the eleventh bus driver is connected with the control input of the sixth buffer register and the seventh output control device, the input data of the sixth buffer register connected to the data bus, the outputs of the sixth buffer register are second outputs of block finding significant relative to the locator, the first input device initialization and clock control unit connected to the bus of the second tevista initialization is connected to the bus initialization the first output device initialization is connected to the address bus, the second output device initialization is connected to the data bus, and the device initialization contains the second counter, the second multiplexer, the third multiplexer, the fourth multiplexer, the second selector code of zero, the second comparison circuit codes, twelfth bus driver, the thirteenth bus driver, fourteenth bus driver, and a clock input of the second counter is the first input device initialization, the second inputs of the second multiplexer is connected to the first inputs of the second differential amplifier codes and are the second inputs of the device initialization the first inputs of the second multiplexer and the second input of the third multiplexer is connected to the bus code of zero, the first inputs of the third multiplexer is connected to the bus unit code, the first outputs of the second counter is connected to the inputs of the second selector code of zero, with the second inputs of the second differential amplifier codes, with the third and fourth inputs of the fourth multiplexer and the input data of the fourteenth bus driver, the second outputs of the second counter is connected to control inputs of the fourth multiplexer and the criterion input of the second multiplexer, the second output of the comparison circuit codes connected with the control input of the third multiplexer, the outputs of the second multiplexer is connected to the first input of the fourth multiplexer, the outputs of the third multiplexer is connected with the second input of the fourth multiplexer, the outputs of the fourth multiplexer connected to the data inputs of the twelfth bus driver, the control input of the twelfth bus driver is connected with the control input of the thirteenth bus driver, with the control input of the fourteenth bus driver and is the third input device initialization, the outputs of the twelfth bus driver are the second output device initialization, the outputs of the thirteenth bus driver are the third and fourth outputs of the device initialization the outputs of the fourteenth bus driver are the first outputs of the device initialization, and the unit of decision-making errors contains the second myCitadel, third myCitadel, the first adder, a second adder, a third comparison circuit codes, the fourth comparison circuit codes, the fifth comparison circuit codes, sixth comparison circuit codes, the seventh circuit comparing the codes, the fifth alchemy comparison of sequences, the second element And the third element And the fourth element And the first inverter, JK flip-flop, a third selector code of zero, the multiplier is two, the element AND-NOT, and the second inputs of the second vicites connected with the first inputs of the third myCitadel, with the second input of the sixth multiplexer and the first input unit of decision errors, the first input of the fourth differential amplifier codes connected with the second inputs of the sixth circuit comparing codes and are the second inputs of the unit of decision errors, the first inputs of the second vicites connected with the second inputs of the third myCitadel, with the first inputs of the sixth multiplexer and are the third input unit decision errors, the second input of the fourth differential amplifier codes connected with the first inputs of the fifth circuit comparing codes and are the fourth input unit decision errors, the output of the fourth differential amplifier codes connected with the first Manager of the entrance of the fourth counter, with the control input of the sixth multiplexer, with the J input of the JK-flip-flop and the third input of the fourth element And the outputs of the sixth multiplexer connected to the first inputs of the first adder, the outputs of the third counter with the s in synchronity, the inverter output locators in synchronity connected with the second input of the comparison circuit sequences, the output of the comparison circuit sequences connected to the first input of the third element And the second inputs of the fifth circuit comparing codes and the first input of the sixth differential amplifier codes connected with the bus bar code threshold, the output of the fifth differential amplifier codes connected with the first input of the second element And the sixth output of the comparison circuit codes connected with the second input of the second element And the output of the second element And is connected to a second input of the third element And with the input of the first inverter and to the first input of the fourth element, And the output of the third element And is the fourth output unit decision errors, the output of the first inverter is the fifth output unit decision errors, the outputs of the second vicites connected to the first input of the fifth multiplexer and the first input of the third differential amplifier codes, the outputs of the third vicites connected with the second input of the fifth multiplexer and the second inputs of the third differential amplifier codes, the third output of the comparison circuit codes connected with the control input of the fifth multiplexer, a second input element AND IS NOT and is the second what about the selector code of zero, with the second inputs of the second adder and are the third outputs of the unit of decision errors, the inverted output of the third selector code of zero is connected to the fourth input of the fourth element And direct the output of the third selector code of zero is connected to the K input of the JK-flip-flop and the second managing input of the fourth counter, the clock input of the JK-flip-flop and a clock input of the fourth counter connected to the first bus clock signal, the inverted output of the JK-flip-flop is connected to a second input of the fourth element And the fourth element is the first access unit of decision-making errors, the outputs of the fourth counter connected to the inputs of the multiplier on the two outputs of the multiplier of two is connected with the first inputs of the second adder, the outputs of the second adder connected to the first inputs of the seventh circuit comparing the codes, the second inputs of the seventh circuit comparing codes connected with the bus bar code window size, the seventh output of the comparison circuit codes connected with the first input element AND the output element AND is connected to the third input of the third element And, moreover, the set of flow States of the channel includes a D-flip-flop, the EXCLUSIVE OR element, the fifth element And the sixth element, And the first e and the D-input of D-flip-flop is connected to the second input of the EXCLUSIVE OR element and is the fourth input unit of flow formation of the channel state, the clock input of D-flip-flop is connected to a second input of the fifth element And with the input of the second inverter, a clock input of the fifth counter, and bus of the third clock signal, the output of D-flip-flop connected to the first input of the EXCLUSIVE OR element and to the first input of the seventh multiplexer, the output of the EXCLUSIVE OR element connected to the first input of the fifth element And to the first input of the second element OR the output of the fifth element And connected to the first input of the first element OR the second input of the first element OR is connected with the second input of the second OR element, and is the first input unit of flow formation of the channel state, the output of the first element OR is connected to a second input of the sixth element And the first input of the sixth element And is connected to the fourth bus clock signal, the output of the sixth element, And is the first output of the processing unit thread of the channel state, the output of the second element OR is connected to the input load of the fifth counter, the data inputs of the fifth counter is connected to the bus unit code, the outputs of the fifth counter is connected with the first inputs of the eighth multiplexer, the second input of the seventh multiplexer is a second input unit of flow formation of the channel state, the second inputs of WOSM is rtor connected with the control input of the seventh multiplexer and with the control input of the eighth multiplexer, the output of the seventh multiplexer and the output of the second inverter are second outputs forming unit flow of the channel state, the outputs of the eighth multiplexer are the third output block flow formation of the channel state.

The interaction of the introduced functional blocks allows the use of the proposed device for measuring the parameters of error in any bit channels and get with it in real time directly to the flow conditions investigated channel, such as information about packages additive errors and gaps between them are also detailed information synchronization error (type error: insert or drop bits and the size of the synchronization errors - the number of bit insertions or deposition). Introduction (in addition to certain auxiliary elements) block finding significant locator 8 (capable of handling relative locators according to majority rule) to estimate the location of the processed bits in the test sequence allows to obtain accurate information about the synchronization errors in the investigated section of the sequence on the next stage of processing (block decision errors 11). Introduction Biochemy output unit decision errors 11.

The invention consists in the following. To detect synchronization errors are test sequence (M-sequence, sequence De brain, the modified sequence of De brain) where any are located in a row m-bit sequence (synchronically) uniquely determine its phase. Adopted from channel test sequence is converted into a stream of singlesymbol, in which there are two sequences of equal length (open). Based on the analysis of singlesymbol in each window are formed left and right assessment of the current location of the analyzed bit of the test sequence (located in the center between the Windows). The estimates obtained allow us to determine the presence and size of inserts or deposition bit on the analyzed area of the test sequence. In difference estimates can be judged on the size of the insert or drop. If the difference between the estimates is equal to zero, then insert or drop a bit in the analyzed area of the test sequence are missing. The use of majority rule analysis singlesymbol when determining assessment allows for high accuracy in localizing the synchronization errors of the national scheme proposed device parameters measurement errors in the channel; in Fig.2 shows a functional block circuit diagram of a finding of substantial relative locator of Fig.3 shows a functional diagram of the device initialization (block finding significant relative locator) of Fig.4 shows a functional block diagram of decision errors; Fig.5 shows a functional block circuit diagram of the formation of flow of the channel state, and Fig.6 shows a linear shift register with feedback for the case m=5, the generated data register M-sequence, and mapping table locators and singlesymbol for this sequence of Fig.7 is illustrated the principle of the replacement of two blocks of finding significant relative locator on one with buffering its output, and Fig.8 shows the algorithm of functioning of the unit finding significant relative locator of Fig.9 shows an example of the contents of the buffer relative locators and the corresponding contents of the four arrays (which are allocated in the memory device), and the table lists the values that are populated arrays at the beginning of the operation of the device of Fig.10 is a table of control signals y1...y23. the generated the Itza, explaining the operation of the processing unit thread of the channel state, and Fig.12 shows timing diagrams of the clock signals of the device parameters measurement errors in the channel of Fig.13-16 examples of device parameters measurement errors for various configurations of errors.

In the device description and the drawings, the following symbols are used:

m is the degree of the generating polynomial of the M-sequence (the number of steps linear shift register with feedback),

n - period pseudo-random sequence,

A - singlesymbol,

L - locator singlesymbol,

ST2 is a binary counter,

RG - register

SM - adder,

SB - myCitadel,

FIFO - buffer (set of registers connected in series m-bit buses),

BF - bus driver,

RAM - random access memory,

MUX - multiplexer,

SHA - bus address

SM - bus data

AP - device initialization

The SU - device management

INLOC - incoming relative latitude (in locator),

OUTLOC - facing relative latitude (out locator),

The ENABLE signal enable block finding significant relative locator

RLOC - suseo - significant relative locator-left of the window (left relative locator),

LNUM - weight substantial relative locator-left of the window,

RRLOC - significant relative the locator the right hand window (right relative locator),

RNUM - weight substantial relative locator right of the window,

SV - Central bit (common for the left and right Windows) (central bit),

SYNCERR, SE - error signal synchronization (sync error),

INS/DEL - type synchronization error: insert or drop bits (insertion/deletion),

DL is the size of the synchronization errors (number of bits),

NOISE - signal extraction parameters measurement errors (noise),

ADDERR, AE - signal additive error,

WRITE - strobe write to the external device information registration error,

ERRTYPE - type error (error type),

ERRSIZE - size error size),

WINSIZE, WS - buffer size relative locators (window size),

INIT - the initialization signal for device initialization block finding significant relative locators

THRESHOLD - the threshold for significant weights relative locators left and right Windows,

CLK is the first clock signal,

CLK2 - second clock,

CLK3 is the third clock signal,

CLK4 fourth clock signal,

Num - array used to store the number corresponding locators (number),

Loc - the array in which to store locators in descending order of their frequency of occurrence in the buffer relative locator (locator),

Pos - array are mutually inverse to the array Loc (position),

LB - array for storing the left edge of the group, equal amounts of locators, as if the locators were sorted (left bound),

Numi, Loci, Posi, LB1 - a designation that reflects the contents of the buffer registers REG1, REG2, REG3, REG4 and related to the processing of incoming substantial relative locator (INLOC),

Num2, Eoc2, Pos2, LB2 - a designation that reflects the contents of the buffer registers REG1, REG2, REG3, REG4 and related to the processing of facing significant relative locator (OUTLOC),

ROM is permanent memory.

The unit of measurement errors (Fig.1) contains the first shift register (1), the second shift register (5), the Converter singlesymbol in locators (2), the first myCitadel (3), the first counter (4), the buffer relative locators (6), the first comparison circuit codes (7), block finding significant relative locator (8), buffer substantial relative locators (9), the buffer weights significant is the anal (12).

The input of the first shift register (1) is analyzed bit sequence. The first output of the first shift register (1) is connected to the input of the second shift register (5). The output of the second shift register (5) is connected to the first input of the comparison circuit sequences (52). The inputs of the Converter singlesymbol in locators (2) connected to the second outputs of the first shift register (1). The first inputs of the first vicites (3) are connected to the outputs of the Converter singlesymbol in locators (2), the second inputs of the first vicites (3) are connected to the outputs of the first counter (4), the outputs of the first vicites (3) are connected with the inputs of the buffer relative locators (6), with the first inputs of the first differential amplifier codes (7) and with the first inlet of finding significant relative locator (8). The outputs of the buffer relative locators (6) is connected with the second inputs of the first differential amplifier codes (7) and with the second inlet of finding significant relative locator (8). The first output of the comparison circuit codes (7) is connected with a third input of block finding significant relative locator (8). The first outputs of block finding significant relative locator (8) are connected to the inputs of buffer substantial the ka finding significant relative locator (8) are connected with the inputs of the buffer weights significant relative locators (10) with the second inlet of decision errors (11). The outputs of the buffer substantial relative locators (9) is connected with the third input unit decision errors (11). The outputs of the buffer weights significant relative locators (10) is connected to the fourth inputs of the unit of decision-making errors (11). The first output unit decision errors (11) connected to the first input of the processing unit thread States of the channel (12), the second output unit decision errors (11) is connected with the second input unit of flow formation States of the channel (12), the third output unit decision errors (11) is connected to third inputs of the processing unit thread States of the channel (12), the fourth output unit decision errors (11) is connected with the fourth input unit of flow formation States of the channel (12), the fifth output of the decision errors (11) generates a signal "Refusal" dimension for the device information registration error. The first output block flow formation States of the channel (12) generates a signal "Gate" write to device register information about the error, the second outputs of the processing unit thread States of the channel (12) form the signal "error Type" device registration inski" for device registration information about the error.

Block finding significant relative latitude (Fig.2) contains a first multiplexer (13), the first bus driver (15), the second bus driver (14), the third bus driver (17), the fourth bus driver (18), the fifth bus driver (20), the sixth bus driver (21), the seventh bus driver (23), the eighth bus driver (24), the ninth bus driver (26), the tenth bus driver (27), the eleventh bus driver (32), the first buffer register (16), the second buffer register (19), the third buffer register (22), the fourth buffer register (25), the fifth buffer register (31), the sixth buffer register (33), the first selector code of zero (28), random access memory (29), the first element And (30), the device initialization (34), the control unit (35).

The first inputs of the first multiplexer (13) are the first inputs of block finding significant relative locator (8), the second inputs of the first multiplexer (13) are the second inputs of block finding significant relative locator (8), the enable input of the control device (35) is the third inlet of finding significant relative locator (8). The control input is (13) connected to the data inputs of the first bus driver (15) and inputs data of the second bus driver (14). The control input of the first bus driver (15) is connected with the second output control device (35), the control input of the second bus driver (14) is connected with the third output of the control device (35), the outputs of the first bus driver (15) connected to the address bus, the outputs of the second bus driver (14) connected to the data bus. The first address inputs of RAM (29) connected to the address bus, the second address input of the random access memory device (29) is connected with the third input of the first element And (30), with the fourth output of the control unit (35) and with the third output device initialization (34), the third address input of the random access memory device (29) is connected with the second input of the first element And (30), with the fifth output control device (35) and with the fourth output device initialization (34), the control input read/write random access memory (29) connected to the first input of the first element And (30) and the sixth output control device (35), the input sample memory device (29) is connected with the twenty fourth output control device (35), the outputs of the data memory device (29) is connected with the first code (28) is connected with the fourth input of the first element And (30). The data inputs of the first buffer register (16) connected to the data bus, the first control input of the first buffer register (16) is connected to the eighth output control device (35), the second control input of the first buffer register (16) is connected to the ninth output control device (35), the outputs of the first buffer register (16) is connected to the data inputs of the third bus driver (17) and inputs data fourth bus driver (18). The control input of the third bus driver (17) is connected with the tenth output control device (35), the outputs of the third bus driver (17) connected to the address bus. The control input of the fourth bus driver (18) is connected with the eleventh output control device (35), the outputs of the fourth bus driver (18) connected to the data bus. The input data of the second buffer register (19) connected to the data bus, the first control input of the second buffer register (19) is connected with the twelfth output control device (35), the second control input of the second buffer register (19) is connected with the thirteenth output control device (35), the third control input of the second buffer register (19) is connected to the fourteenth output panel) and with inputs data sixth bus driver (21). The control input of the fifth bus driver (20) is connected to the fifteenth output control device (35), the outputs of the fifth bus driver (20) is connected to the address bus. The control input of the sixth bus driver (21) is connected with the sixteenth output control device (35), the outputs of the sixth bus driver (21) connected to the data bus. The data inputs of the third buffer register (22) connected to the data bus, the control input of the third buffer register (22) is connected with the seventeenth access control device (35), the outputs of the third buffer register (22) are connected with the inputs of the seventh data bus driver (23) and with the inputs of the eighth data bus driver (24). The control input of the seventh bus driver (23) is connected with the eighteenth access control device (35), the outputs of the seventh bus driver (23) connected to the address bus. The control input of the eighth bus driver (24) is connected with nineteenth output control device (35), the outputs of the eighth bus driver (24) connected to the data bus. Inputs data to the fourth buffer register (25) connected to the data bus, the first control input of the fourth buffer register (25) is connected with the twentieth o the first output control device (35), the outputs of the fourth buffer register (25) are connected with the inputs of the ninth data bus driver (26) and with the inputs of the tenth data bus driver (27). The control input of the ninth bus driver (26) is connected with the twenty-second output control device (35), the outputs of the ninth bus driver (26) connected to the address bus. The control input of the tenth bus driver (27) is connected with the twenty-third output control device (35), the outputs of the tenth bus driver (27) connected to the data bus. The data inputs of the fifth buffer register (31) connected to the data bus, the control input of the fifth buffer register (31) is connected to the output of the first element And (30), the outputs of the fifth buffer register (31) is connected to the data inputs of the eleventh bus driver (32) and are the first outputs of block finding significant relative locator (8). The outputs of the eleventh bus driver (32) connected to the address bus, the control input of the eleventh bus driver (32) is connected with the control input of the sixth buffer register (33) and the seventh output control device (35). The data inputs of the sixth buffer register (33) connected to the data bus, the outputs of the sixth puff the first input device initialization (34) and to the clock input of the control device (35) is supplied to the second clock signal, on the second input device initialization (34) is the code for the window size, the third input device initialization (34) is supplied to the initialization signal, the first output device initialization (34) connected to the address bus, the second output device initialization (34) connected to the data bus.

Device initialization (Fig. 3) contains a second counter (36), a second multiplexer (39), the third multiplexer (40), the fourth multiplexer (41), the second selector code of zero (37), the second comparison circuit codes (38), twelfth bus driver (42), the thirteenth bus driver (43), the fourteenth bus driver (44).

The clock input of a second counter (36) is the first input device initialization (34). The second inputs of the second multiplexer (39) is connected with the first inputs of the second differential amplifier codes (38) and are the second inputs of the device initialization (34). On the first inputs of the second multiplexer (39) and the second input of the third multiplexer (40) is code of zero, to the first inputs of the third multiplexer (40) is fed code units. The first outputs of the second counter (36) are connected with inputs of the second selector code of zero (37), with the second inputs of the second differential amplifier codes (38), third is(44). The second outputs of the second counter (36) is connected with the control input of the fourth multiplexer (41) and inputs data of the thirteenth bus driver (43). The output of the second selector code of zero (37) is connected with the control input of the second multiplexer (39). The second output of the comparison circuit codes (38) is connected with the control input of the third multiplexer (40). The outputs of the second multiplexer (39) connected to the first input of the fourth multiplexer (41). The outputs of the third multiplexer (40) connected with the second input of the fourth multiplexer (41). The outputs of the fourth multiplexer (41) is connected to the data inputs of the twelfth bus driver (42). The control input of the twelfth bus driver (42) is connected with the control input of the thirteenth bus driver (43), with the control input of the fourteenth bus driver (44) and the third input device initialization (34). The outputs of the twelfth bus driver (42) are the second output device initialization (34), the outputs of the thirteenth bus driver (43) are the third and fourth outputs of the device initialization (34), the outputs of the fourteenth bus driver (44) are the first outputs of the device ini is myCitadel (46), the first adder (50), a second adder (65), the third comparison circuit codes (60), the fourth comparison circuit codes (47), the fifth comparison circuit codes (54), the sixth comparison circuit codes (55), the seventh circuit comparing codes (66), the fifth multiplexer (61), the sixth multiplexer (48), the third counter (49), the fourth counter (63), the Converter locators in synchronity (51), the comparison circuit sequences (52), the second element And (56), the third element, And (53), the fourth element And (59), the first inverter (57), JK flip-flop (58), the third selector code of zero (62), a multiplier of two (64), AND (67).

The second inputs of the second vicites (45) is connected with the first inputs of the third vicites (46), with the second input of the sixth multiplexer (48) and are the first inputs of the unit of decision-making errors (11). The first input of the fourth differential amplifier codes (47) is connected with the second inputs of the sixth differential amplifier codes (55) and are the second inputs of the unit of decision-making errors (11). The first inputs of the second vicites (45) is connected with the second inputs of the third vicites (46), with the first inputs of the sixth multiplexer (48) and are the third input unit decision errors (11). Second input of the fourth differential amplifier codes (47) is tion of errors (11), the fourth output of the comparison circuit codes (47) is connected to the first Manager of the entrance of the fourth counter (63), with the control input of the sixth multiplexer (48), with the J input of the JK-flip-flop (58) and with the third input of the fourth element And (59). The outputs of the sixth multiplexer (48) is connected with the first inputs of the first adder (50). The outputs of the third counter (49) is connected with the second inputs of the first adder (50), the outputs of the first adder (50) connected to the Converter locators in synchronity (51), the inverter output locators in synchronity (51) is connected with the second input of the comparison circuit sequences (52), the output of the comparison circuit sequences (52) connected to the first input of the third element And (53). On the second inputs of the fifth differential amplifier codes (54) and the first input of the sixth differential amplifier codes (55) is the code threshold. The fifth output of the comparison circuit codes (54) connected to the first input of the second element And (56). The sixth output of the comparison circuit codes (55) is connected with the second input of the second element And (56). The output of the second element And (56) is connected to a second input of the third element And (53) with the input of the first inverter (57) and to the first input of the fourth element And (59). The output of the third element And (53) is the fourth output unit decision is to (11). The outputs of the second vicites (45) connected to the first input of the fifth multiplexer (61) and to the first inputs of the third differential amplifier codes (60). The outputs of the third vicites (46) is connected with the second input of the fifth multiplexer (61) with the second inputs of the third differential amplifier codes (60). The third output of the comparison circuit codes (60) is connected with the control input of the fifth multiplexer (61), with the second input element AND-NOT (67) and the second output unit decision errors (11). The outputs of the fifth multiplexer (61) is connected to the input of the third selector code of zero (62), with the second inputs of the second adder (65) and are the third output unit decision errors (11). Inverted output of the third selector code of zero (62) is connected with the fourth input of the fourth element And (59), a direct output of the third selector code of zero (62) connected to the K input of the JK-flip-flop (58) and with the second Manager of the entrance of the fourth counter (63). To the clock input of the JK-flip-flop (58) and to the clock input of the fourth counter (63) is served first clock signal. Inverted output of the JK-flip-flop (58) is connected to a second input of the fourth element And (59), the output of the fourth element And (59) is the first output of the decision under the (64) is connected with the first inputs of the second adder (65), the outputs of the second adder (65) is connected with the first inputs of the seventh circuit comparing codes (66). On the second inputs of the seventh circuit comparing codes (66) is the code for the window size, the seventh output of the comparison circuit codes (66) connected to the first input element AND-NOT (67), the output of element AND-NOT (67) is connected to the third input of the third element And (53).

The set of flow States of the channel (Fig.5) contains a D-trigger (68), the EXCLUSIVE OR element (69), the fifth element And (70), the sixth element, And (75), the first element OR (71), the second element OR (72), a second inverter (74), the fifth counter (73), the seventh multiplexer (76), the eighth multiplexer (77).

D-input of D-flip-flop (68) is connected with the second input of the EXCLUSIVE OR element (69) and is the fourth input unit of flow formation States of the channel (12), the clock input of D-flip-flop (68) is connected to a second input of the fifth element And (70), with the input of the second inverter (74), with a clock input of the fifth counter (73) and at a third clock signal, the output of D-flip-flop (68) connected to the first input of the EXCLUSIVE OR element (69) and to the first input of the seventh multiplexer (76). The output of the EXCLUSIVE OR element (69) is connected to the first input of the fifth element And (70) and to the first input of the second element OR (72). The output of the translation language is replaced with the second input of the second OR element (72) and is the first input unit of flow formation of the channel state (12). The output of the first OR element (71) is connected to a second input of the sixth element And (75). At the first input of the sixth element And (75) is supplied to the fourth clock signal, the output of the sixth element And (75) is the first output of the processing unit thread States of the channel (12). The output of the second OR element (72) is connected to the input load of the fifth counter (73). The data inputs of the fifth counter (73) is the code unit, the outputs of the fifth counter (73) is connected with the first inputs of the eighth multiplexer (77). The second input of the seventh multiplexer (76) is the second input unit of flow formation of the channel state (12). Second input of the eighth multiplexer (77) are the third inputs of the processing unit thread States of the channel (12). The output of the second inverter (74) is connected with the control input of the seventh multiplexer (76) and with the control input of the eighth multiplexer (77). The output of the seventh multiplexer (76) and the output of the second inverter (74) are second outputs forming unit flow state of the channel (12). The outputs of the eighth multiplexer (77) are the third output block flow formation of the channel state (12).

The operation of the device parameters measurement errors in the channel is based on the use as a test item is defined consecutive m-bit sequence is uniquely determined by its phase (the location of all bit sequences). Such sequences are M-sequences, the binary sequence De brain, as well as modified binary sequence De brain.

M-sequence is a binary linear recurrence sequence, each member of which number j+m is a linear combination of the previous m members:

aj+m=c1aj+m-1+c2aj+m-2+...+cmaj,

where the coefficients Cktake values from a binary field. To construct such a sequence it is enough to know m consecutive symbols (bits).

M-sequence has a period of n= -2m-l (m - degree of the generating polynomial of the sequence). Sampling from a sequence of n taken consecutive m-bit symbols is a permutation of numbers from 1 to 2m-1 Aj=(aj, aj+1, . . . aj+m-1), j=0,1,..., n-1. In the invention ASjwill be called singlesymbol, and the index j locator singlesymbol (locator is actually the serial number of singlesymbol on the same period of the test sequence). When this element andjwill be called Synchronica, and the index j at him - locator Synchronica.

In Fig. 6 the 5+x2+1 (in this case m=5), and the generated data register M-sequence. Subsequent bits of the M-sequence are located on the left relative to the previous bits. In Fig.6b shows a table of correspondence of locators and singlesymbol for this sequence. Following this sequence will be used to illustrate the operation of the device.

The determination of inserts and deposition using the test sequences can be performed as follows.

Adopted from channel test sequence is converted into a stream of singlesymbol, in which there are two sequences of the same length k, with a common synchronic andi:

(Ai+k-1ANDi+k-2... , ANDi+1ANDi)

and

(Ai-m+1, Ai-m,..., Ai-k+2-m+1, Ai-k+1-m+1).

In the invention, these sequences will be called respectively the left and right Windows.

In each window you can find the locators singlesymbol and recalculate them modulo n relation inhabit ai. Thus obtained two vectors of the estimated latitude of the current bit andi:

{L(Ai+k-1)-k+1, L(Ai+k-2)-k+2,..., L(A

Here L(Ai) denotes the operator locate the locator singlesymbol ANDi.

Analyzing these vectors it is possible to generate estimates of locators left Lland right Lr. As an estimate, it is advisable to choose a locator, which most often occurs in the vector window. In the invention it will be called essential locator. The number of occurrences of the locator in the vector window will be called its weight.

Significant locator uniquely determines the phase sequence in the window. On the significant difference of the left and right locators window L can be judged on the size of the insert Linsertionor loss Ldeletion.

Linsertion=(Lr-Ll) mod n; (1)

Ldeletion=(Ll-Lr) mod n.

If L=0 then insert or drop bits missing. The size of the inserts and deposition is defined to period n

M-sequence. Smaller values of Linsertionand Ldeletiondetermines that happened: insert or loss.

The location of the inserts or deposition in the test sequence is determined by the time of exceeding the weight of material left locator window over weight significant locator right of the window.

First, the flow of singlesymbol ANDiconverted into a stream of locators L(Ai). Then the locators are converted to relative locators rLiby subtracting from them i modulo n, where i is the variable that identifies the currently processed bit test sequence, which is incremented at each cycle of the device. The sequence of relative locators in the absence of errors will be a constant sequence. For any i-th bit of the test sequence corresponding to the locator can be restored by adding to the relative locator value of i modulo n.

To estimate the relative latitude of the current bit to the left and to the right in the sequence relative locators are two Windows:

{rLi+k-1, rLi+k-2,..., rLi+1, rLi}

and

{rLi-m+l, rLi-m,..., rLi-k+2-m+1, rLi-k+1-m+1}.

Significant relative locators these Windows will give an estimate of the relative locate the -rLl) mod n; (2)

Ldeletion=(rLl-rLr) mod n.

The unit of measurement errors in the channel works as follows.

m-bit shift register 1 (Fig.1) converts the input bit test sequence into a sequence of singlesymbol, which in turn Converter singlesymbol in the locator 2 is converted into a sequence of locators. The Converter singlesymbol in locators 2 can be implemented in ROM (capacity 2mm-bit words).

MyCitadel 3 subtracts from each locator at the input of the current value of the counter 4 with the variable i. Thus the sequence of relative locators, which output vicites 3 is fed to the input of the buffer relative locators 6. In the case of use as a test sequence M-sequence in the reference test sequence is missing a zero singlesymbol (Fig.6), which corresponds to the locator 2m-l (all units). But it can be found in the adopted from channel test sequence errors. Therefore, myCitadel 3 must track the emergence input locatorm-l and issue byggmester in the reference sequence wrong locators on the decision about the presence of synchronization errors. In the case of use as test sequences De brain is not required and myCitadel 3 is the usual scheme of subtraction (as the period of the sequence and, accordingly, the module is equal to n=2m).

The shift register 5 is designed to delay bits of the test sequence, which is then used for the detection of additive errors. This delay is necessary to agree upon the adoption of the decision on the presence of additive errors and synchronization errors. The number of stages of the shift register 5 is WINST7E-1 (one less than the window size).

Block finding significant relative locator 8 on the basis of which put the majority principle, in each step generates a locator (RLOC), which at the moment more than any other locators found in the buffer relative locators 6. This significant locator corresponds to the weight (NUM), i.e. the number of occurrences of the locator in the buffer relative locators 6, which is also present on the output unit 8. The number of stages of the buffer relative locators is WINSIZE (window size) and should not exceed threshold 2m-1 (this is due to the capacity of random access memory 29 in the block nahorodny from him relative locators are the same, processing is not required and substantial relative the locator does not change. Therefore, the block finding significant relative locator is activated only if the incoming and outgoing relative locators different. The enable signal (ENABLE) block finding significant relative locator 8 is formed by the comparison circuit code 7. In the absence of any errors block finding significant relative locator 8 is inactive.

Thread substantial relative locators and their weights is delayed by the buffer substantial relative locators 9 and buffer weights significant relative locators 10, respectively, which contain WTNSIZE+m-2 degrees each. Locators and weights on the inputs of the buffers correspond to the left window, and detained locators and detained weight on the output buffers correspond to the right window. The use of a single block of finding significant relative locator for two Windows greatly simplifies the device. This is possible due to the complete functional equivalence aggregate, 6, 7, 8, 9 and 10 blocks of the device (as illustrated in Fig.7a) the aggregate of the blocks shown in Fig.7b.

Block making resenes and RRLOC), as well as the values of their weights (LNUM and RNUM) makes a decision about the presence in a given time synchronization errors (insert/drop bit). In case of detection of synchronization errors on the output unit of decision errors 11 given the signal SYNCERR and accompanying signals: INS/DEL (the type of the detected synchronization error: insert or loss) and DL (size synchronization errors - the number of bits). The unit of decision errors is also significant relative to the locators restores the correct value of the Central bits of the analyzed area of the test sequence and makes comparison with its actual (detainees) value, which is supplied from the second shift register 5. In the case of inequality of these bits is fixed additive error. If this error was not caused by insert bits, then the output of decision errors 11 receive a signal about the presence of additive errors ADDERR. If the level of additive errors exceeds a threshold, and significant weight relative locators decreased so that it is impossible correct decision errors at the moment, given the signal NOISE (the impossibility of a correct measurement pairs is about all issued by the unit of measurement error information at the moment is wrong, and this should be taken into account in subsequent processing flow of the channel state.

The set of flow States of the channel 12 on the basis of information coming from the unit of decision-making errors 11, forms for registration device error information gates write WRITE and accompanying them with information about the state of the channel for a certain period of time: the type of the error ERRTYPE and the size of the error ERRSIZE. Flawless condition and additive errors are going to block the formation of flow of the channel state in the packages. The unit are 4 types of States of the channel, as shown in the table.

Let us consider the operation of the major blocks of the unit of measurement errors in the channel.

Block finding significant relative latitude (Fig.2) is a machine that contains random access memory in which selected four of the same memory location, six buffer registers, device management, device initialization and the number of auxiliary elements. This machine allows you to implement the following simple operations: the data transfer between the memory device and one of the four registers, the data transfer between the two Rega (subtraction unit) registers. The forwarding operation is implemented as follows. Forwarding data from one register to another is made directly through the data bus. The data transfer between the cell random access memory device and one of the four registers is also available through the data bus, but requires selection of one of the four memory areas by drawing on the high-order bits of the address bus values from zero to three, and the low-order bits of the address bus is the cell number. The signals y1...y23determine the source and receiver during data transfer, as well as specify the type of arithmetic operation to the buffer registers.

Block finding significant relative locator implements the algorithm shown in Fig.8. The algorithm can be divided into two independent parts: processing incoming locator and then the processing goes locator. In the right part of the table shows the contents of each of the four buffer registers (16, 19, 22 and 25) to perform the operation specified in the left half of the table.

Dedicated in the memory device, four memory designed to store the following arrays. In the array Num stored number corresponding relative Loka is an Array of Loc is designed to store locators in descending order of their quantity, i.e. at address zero is stored locator, often occurring at the moment in the buffer relative locators (significant locator), and the oldest address is stored locator, least frequently occurring currently in the buffer relative locators (index in the array is a sequential number locator). Array Pos is designed to store the positions of the locators in the sorted array (index in the array is the locator). Array Pos is mutually opposite to the array Loc, i.e., for arrays Loc and Pos are the ratio of Loc[Pos[i]]=i and Pos[Loc[i]]=i, where i is an arbitrary index. Array LB is designed to store the left edge of the group, equal amounts of locators, as if the locators were sorted.

In Fig.9a shows an example of the contents of the buffer relative locators 6 and the corresponding correct the contents of the four arrays (Num, Loc, Pos and LB) block of finding significant relative locators 8 for the case m=3.

A selector code of zero 28 and item And 30 is monitored entry in the array locator Loc at address zero. In this case, the value (significant relative locator) that is present on the data bus is written into the buffer register 31. In affect, the treatment of additional read operations of the array Loc at address zero to identify significant relative to the locator.

For the implementation of the algorithm (Fig.8) the control unit 35 provides for 21 quantum CLK2 issuing control signals y1...y23, shown in Fig.10. The signal24responsible for chip select memory device 29, is set to a logical unit in each clock cycle CLK2 some time after the establishment of the data on the address and data bus and is reset after a certain period of time, providing a guaranteed entry. Data at the output of finding significant relative locator 8 is significant relative to the locator and its weight) ready by the end of the 18th quantum CLK2.

Device initialization (Fig.3) is used for the initial filling of the cells of the memory device. At the beginning of the operation of the device parameters measurement errors in the channel is assumed that the buffer relative locators 6 is initialized to zero values. Therefore, the device initialization 34 fills four array with values given in the table in Fig.9D. Cell random access memory device 29 will be filled with the specified values after the 2m+2cycles after signal INTT. After that, signalize errors (Fig.4) operates as follows. Vycitalem 45 of the locator the right hand window is subtracted locator of the left window, and vycitalem 46 from the left locator window is subtracted locator of the right window. Both vicites perform subtraction modulo n. From the obtained two values of the comparison circuit 60 and the multiplexer 61 selects the smaller value of L, thereby determines the size of the synchronization error, which is present in the moment, within the two Windows. If L=0, the synchronization errors in the analyzed segment of the sequence is missing (this fact is determined by the selector 62 code of zero). The output of the comparison circuit codes 60, there is a code of logical unit in case of detection of insertion of bits and code logical zero in case of loss of bits (or if L=0).

If the detected synchronization error (inverted output of the selector 62 code of zero is a logical unit) and the weight is substantial relative locator-left of the window began to exceed the weight is substantial relative to the locator the right hand window (the output of the comparison circuit codes is a logical unit), as in the previous step (the state of the JK-flip-flop 58) it was Vice versa (significant weight relative to the locator the right hand window exceeded the weight semesterhours between the two Windows and requires registration. At this point, the output element And 59 present signal detecting synchronization errors (logical unit). Thus, information about the parameters of synchronization errors (INS/DEL, DL) is present all the time at the output of the decision-making errors, while the synchronization error is within the two Windows, but the signal detected is issued only when the center of synchronization errors is centrally located between the two Windows (where they are virtual overlap by one bit). In the absence of synchronization errors is reset JK flip-flop 58. The application of the JK-flip-flop in the circuit due to the need to eliminate the possible "bounce" the signal at the output of element 47 when detecting synchronization errors (logical zero to direct the output of the selector 62 code of zero), which will lead to the registration of more than one synchronization errors.

The chain elements 48, 49, 50, 51 (counter 49 and the adder 50 function modulo n) is used to recover the correct values of the Central bit. Using the multiplexer 48 selects significant relative locator with more weight. The counter 49 (it is signal CLK), and working modulo n, is shifted to the lower side (the p the I the inverse transform relative locator from the output of the multiplexer 49 in true latitude, which in turn Converter locators in synchronity 51 is converted into the correct bit, located in the center between the two Windows. In fact, the operation reverse to the operation made by items 2, 3, 4 at the initial stage, except that you do not need the full recovery of singlesymbol, but enough to restore one of its bits. Next, the comparison circuit sequences 52 (which represents the EXCLUSIVE OR element) compares the restored bits and a valid Central bit delayed by the shift register 5. A logical unit is present at the output of the element And 53, means the fact of detection of additive errors. Converter locators in synchronity 51 can be implemented in ROM (capacity 2m1-bit words, i.e., bits).

If the weight of at least one significant locator (to determine this fact serves as a chain of elements of two schemas comparison codes 54, 55 and element And 56) strongly decreased (as determined by the threshold of the THRESHOLD, it means that the channel resulting in a high level of additive errors. The last circumstance in this case makes it impossible to correctly measure idaco error information (signals ADDERR and SYNCERR) and the output of the block decision errors given the signal-to-noise (NOISE), which should be used by the device information registration error in the further processing of the stream of the channel state.

The circuit consisting of the counter 63, the multiplier into two 64, the adder 65, the comparison circuit codes 66 and element And 67, is designed to block the registration of additive errors for some time upon detection of a timing type insert bits, as in this case additive error due to the last. The counter 63 is reset in the absence of synchronization errors, and detection starts counting upwards up until the center of synchronization errors is within the left window (which is determined by the ratio of the weights significant relative locators), and then downward, when the center of a timing moves in the right window. Note that the synchronization error begins to register with the moment when its center is located in the center of the left window, and until the moment when the center will be located in the center of the right window. In fact indicated by the chain elements the following condition is checked:

CNT+L/2 > WINSIZE/2

or

2CNT+L > WINSIZE,

where CNT is the current state of the counter L is the size of the synchronization errors.by blocking the registration of additive errors (bits until the insert is fully moved in the right window).

The counter 63 is a counter with block zero, i.e. the current value of the counter does not change when the counter reaches zero when a countdown (from highest value to lowest value). A multiplier of two is not actually functional element is implemented as a simple transposition of conductors in the bus.

The set of flow States of the channel (Fig.5) on the basis of information received from the unit of decision-making errors 11 (signals SYNCERR, ADDERR, INS/DEL, and DL), assembles consecutive error-free channel States and sequences of errors in the packet, and allocates time to check synchronization errors and additive errors with the simultaneous appearance of signals ADDERR and SYNCERR (it uses the clock signal CLK3). D-flip-flop 68 is designed to determine the end of the same thread of the channel state (error-free state, or additive errors). For this purpose, the EXCLUSIVE OR element 69 is compared to the previous channel status (state of the D-flip-flop) and the current (current value signal ADDERR). When it detects the specified event occurs, the boot code units in the counter 73 by filing a logical unit to the input of the load sets of additive errors. Therefore, the dimension of the counter and tires at the output of the counter 73 (P) is determined by the greatest length of the interval the same conditions (2p). The operation of the processing unit thread States channel 12 explains the table shown in Fig. 11, which shows performed by unit steps and outputted to the output signals depending on the signals at the input and the current state of the D-flip-flop 68. In the first three columns of the table shows all possible combinations of input signals at the input AE, SE (ADDERR and SYNCERR respectively) and the state of the D-flip-flop (f/L). If C/L=0, it means that at the moment is counted by counter 73 error-free States of the channel, otherwise the equality C/L=1 means that the count of additive errors. C/L' - D-flip-flop, in which the transition in the next cycle. In the last column of the table contains the part of the flow state signals SYNCERR (SE) and ADDERR (AE) in earlier times, corresponding to each of these situations (in bold are the current state of the signals SYNCERR and ADDERR).

Notes to the table.

Control signals:

With the clock input of the counter 73,

L - input load of the counter 73,

W - signal recording WRITE the function synchronization errors,

Per. L - registration package additive error,

Per. With - check error-free interval.

In Fig. 12 shows timing diagrams of the clock signals of the device parameters measurement errors in the channel. One clock CLK corresponds to the time of receiving one bit of the test sequence in the device. The clock signal CLK2 is required to work finding significant relative locator 8. The control unit 35 transmits one clock cycle of the clock signal CLK2 is due to the fact that the Converter singlesymbol in locators 2 requires some time and, therefore, the data at the output will not appear at the beginning of the bar (because it is assumed that the Converter singlesymbol in the locators will be implemented in ROM). The set of flow States of the channel 12 starts to operate in parallel with the block finding significant relative locator 8 twentieth tact. This is possible because the data on the yield of the latter is ready for use at the end of the eighteenth tact. This saves two stroke work (CLK2) the whole device. The clock signal CLK3 is required to explode at the time of registration additive errors and synchronization errors. Clock with ibqah, which should record information about errors on the leading edge of the WRITE signal.

In Fig. 13-16 examples of device parameters measurement errors in the cases of four different configurations of errors. As a test use M-sequence obtained using a linear shift register with feedback shown in Fig.6A (m=5). Subsequent bits of the M-sequence are located on the figures to the left relative to the previous bits.

Abbreviations used in the tables (in order).

N is the number of the quantum,

SS - current singlesymbol (the output of the shift register 1),

L - current locator (Converter output singlesymbol in locators 2),

CNT - the current value of the counter 4,

R - the current value of the relative locator (output vicites 4),

ST - Central-bit output of the shift register 5),

LL - essential relative the locator to the left of the window (the output of block finding significant relative locator RLOC),

LN - weight substantial relative locator to the left of the window (the output of block finding significant relative locator NUM),

RL - significant relative the locator to the right for OA of the right window (the output of block finding significant relative locator 10),

SC - the current value of the offset counter 49 (shifted counter),

DO - the current value to direct the output of the selector 62 code of zero (DL= 0),

IJ is the current value of the J-input of the JK-flip-flop 58,

JK - the current value of the direct output of the JK-flip-flop 58,

LC - the current value of the counter 63,

EN - the current value of the output element AND-NOT 67 (permission signal reception additive errors),

AE - the presence of additive errors (the output of the comparison circuit sequences 52),

AE - the current value of the output element And 53 (signal additive errors)

SE - the current exit value of the element 59 (signal synchronization errors),

DL - the current value at the output of the multiplexer 61 (the size of the synchronization errors),

ID - the current value at the output of the comparison circuit codes 60 (type synchronization errors),

DC - current state of the D-flip-flop (interval type),

L - the current value of the input load of the counter 73,

IC is the current value of the counter 73 (size interval),

W - the current value of the signal record WRITE output devices

T - the current value of the error type (ERRTYPE) output device (in decimal form),

S - current value of the size of the error (ERRSIZE) on the output device.

Note: the signal is then received from the channel data stream meets the additive package errors and single additive error. As can be seen from table 24 step is the first issue of the WRITE signal for external device information registration error is logged empty interval without errors of length 24. Next, on the 29th quantum registers package additive errors (ERRTYPE=1) of size 5 bits. 30 quantum registers empty interval (ERRTYPE=0) size 1 bit, and finally, the next step is the registration packet additive error of length 1 bit (ERRTYPE= 1), which is fully consistent picture of the errors present in the analyzed stream.

In Fig. 14 shows the situation when received from the channel stream error occurred synchronization type drop size of 3 bits. As can be seen from table 39 quantum registers empty error-free interval of length 39 prior to the loss, and later in the same quantum error may be logged in the synchronization type drop (ERRTYPE=2), a length of 3 bits.

In Fig.15 shows the situation, when taken out of the channel bit stream occurred inserting the value of 4 bits. 29 step is to register this synchronization errors (ERRTYPE=3), and an empty error-free interval (ERRTYPE=0) length 29 preceding it.

In Fig.16 shows the situation when the analyzed bit poto is a situation of ambiguity in the localization of synchronization errors. And therefore, besides the loss of the value of 3 bits, recorded at 37 tact (ERRTYPE=2) and two additive error occurs check one extra additive errors.

The proposed device consists of a simple on its functional purpose, elements and can therefore be easily implemented on commercially available chips and radioelements. To reduce the size of the device it is advisable to implement the device to the FPGA or specialized ENCORE.

The proposed device is compared with the prototype has the advantage that a more accurate determination of the location of the inserts and deposition of bits in the data stream, and a more accurate restoration of the flow of additive errors that accompany the failure of synchronization. In the proposed device does not have a hard limit on the maximum size of the detected synchronization errors. The device allows real-time to obtain information about the error, refer to compact and convenient for further processing.

Sources of information

1. Patent 4158193 USA. IPC G 08 C 025/00; H 04 L 017/00. Data transmission test set with synchronization detector. /D Antonio Renato A. - declared 06.06.77; 803987; publ. 12.06.79.

2. PA is to, Calif - declared 13.10.93; 136075; publ. 21.02.95.

3. Patent 5727018 USA. IPC H 04 001/69; N 04 003/46. Process for obtaining a signal indicating a synchronization error between a pseudo-random signal sequence from a transmitter and a reference pseudo-random signal sequence from a receiver. /Andreas Wolf, Arweiler Hans-Wemer - declared 28.11.95 553447; publ. 10.03.98.

4. Patent 5282211 USA. IPC G 06 F 11/00. Slip detection during bit-error-rate measurement. /Robert M. Manlick, Matthew L. Fitchtenbaum - declared 15.10.91 776850; publ. 25.01.94.

5. McEliece, R. J. Finite fields for computer scientists and engineers. Borton, Kluwer Academic Publishers, 1987.

6. Lidl R. , Niederreiter, Finite fields: 2 T. Per. from English. - M.: Mir, 1988.

The unit of measurement errors in the channel containing the first and second shift registers, the comparison circuit sequence, and the input of the first shift register is an input device for the analyzed bit sequence, the first output of the first shift register connected to the input of the second shift register, the output of the second shift register with the first input of the comparison circuit sequences, characterized in that the device entered Converter singlesymbol in the locators, the first myCitadel, the first counter, the buffer relative locators, the first comparison circuit codes, block finding significant relative locator, buffer susistence errors block flow formation of the channel state, and the inputs of the Converter singlesymbol in locators connected to the second outputs of the first shift register, the first inputs of the first myCitadel - outputs Converter singlesymbol in the locators, the second inputs of the first myCitadel - the outputs of the first counter, the outputs of the first myCitadel - with the inputs of the buffer relative locators, with the first inputs of the first circuit comparing the codes with the first inlet of finding significant relative to the locator, the outputs of the buffer relative locators - with the second inputs of the first circuit comparing the codes with the second inlet of finding significant relative locator, the first output of the comparison circuit codes with the third inlet of finding significant relative to the locator, the first output unit finding significant relative locator - with inputs buffer substantial relative locators and with the first unit of decision errors, the second output unit finding significant relative locator - with inputs buffer weights significant relative locators with the second inlet of decision errors, the outputs of the buffer significant from the public relative locators - with the fourth input unit decision errors, the first output unit decision errors from the first input unit of flow formation of the channel state, the second output unit decision errors from the second input unit of flow formation of the channel state, the third output unit decision errors - with the third inlet flow formation of the channel state, the fourth output unit decision errors - with the fourth input unit of flow formation of the channel state, the fifth output unit of decision errors is the output of "Refusal measurement devices, the first output block flow formation of the channel state output Strobe recording devices, the second outputs of the block forming stream of the channel state outputs "error Type" device, the third output block flow formation of the channel state outputs "Size error" device, and the block finding significant relative locator contains the first multiplexer, the first - eleventh bus shapers, first - sixth buffer registers, the first selector code of zero, random access memory, the first element And the device initializemenu significant relative locator, the second inputs of the first multiplexer is the second inputs of block finding significant relative to the locator, the enable input of the control unit is the third unit finding significant relative to the locator, the control input of the first multiplexer is connected to the first output control unit, the outputs of the first multiplexer with inputs data of the first and second tire shapers, control input of the first bus driver connected with the second output control device, the control input of the second bus driver is connected to the third output control unit outputs the first bus driver - bus address outputs of the second bus driver - bus data the first address input of random access memory with the address bus, the second address input of random access memory with a third input of the first element And the fourth output control device and the third output device initialization, the third address input of random access memory to the second input of the first element And the fifth output control device and the fourth device output device initialization control input th the disorder management, the input sample RAM - with the twenty fourth output control unit that outputs data random access memory device with a data bus, the inputs of the first selector code of zero - address bus, the output of the first selector zero code with the fourth input of the first element And the data inputs of the first buffer register from the data bus, the first control input of the first buffer register - with the eighth output control device, the second control input of the first buffer register with the ninth output control device, the outputs of the first buffer register with the data inputs of the third and fourth tire shapers, the control input of the third bus driver - tenth the output control unit outputs the third bus driver - bus address control input of the fourth bus driver - eleventh output control unit outputs the fourth bus driver - bus data inputs data of the second buffer register from the data bus, the first control input of the second buffer register with the twelfth output control device, the second control input of the second buffer register from the thirteenth to the output device the Board, the outputs of the second buffer register with the data inputs of the fifth and sixth bus shapers, the control input of the fifth bus driver - from the fifteenth to the output control unit outputs the fifth bus driver - bus address control input of the sixth bus driver - from the sixteenth to the output control unit outputs the sixth bus driver - bus data inputs data of the third buffer register from the data bus, the control input of the third buffer register from the seventeenth access control devices, the outputs of the third buffer register with the data inputs of the seventh and eighth tire shapers, the control input of the seventh bus driver from the eighteenth access control devices, the outputs of the seventh bus driver - bus address control input of the eighth bus driver - nineteenth output control unit that outputs an eighth bus driver - bus data inputs data to the fourth buffer register from the data bus, the first control input of the fourth buffer register - twentieth of the output control device, the second control input of the fourth buffer register with the twenty first out ustroiteli, the control input of the ninth bus driver - the twenty-second output control unit that outputs the ninth bus driver - bus address control input of the tenth bus driver - with the twenty-third output control unit outputs the tenth bus driver - bus data inputs data of the fifth buffer register from the data bus, the control input of the fifth buffer register with the output of the first element And the outputs of the fifth buffer register with input data of the eleventh bus driver and are the first outputs of block finding significant relative to the locator, the outputs of the eleventh bus driver connected to the address bus, the control input of the eleventh bus driver - with the control input of the sixth buffer register and the seventh output control device, the input data of the sixth buffer register from the data bus, the outputs of the sixth buffer register are second outputs of block finding significant relative to the locator, the first input device initialization and clock control unit connected to the bus of the second clock signal, second input device initialization - bus code size E address bus, the second outputs from the data bus, and the device initialization contains the second counter, the second to fourth multiplexers, the second selector code of zero, the second comparison circuit codes, twelfth to fourteenth bus shapers, and the clock input of the second counter is the first input device initialization, the second inputs of the second multiplexer is connected to the first inputs of the second differential amplifier codes and are the second inputs of the device initialization, the first inputs of the second multiplexer and the second input of the third multiplexer is connected to the bus code of zero, the first inputs of the third multiplexer with bus unit code the first outputs of the second counter with the inputs of the second selector code of zero, with the second inputs of the second differential amplifier codes, with the third and fourth inputs of the fourth multiplexer and the input data of the fourteenth bus driver, the second outputs of the second counter with the control input of the fourth multiplexer and the data inputs of the thirteenth bus driver, the output of the second selector zero code with the control input of the second multiplexer, the second output of the comparison circuit codes with the control input of the third multiplexer,and with the second input of the fourth multiplexer, the outputs of the fourth multiplexer with inputs data of the twelfth bus driver, the control input of the twelfth bus driver with control inputs of the thirteenth and fourteenth tire shapers and the third input device initialization, the outputs of the twelfth bus driver are the second output device initialization, the outputs of the thirteenth bus driver - the third and fourth outputs of the device initialization, the outputs of the fourteenth bus driver, the first output device initialization, and the unit of decision-making errors contains the second and third myCitadel, the first and second adders, the third - seventh of the comparison circuit codes, fifth and sixth multiplexers, the third and fourth counters, Converter locators in synchronity, the comparison circuit sequence, the second to fourth elements And the first inverter, JK flip-flop, a third selector code of zero, the multiplier is two, the element AND-NOT, and the second inputs of the second vicites connected with the first inputs of the third myCitadel, with the second input of the sixth multiplexer and the first input of the block adoption of resea codes and are the second inputs of the unit of decision-making errors, the first inputs of the second myCitadel - with the second inputs of the third myCitadel, with the first inputs of the sixth multiplexer and are the third input unit decision errors, the second inputs of the fourth circuit comparing the codes with the first inputs of the fifth circuit comparing codes and are the fourth input unit decision errors, the fourth output of the comparison circuit codes with the first Manager of the entrance of the fourth counter, with the control input of the sixth multiplexer, with the J-input J trigger and with a third input of the fourth element And the outputs of the sixth multiplexer with the first inputs of the first adder, the outputs of the third counter with the second inputs of the first adder, the outputs of the first adder - inverter locators in synchronity, the inverter output locators in synchronity with the second input of the comparison circuit sequences, the output of the comparison circuit of sequences to the first input of the third element And the second inputs of the fifth circuit comparing codes and the first input of the sixth differential amplifier codes - bus code threshold, the output of the fifth differential amplifier codes with the first input of the second element And the sixth output of the comparison circuit codes with the second input of the second element And the second output is amenta And the output of the third element And is the fourth output unit decision errors, the output of the first inverter - fifth output unit decision errors, the outputs of the second vicites connected to the first input of the fifth multiplexer and the first input of the third differential amplifier codes, the outputs of the third myCitadel - with the second input of the fifth multiplexer and the second inputs of the third differential amplifier codes, the third output of the comparison circuit codes with the control input of the fifth multiplexer, a second input element AND IS NOT and is the second output unit decision-making errors, the outputs of the fifth multiplexer with inputs of the third selector code of zero, with the second inputs of the second adder and are the third outputs of the unit of decision errors, the inverted output of the third selector code of zero to the fourth input of the fourth element And direct the output of the third selector code of zero with K input of the JK-flip-flop and the second managing input of the fourth counter, the clock input of the JK-flip-flop and the fourth counter connected to the first bus clock signal, the inverted output of the JK-flip-flop to the second input of the fourth element, And the output of the fourth element And the two and a multiplier of two, the outputs of the multiplier on the two first inputs of the second adder, the outputs of the second adder with a first input of the seventh circuit comparing the codes, the second inputs of the seventh circuit comparing codes - bus code window size, the seventh output of the comparison circuit codes with the first input element AND the output element AND to the third input of the third element And, moreover, the set of flow States of the channel includes a D-flip-flop, the EXCLUSIVE OR element, fifth and sixth elements And the first and second elements OR the second inverter, the fifth counter, seventh and eighth multiplexer, and the D-input of D-flip-flop is connected to the second input of the EXCLUSIVE OR element and is the fourth input unit of flow formation of the channel state, the clock input of D-flip-flop is connected to a second input of the fifth element And with the input of the second inverter, a clock input of the fifth counter, and bus of the third clock signal, the output of D-flip-flop - with the first input of the EXCLUSIVE OR element and to the first input of the seventh multiplexer, the output of the EXCLUSIVE OR element with the first inputs of the fifth element and the second element OR the output of the fifth element And the first input of the first element OR the second input of the first element OR the second input of the second element OR and I'm the MD of the sixth element, And the first input of the sixth element And the fourth bus clock signal, the output of the sixth element, And is the first output of the processing unit thread of the channel state, the output of the second element OR is connected to the input load of the fifth counter, the data inputs of the fifth counter - bus single code, the outputs of the fifth counter - with the first input of the eighth multiplexer, the second input of the seventh multiplexer is a second input unit of flow formation of the channel state, the second input of the eighth multiplexer are the third inputs of the processing unit thread of the channel state, the output of the second inverter is connected to control inputs of the seventh and eighth multiplexers, the outputs of the seventh multiplexer and the second inverter are second outputs forming unit flow of the channel state, the outputs of the eighth multiplexer - third outputs of the block forming stream of the channel state.

 

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