A method of manufacturing a field-effect transistor with periodically alloyed channel

 

(57) Abstract:

Use: for the manufacture of field-effect transistors with the structure of a metal-oxide-semiconductor. The inventive method of manufacturing a field-effect transistor with periodically alloyed channel is that prior to forming the gate field-effect transistor for increasing the steepness of N times and increase the operating frequency is 2N silicon n-channel field-effect transistor choose the wavelength of the wave-like periodic nanostructures in the N2/2 times less than the channel length of the formed transistor. Formed in the channel region of a transistor wavelike nanostructure formed by the bombardment of the silicon surface by a stream of nitrogen ions, setting the period of the structure of the ion energy and angle of the bombing. The direction of flow of nitrogen ions set along the channel field-effect transistor. The nanostructure may form on the surface of monocrystalline silicon, and a surface layer of amorphous silicon. Modify the nanostructure to increase its amplitude and use it as a mask for carrying out ion implantation and formation of the periodically doped regions in the channel region of transiti. The technical result of the invention is the formation of a field-effect transistor with periodically alloyed channel militarychannel way, based on the process of self formation of nanostructures. 6 C.p. f-crystals, 27 ill.

The invention relates to methods of manufacturing field-effect transistors with the structure of a metal-oxide-semiconductor - MOSFETs. More precisely, the invention relates to a method of manufacturing MOS transistors having improved performance characteristics.

It is known that this device is a basic element of very large scale integrated circuits (VLSI) and is located in the surface region of a semiconductor two highly conductive (low resistance) region - drain and source-separated relatively high resistance gap channel, the electrical conductivity of which is controlled by varying the voltage at located over the channel field electrode - gate, electrically separated by an oxide layer (U.S. Patent 6078082 Field-Effect Transistor Having a Multi-Part Channel, 20.06.2000) [1].

It is known that the performance of the device and its maximum operating frequency is proportional to the mobility of the charge carriers in the channel and operating voltage and inversely proportional and supplementary ed. - M.: Mir, 1984, 456 S., Chapter 8) [2].

It is known that the limit of the length of the channels of the transistors in order to increase their performance is determined by the resolution of lithography methods. Currently, advanced technology, using advanced lithographic processes, provide the channel length of the transistors of the order of 0.1 μm. Thus, the performance of field-effect transistors including a device, the device which is disclosed in [1], limited by the capabilities of the lithography methods.

The idea of the way to increase the performance of field-effect transistors by increasing the mobility of charge carriers in the channel described in the article (C. A. Gergel, Century, Makarov. "About the increase in performance field-effect transistors due to the profiling of the channel" - reports of the Academy of Sciences, 2000, vol 375, 5, S. 609-610) [3] , where proposed in order to overcome the negative impact of electroresistive carriers in the transistor channel on its functional characteristics to form a transistor channel in the form of alternating nanometer regions with high and low conductivity extended across the flow field in the channel. The electric field in the channel of this transistor will oscillate in a measure of attitudes held by the physical parameter, the length of the heating (cooling) media, which is the product of time and energy relaxation to the drift velocity, will also oscillate. With proper selection of the ratios of the concentrations of carriers and the characteristic dimension of nanoplasma constituting the channel conditions, when the electrons is not too much "heat", drifting in high resistance areas, and almost completely surrender purchased thermal energy (cooled) in the low-resistance regions. Thus over the entire length of the channel nanoblasts doping on the average remains relatively low electron temperature, and hence the high, close to the low field values of the electron mobility.

However, the idea of forming a channel doped with nanoblasts according to [3] is not disclosed in sufficient detail for implementation. It is noted only that the specified formation can be realized by means of the formation of nanostructures.

In [1] proposed a transistor, the channel of which is composed of two parts (low impedance and high impedance), extended across the flow of charge carriers to overcome the effects of heating of the charge carriers.

Periodicity mobility of charge carriers in the channel due to the even more less heat.

Analyze the possibility of implementing formulated in the paper [3] the idea of bullet drift with respect to silicon MOS transistors and modern features silicon technology. Focusing on the effect at room temperature T = Tabout= OO TO and measuring the temperature in Volts proportional to its value in Kelvin, with Tabout= 0,026, use the simplest known model of dependence of kinetic coefficients from the electronic temperature

=0(T0/T)1/2,e=0(T/T0)1/2, (1)

where the mobility of charge carriers0= (T0) = 1,5103cm/Bc and the time of energy relaxation0= (T0) = 510-13c. Formula (1) given in the article (Kalfa A. A. Electronic technician. Ser. 1, 1985, 11, S. 383) [4].

Formula (1) are well-known theoretical model of electron scattering by acoustic phonons, and on the other hand, their direct use gives the familiar formula almost exactly describing the effect of saturation drift velocity vDin long samples

< / BR>
where E is the electric field in the transistor channel.

In this traditional situation, the electronic temperature the ones in the electric field and their "cool" due to the "impact" of excess thermal energy in the lattice due to the emission of the appropriate number of phonons.

We are interested in sverkhkorotkogo overshoot-mode electronic drift by the formula (2) Joul warmth educed goes on dynamic heating of the electrons, and thermoreectance negligible. The average electron temperature

< / BR>
where V is the voltage applied to the channel between drain and source). Formula (3) was derived in the article (Gergel C. A., Makarov Century BC, Timofeev, M. C., Fedorov, Y. C. "Ultra-kvazigidrodinamicheskoe electron transport in submicron field TIR and heteroresistance") [5]. Comparing dzhoulevo heating and thermoelasticity, the authors of the present invention has been important inequality between the normal condition and overshoot-mode electronic drift

,

which implies that modern MOS transistor with a typical sub-micron channel in 0.25 μm when the tension drain 1 is already in terms of overshoot mode. The authors of the present invention evaluated the average electron velocity in the channel field-effect transistor

< / BR>
For a transistor with L=0.25 μm at V=1 B vDalmost three times higher than the rate of saturation of the vS.

Using the above formula (5), the authors present invention evaluated the win, which is obtained by partitioning Cano V substitute the V/N, and instead of L - L/(N) where the geometric factor = /Lh2-3, is equal to the ratio of the period of doping to the size of the high-resistance region Lh. The result is that the velocity of the carriers, and hence the steepness of the device with the partitioned channel at least at times surpass the speed and steepness of the conventional transistor with the same total channel length. The corresponding absolute values in order to surpass traditional values (108cm/s 1 Cm/mm).

Even more time will increase the cutoff frequency fTcharacterizing the performance of the device.

Can be summarized advantages of the proposed transistor with partitioned channel. Namely, the electrical properties of the transistor with the partitioned channel length L is equivalent to the properties of the transistor of conventional design with distance from the drain to the source in times less.

The known method of forming a silicon wavelike nanostructures (U.S. Patent 6274007 Methods of formation of a silicon nanostructure, a silicon quantum wire array, and devices based thereon 14.08.2001) [6]. This nanostructure can be used as a mask for implantation and, accordingly, to create a channel with periodically alloy nanoplate. About is the fact that MOS VLSI technology and is suitable for periodic doping of the channel of the transistor, also not disclosed in [6].

Methods [3] and [6] in the aggregate, indicate a method of forming a periodically doped channel field-effect transistor with high mobility of charge carriers in the channel, but the stated characteristics are not sufficient to implement the invention.

The technical result of the present invention consists in forming a field-effect transistor with periodically alloyed channel militarychannel way, based on the process of self formation of nanostructures.

This is achieved using silicon periodic nanostructure as a mask for ion implantation when forming the channel of the FET.

The present invention is in the following set of features.

Prior to forming the gate field-effect transistor for increasing the steepness of N times and increase the operating frequency is 2N silicon n-channel MOS transistor choose the wavelength of the wave-like periodic nanostructures in the N2/2 times less than the channel length of the formed transistor (at = 2).

Spray the surface of the silicon ion flux of nitrogen molecules in vacuum prior to the formation of a periodic wave NAS the charge in the channel field-effect transistor formed with a choice of energy nitrogen ions, the angle of flow of nitrogen ions with respect to the silicon surface temperature of silicon, the depth of formation of nanostructures and the height of the nanostructures on the basis of the values selected wavelength nanostructures.

Perform selective removal of amorphous silicon to the saturation amplitude of the periodic relief nanostructures.

Implanted dopant ions into the silicon using nanostructure with the saturation amplitude of the periodic relief as a mask for implantation.

Carry out the removal of nanostructures reverse (explosive) method.

Forming a layer of gate silicon oxide, the gate, source and drain of the FET, produce low-temperature deposition of silicon oxide and planarization its surface, forming metal contacts to the gate, source and drain and Passepartout surface.

It is preferable for the formation of nanostructures to be used as the silicon layer of amorphous silicon deposited on the surface of the crystalline silicon.

It is preferable to remove the amorphous silicon selectively with respect to silicon nitride and crystalline silicon.

Preferably the layer of amorphous Crimescope silicon.

It is preferable to remove the amorphous silicon selectively with respect to silicon nitride and silicon oxide.

It is preferable to carry out reactive ion etching of amorphous silicon.

It is preferable to select the thickness of the layer of amorphous silicon greater amount of depth of formation of nanostructures, the height of the nanostructures and the depth of penetration of the nitrogen ions in the amorphous silicon.

Preferably the layer of silicon oxide previously formed on the surface of crystalline silicon, to use as a layer of gate silicon oxide.

The invention is illustrated by drawings, where:

in Fig. 1 shows a cross-section of the region forming the n-channel MOS transistor;

in Fig. 2 is a cross-section of the region forming the n-channel MOS transistor in the formation of nanostructures;

in Fig.3 is a cross section of the nanostructure;

in Fig. 4 is a cross section of the nanostructure with a partially remote layer of amorphous silicon;

in Fig. 5 is a cross section of the nanostructure with a partially remote layer of amorphous silicon and the process of ion implantation;

in Fig.6 is a cross-section of the implanted regions after the gate oxide of silicon;

in Fig. 8 is a cross section of a periodically doped region forming the n-channel MOS transistor;

in Fig.9 is a cross section of n-channel MOS transistor with a periodically alloyed channel;

in Fig. 10 is a cross-section of the region forming the n-channel MOS transistor with a layer of amorphous hydrogenated silicon;

in Fig. 11 is a cross-section of the region forming the n-channel MOS transistor in the formation of nanostructures in the layer of amorphous hydrogenated silicon;

in Fig.12 is a cross section of the nanostructure in the layer of amorphous hydrogenated silicon;

in Fig.13 is a cross section of the nanostructure with a partially remote layer of amorphous hydrogenated silicon;

in Fig.14 is a cross section of the nanostructure with a partially remote layer of amorphous hydrogenated silicon and the process of ion implantation;

in Fig.15 is a cross-section of the implanted regions after the process of removal of the nanostructure;

in Fig.16 is a cross-section of the implanted regions with a gate oxide of silicon;

in Fig. 17 is a cross-section of the region forming the n-channel MOS transistor layer and the cross-section region forming the n-channel MOS transistor in the formation of nanostructures in the layer of amorphous hydrogenated silicon;

in Fig.19 is a cross section of the nanostructure in the layer of amorphous hydrogenated silicon;

in Fig.20 is a cross section of the nanostructure with a partially remote layer of amorphous hydrogenated silicon;

in Fig.21 is a cross section of the nanostructure with a partially remote layer of amorphous hydrogenated silicon and the process of ion implantation;

in Fig.22 is a cross section of the nanostructure with a partially remote layer of amorphous hydrogenated silicon using reactive ion etching;

in Fig.23 is a cross section of the nanostructure with a partially remote layer of amorphous hydrogenated silicon and the process of ion implantation;

in Fig. 24 is a cross section of n-channel MOS transistor with a periodically legirovannym channel;

in Fig.25 is a perspective image of the periodically doped channel regions and source and drain n-channel MOS transistor;

in Fig. 26 is a cross-section of the region forming the n-channel MOS transistor with a layer of hydrogenated amorphous silicon deposited on a thin layer of silicon oxide and the field insulating silicon oxide;

in Fig. 27 is a cross-section of the region forming the n-channel MOS-transacti silicon wafers.

The invention is illustrated by the following example.

Example. The near-surface region of a silicon wafer of p-type conductivity 1 area of silicon oxide 2 and the mask of silicon nitride 3, shown in Fig.1, is irradiated to the flow of ions of molecular nitrogen 4. The result is a wavelike nanostructure 6 shown in Fig.2. Areas 2 and 3 partially sprayed stream 4 and into the area 2A and 3A. At this initial level of the silicon surface 5 is reduced due to the ion sputtering process, and on the side surface 2A is formed a thin layer of oxynitride 7.

Formed wavelike nanostructure shown in Fig.3 and consists of regions of silicon nitride layer 8 and the amorphous silicon 9 with inclusion of the nitrogen atoms and N-N pairs.

The crests of the waves nanostructures are perpendicular to the direction of flow of the ions. Therefore, the direction of flow of ions is chosen along the channel as shown in Fig.2. The vector of the flow of ions is located in the plane of the drawing in Fig. 2 and has no component perpendicular to the plane of the drawing.

After the process of forming wavelike nanostructures in the process of partial udaleneace amorphous silicon 9A are arranged on the surface of the crystalline silicon 1. The process of partial removal of the layer of amorphous silicon 9 may be implemented with a liquid etching nanostructures 6 to provide the Etchant amorphous silicon, selective with respect to crystalline silicon and silicon nitride.

Periodically repeating regions 8 and 9A are a mask for ion implantation, which is carried out according to Fig.5. The energy of the arsenic ions 10 are chosen so that ions completely delayed layers 8 and 9A. In the process of ion implantation are formed implanted region 11 in silicon 1.

Re-conduct the process liquid etching nanostructures to provide the Etchant amorphous silicon, selective with respect to crystalline silicon. In the reverse process (explosive) remove the nanostructures obtained with the structure shown in Fig.6.

Carry out the oxidation process of silicon, which is formed by the structure shown in Fig.7. The structure includes a thin gate silicon oxide 12 and the doped region 11A, obtained from regions 11 in the electrical activation of the implanted impurities. Electrical activation can be carried out through a known process, a rapid thermal horizontaly in Fig.7 specifies the length of the high resistance region Lh. Period doping equal to the period of the nanostructure .

After removal of the mask silicon nitride 3A (shown in Fig.2) the resulting structure shown in Fig.8. MOS-transistor with periodically alloyed channel shown in Fig. 9. He formed as a result of the operations of forming the gate polysilicon 13, followed by implantation of arsenic ions and the formation regions of the source 14 and drain 15.

MOS-transistor with periodically alloyed channel can be made in another way. The platform for the formation of the transistor, as shown in Fig.10, first, the precipitated layer of amorphous hydrogenated silicon (Si:H) 16, and then precipitated mask silicon nitride 3V.

Carry out the process of forming wavelike nanostructures, as shown in Fig. 11. The structure shown in Fig.10, by the flow of ions of molecular nitrogen 4. The result is a wavelike nanostructure 17, shown in Fig.11. Area 3B partially sprayed stream 4 and into the area 3C.

Nanostructure 17 in the enlarged view shown in Fig.12. It consists of regions of amorphous hydrogenated silicon nitride (Si3N4(H): 18, regions Si:H with inclusions of atoms of azo the layers 19 and 16A. The result is a periodic structure consisting of regions 18, regions Si3N4:H 19A and areas Si:H 16B. Partial removal of the layers 19 and 16A can be accomplished by liquid etching amorphous silicon provide the Etchant that is selective with respect to the nitride and crystalline silicon 1.

The process of ion implantation of arsenic is shown in Fig.14. The flow of ions of arsenic 10 is delayed by fields 18, 19A and 16B. The ion energy was chosen such that ions completely delayed layers 18, 19A and 16B. As a result of implantation are formed implanted region 20.

After the process of removal areas 16B structure that served as a mask for ion implantation of arsenic is removed reverse (explosive) method and remains the silicon surface with periodically implanted regions 20, as shown in Fig.15. Removing regions 16B can be accomplished by liquid etching amorphous silicon provide the Etchant that is selective with respect to the crystalline silicon 1.

Carry out the oxidation process of silicon, which is formed by the structure shown in Fig.16. The structure includes a thin gate silicon oxide 21 and the doped region 20A, obtained from obestatin as due to a known process, rapid thermal annealing, and due to thermal influence during the formation of oxide. The distance between the regions 20A horizontally in Fig.16 specifies the length of the high resistance region Lh. Period doping equal to the period of the nanostructure ..

After removal of the mask silicon nitride 3C (shown in Fig.11) to form a gate polysilicon 13A, followed by implantation of arsenic ions form a region of source 14A and the drain 15A and conduct electrical activation of the dopant in these areas. The result is a MOS transistor with a periodically doped regions in the channel 20D shown in Fig.24 and Fig.25.

Periodic doping of the channel of the transistor can be realized otherwise. It uses the structure shown in Fig.17. The difference of this structure from that shown in Fig.10 is that the layer of Si:H 16 lies on a thin thermally grown layer of silicon oxide 21 A. Layer 21 And the pre-form prior to the deposition of a layer of Si:H 16. After forming the layer 16 form the mask silicon nitride 3D.

Carry out the process of forming wavelike nanostructures, as shown in Fig.18. The structure shown in Fig. 17, by the flow of ions of molecular nitrogen 4. The result is Volnoe and 3E.

Nanostructure 17 in the enlarged view shown in Fig.19. It consists of areas of Si3N4:H 18, regions Si:H with inclusion of the nitrogen atoms and N-N pairs 19 and a layer of Si:H 16A. The difference Fig.19 from Fig.12 is that the layer of Si:H 16A rests on a layer of silicon oxide 21 A.

In Fig. 20 shows nanostructure 17 after partial removal of the layers 19 and 16A. The result is a periodic structure consisting of regions 18, regions Si3N4:H 19S and areas Si:H 16C. Partial removal of the layers 19 and 16A can be accomplished by liquid etching amorphous silicon provide the Etchant that is selective with respect to silicon nitride and silicon oxide.

The process followed by ion implantation of arsenic is shown in Fig.21. The flow of ions of arsenic retained areas 18, 19S and 16C. The ion energy was chosen such that ions completely delayed layers 18, 19S, 16C and 21 A. as a result of implantation are formed implanted region 20B.

The process of partial removal of the layer of amorphous silicon 19 and 16A shown in Fig.19, can be performed using reactive ion etching. When this layer of silicon oxide 21A may act as a stop layer. Such chemical etching silicon silicon VLSI.

In the reactive ion etching nanostructures 17 is obtained with the structure shown in Fig. 22. It consists of areas 18, regions Si3N4:H 19D and areas Si:H 16D. The difference of this structure from that shown in Fig. 20 is that the areas and 16D 19D side walls vertical.

The process followed by ion implantation of arsenic is shown in Fig. 23. The flow of ions of arsenic 10V delayed areas 18, 19D and 16D. The ion energy was chosen such that ions completely delayed layers 18, 19S, 16D and 21A. As a result of implantation are formed implanted region 20C. The distance between the regions 20C horizontally in Fig. 23 specifies the length of the high resistance region Lh. Period doping equal to the period of the nanostructure .

A mask consisting of layers 18, 19D and 16D or 18, 19S and 16C, remove the reverse (explosive) method.

After removal of the mask silicon nitride 3E (shown in Fig.18) to form a gate polysilicon 13A, followed by implantation of arsenic ions form a region of source 14A and the drain 15A and conduct electrical activation of the dopant in these areas. The result is a MOS transistor with a periodically doped regions in the channel 20D shown in Fig.24 and Fig.25.

Carry out the process of forming wavelike nanostructures, as shown in Fig.27. The structure shown in Fig.26, by the flow of ions of molecular nitrogen 4. The result is a wavelike nanostructure 17, shown in Fig.18. In this case, wavelike nanostructure is formed on the surface regions 2. On the surface of the "bird's beak" regions 2 is formed on the one side region 19 Si:H with inclusion of the nitrogen atoms and N-N pairs and the other side region 18 Si3N4H, as shown in Fig.27.

After consistently surgery partial removal of the layers 19 and 16A and ion implantation, as shown in Fig.22 and in Fig.23 receive periodically implanted region, including on the surface of the insulating silicon oxide 2. After removal of the mask for ion implantation reverse (explosive) method, if necessary, implanted layers from the surface of the insulating silicon oxide can be removed by the known methods of etching silicon oxide, while the implanted areas on the surface of Kremnev-transistor with periodically alloyed channel, it is shown in Fig.24 and Fig.25.

1. A method of manufacturing a field-effect transistor with periodically alloyed channel, namely, that prior to forming the gate field-effect transistor for increasing the steepness of N times and increase the operating frequency is 2N silicon n-channel field-effect transistor choose the wavelength of the wave-like periodic nanostructures in the N2/2 times less than the channel length of the formed transistor, spray silicon surface by the flow of ions of nitrogen molecules in vacuum prior to the formation of periodic wavelike nanostructures when the projection direction of the flow of ions to the silicon surface, parallel to the flow of charge carriers in the channel field-effect transistor formed with a choice of energy nitrogen ions, the angle of flow of nitrogen ions with respect to the silicon surface temperature of silicon, the depth of formation of nanostructures and the height of the nanostructures on the basis of the values selected wavelength nanostructures, carry out selective extraction of amorphous silicon to the saturation amplitude of the periodic relief nanostructures, implanted dopant ions into the silicon, using nanostructure with the saturation amplitude of the periodic relief in kachestve silicon, the gate, source and drain of the FET, produce low-temperature deposition of silicon oxide and planarization its surface, forming metal contacts to the gate, source and drain and Passepartout surface.

2. The method according to p. 1, characterized in that for forming the nanostructure is used as a silicon layer of amorphous silicon deposited on the surface of the crystalline silicon.

3. The method according to p. 2, wherein removing the amorphous silicon selectively with respect to silicon nitride and crystalline silicon.

4. The method according to p. 1, characterized in that for forming the nanostructure is used as a silicon layer of amorphous silicon, which is precipitated on the surface of the layer of silicon oxide formed on the surface of the crystalline silicon.

5. The method according to p. 4, wherein removing the amorphous silicon selectively with respect to silicon nitride and silicon oxide.

6. The method according to p. 4, characterized in that the removal of amorphous silicon carry out reactive ion etching.

7. The method according to p. 2, characterized in that choose the thickness of the layer of amorphous silicon greater amount of depth of formation of nanostruct

 

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6 cl, 4 dwg

FIELD: electronic equipment.

SUBSTANCE: invention is intended to create discrete devices and microwave integrated circuits with the help of field-effect transistors. Method of making field-effect transistor, including creation of drain and source contacts on the contact layer of semiconductor structure and extraction of active region, metal or metal and dielectric mask is applied directly on the surface of contact layer, formation of submicron slot in the mask for further etching operations of contact layer etching and application of T-shaped gate metal through resist mask, after application of the first metal mask lithography for opening windows is carried out when one of the edges coincides with location of Schottky gates in manufactured transistor, and after opening windows the second metal or dielectric mask is applied on the whole surface, remove resist and by lithography create window in resist surrounding slits formed between two metals or between metal and dielectric, perform selective etching of contact layer, after which spray metal films to form T-shaped gates. As a result, edges of T-shaped gate heads on both sides resting on metal or metal and dielectric masks. Then, via selective etching the mask is removed from under the "wings" of T-shaped gate and from the surface of transistor active area. After that, the surface of transistor active area, containing drain, source contacts and Schottky gates, is coated with a passivating layer of dielectric so that under "wings" of T-shaped gate cavities are formed filled with vacuum or gas medium.

EFFECT: technical result is production of gated with length less than 100 nm, as well as reduced thickness of the metal mask and elimination of intermediate layer of dielectric placed between the active region surface and mask.

1 cl, 1 dwg

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