A persistent storage device and method of control

 

(57) Abstract:

The invention relates to a permanent storage device and method of its control. The technical result is the ability to read data from a permanent storage device with low energy consumption. The device has plenty of memory cells, tyres words bit bus, the bus source, switch gears. The method describes the ability to control a permanent storage device. 2 C. and 17 C.p. f-crystals, 4 Il.

The invention relates to a permanent storage device and method of its control. Permanent storage device (ROM, EPROM, BOTTOM, EEPROM and the like) and methods for their control are well known.

A practical example of the construction and management of conventional permanent storage device explained below with reference to figures 3 and 4 for example, a persistent storage device (ROM).

Described ROM has lots of memory cells, the contents of which with proper management can be read via the bus words bit bus and bus source. In the case of the ROM as opposed to some other forms of persistent storage devices (e.g., Ÿ information ("0" or "1"). In one case we are talking about the transistor, and in another case, the transistor without replacement of missing, and associated otherwise with transistor signal bus (bus words bit bus and bus source) lead into the void.

Containing the transistor memory cell of the ROM shown schematically in Figure 3.

It contains, as mentioned, transistor, here in the form of a field-effect transistor T1, the site of the source of which is connected to the bus source SL, plot runoff from the bit-line BL, and the part of the shutter which is connected to the bus of words WL.

Reading the stored data from the ROM operates in the following way:

First means signal for pre-charging charge bit bus to a defined potential, for example to about +4 C. Bit and its external circuit frame is made so that it, as soon as the transistor is turned off or non-existent, retains the potential also after termination of the connection to the source of the signal for pre-charging.

If the transistor in this state, a request for reading or, respectively, selectrow, i.e. via the bus words to the area of the transistor applied voltage, for example +5 V, and the bus is the source of the connection is as charge carriers flowing through the transistor to ground. The potential of the bit bus due to this reduced to 0 C.

On the other hand, in the case of memory cells that do not contain the transistor, due to the lack of a transistor obtained by pre-charging of bit bus potential does not flow, and basically saved.

Depending on the memory contents of the corresponding memory cell, the potentials of bit bus enable you to define the contents of memory.

Although other types of permanent storage devices are partially a completely different design of memory cells, they contain a lot in common with the memory cells of the ROM, as they are connected to the same signal bus (bus words bit bus, the bus source) and a signal bus for reading load in essentially the same signals, and changing signals have comparable consequences.

Bus words may, as in the case of EEPROM, consist of several signal tyre (tire selection, the management bus), however, due to this, there is no fundamental changes described a General principle (see, for example, patent EP 0637035).

Shown in Figure 3 of the memory cell when predusmatrivayut certain number Einaudi devices.

The design is similar to the field of memory cells presented in Figure 4.

Figure 4 is a schematic diagram of the field memory cells of conventional permanent storage device.

Shows the field of memory cells contains many marked "O" of the individual storage cells according to Figure 3, which are arranged in many rows (m) and the number of columns (n).

n elements of each row of the field of memory cells respectively connected with the common bus of words WL0, WL1...WLm(if necessary, consisting of tire selection and control bus). m elements of each column of the memory cells connected respectively to total the bit-line BL0BL1... BLn. Bus source SL of all memory cells of the field of memory cells combined into a common bus of the source.

The connection of memory cells shown in Figure 4 field of memory cells, made in the form of a matrix, allows you to display separately from permanent storage contents of the storage cells by a corresponding control tyres words, bit tires and tire source with relatively low management costs.

The basis of the present invention, therefore, is the task of further developing a persistent storage device according to the restrictive part of paragraph 1 of the claims or, respectively, the method of control according to the restrictive part of paragraph 17 of the claims, to the data reading can be performed with reduced power consumption and faster.

This task according to the invention is solved by the features indicated in the characterizing part of paragraph 1 of the claims or, respectively, in the characterizing part of paragraph 17 of the claims.

According to this provided that the respondents through a separate bus words (WL) of the memory cells are divided into many groups, each of which is assigned to a separate common line source (SL) (item 1 of the claims) or, respectively, produce a group reading of memory cells which are scanned via a separate bus words (WL) (item 17 claims).

These measures allow to poll for read only memory cells, the contents of which should be derived from a permanent storage device. More specifically, what is happening when reading data from memory cells is edelenyi area inside of a number of fields of memory cells, what is still due to provide only a single shared bus, the source for all memory cells of the field of memory cells, it was impossible to carry out (discharge pre-charged bit buses could only happen in rows and fields of memory cells).

If bus source, really want to read, that is also true of the output of the group of memory cells, spare capacity, suitable for reading (for example, 0 V), and the line of source, is not necessarily to be read, that is not the output of the group of memory cells, do not suitable for reading potential (for example, a high voltage of about +5 V), the discharge pre-charged bit bus (bit buses) can only occur within the output group of memory cells, in contrast to the other groups.

If this

1) is not included in the conductive state of one or more provided if necessary transistor or transistors of the storage cells and

2) there is no discharge pre-charged bit buses.

This obviously leads to significant energy savings relatively few memory cells, a few obtained this data can, with the exception of the normally required multiplexer, to be submitted directly provided on the appropriate amount of the output data bus or field bus and thence be derived from a permanent storage device without additional complicated method of sampling, and similar operations.

Disclaimer multiplexer leads to further energy savings and significantly earlier conclusion to be reading data from a persistent storage device.

However, the data is read from the persistent storage device is much faster and at significantly reduced energy consumption.

In addition, a persistent storage device can have a simpler construction, to have smaller sizes, because the possible exception of the very expensive multiplexers.

We offer storage device contains a number of memory cells, configured to read when running through a bus words bit bus and bus source (WL, BL, SL), and scanned via a single bus words (WL) of the memory cells are divided Nay different groups of memory cells through the switch (T5) are connected to a common output buses (BUS), each of the provided output buses (BUS) is connected via a separate device enable (T5), respectively, with one of the bit-line (BL) on one group of memory cells, and a switch controlled by the potential of the bit bus.

The invention is explained below using an exemplary embodiment with reference to the figures.

Figure 1 - schematic representation of an example of execution of field construction of memory cells claimed ROM;

Figure 2 is an example implementation of a device for direct connection read from electrovanne of memory cells of the ROM data to the output data bus;

Figure 3 - schematic representation of the construction of memory cells of the ROM, and

Figure 4 - schematic representation of the construction of a conventional field memory cells of the ROM.

Shown in Figure 1 box of memory cells comprises, as shown in Figure 4 normal field of memory cells from the set of storage cells, indicated by the symbol "O" (for example, memory cells of the type shown in Figure 3), which are located in the set of (m) rows and (n) columns.

n elements of each row of the field of memory cells connected to a common bus of words WL0BL1... BLn.

In contrast are shown in Figure 4 conventional field memory cells tires source SL of memory cells, however, no longer United in common to all memory cells of the field memory cells bus source.

Moreover, there are any number of individual tire source SL (Figure 1, for example, shows SL0SL1and SL0), each of which is assigned to a particular group of memory cells in the row field of memory cells. In other words, memory cells of a number of fields of memory cells are divided into many groups, each of which has a separate, but common to memory cells corresponding group bus source.

As a rule, in practice the group of memory cells has as many storage cells as bits (for example, 1 byte) contains the word data and calculation on each row of the field memory cells, a plurality of such identical groups of memory cells located next to each other (in a row).

However, in General each series of fields of memory cells may be optionally any number of groups (at least two), which can have the same value or the options or accordingly, memory cells which can be arbitrarily distributed across several fields of memory cells.

One of the following from here other than the usual case features then consists, for example, that memory cells each x-data words within a number of fields of memory cells combined into a group (so you can read, for example, only the signs of the displayed text, but not the associated display attributes).

In the view of Figure 1 shows three groups of memory cells. First (according to Figure 1, left) the group consists of three adjacent each other memory cells, tire source which objedini in a separate common bus source SL0. Adjoining the second (according to the Figure 1 average group consists of four adjacent each other memory cells, tire source which objedini in a separate common bus source SL1. The third (according to Figure 1, right), the group consists of two adjacent to each other memory cells, tire source which objedini in a separate common bus source SL2.

The division into groups is shown in the example of execution is the same for all series field saponin Inaudi cells are connected to each other. Similar design but also limits required for the implementation of the field memory cells expenses, but of course is not mandatory. Moreover, each row of the field of memory cells can be separated completely independently of the other rows and tires the source of the respective groups can be installed and operated completely independently from each other.

Describes how to perform field memory cells allows (when using the corresponding control device) group treatment (choice, elektrownie) addressable via a separate bus words of memory cells, and the group, as mentioned above, in the extreme case, may consist of a single storage cell.

It appears extremely beneficial, in particular when reading data, as in the conventional fields of memory cells read data from memory cells, as mentioned above, (as opposed to output data from a permanent storage device) was only possible (under certain circumstances, very large) units of rows of the field of memory cells.

Selective reading of one particular group within the same number of field storage of ACE who I am to her description).

Unlike conventional permanent storage devices (through the corresponding(s) bus(bus) source), however, required to read the voltage (in this example run 0), served only to those terminals of the source, which really infer or, respectively, are required for output. To not output or, respectively, is not required to output the storage elements of the corresponding row of the field of memory cells for reading, more precisely to discharge the pre-charged bit bus through one or more transistors, served the wrong voltage source (in this example, the high voltage of the order of +5).

Because, on the one hand, the transistors truly representing the interest of memory cells included in the passage and, consequently, on the other hand, are discharged only bit bus, which is interesting for output, energy consumption is reduced when the data capture part of what is required when reading data from a normal persistent storage device.

The fact that bit bus no interest of memory cells when reading the person's data is not razrezajut the drain of memory cells (as opposed to data not electrovanne storage cells) could take a field bus, through which the data directly, i.e. without intermediate inclusions are usually provided multiplexers, can be derived from a permanent storage device.

This is extremely advantageous effect is illustrated below in Figure 2.

Figure 2 clearly explains how, depending on the status bit bus memory cells selected for silage preparation on the main output bus can be fed a signal.

In the following explanation, for reasons of clarity proceed from the following assumptions.

Assume that the n elements of each of m are shown in Figure 1 of the series fields of memory cells divided into i having the same amount of groups, and each group can contain such a number of memory cells that corresponds to the number of bits stored data words. Data words in this example are bytes, so that each of the first group consists of j = 8 memory cells.

Of the eight memory cells m i groups, respectively, the first memory cell assigned to the first main bus, the second memory cell is the second main bus, the third memory cell of the third main bus, the fourth zapominaniya cell sixth, the trunk, the seventh memory cell - seventh the trunk, and the eighth memory cell assigned to the eighth the trunk.

Connecting the x-th memory cells of any group to x-th main bus is shown in Figure 2 for ROM; other permanent storage devices requires under certain circumstances in accordance with various conditions of minor changes.

According to the Figure 2 device has an n-MOS field-effect transistors T1 and T2, the p-MOS transistors T3, T4 and T5 and the inverters I1, I2 and I3, shown by United way bus words W1, the bit-line BL, bus source SL field bus BUS bus pre-charge PC and voltage VDDfor example on the order of 5 C.

The transistor T1 is shown in Figure 3-transistor memory cells of the ROM.

At the beginning of each scan cycle to the bus pre-charge briefly put low voltage, for example 0 C. This means that, on the one hand, field bus BUS via included then the pass transistor T2 catch up to the potential supply (inverter I1 may for this purpose is shown to be connected through cootes then included on the pass transistor T3 rises up to the potential VDD.

Connected to the trunk BUS inverters 12 and 13 form a link retention, which supports the potential field bus when returning the transistor T2 in the closed state on the potential of mass (such as the level of retention provided for each of the main buses). The inverter I1 is relatively weak transistor T5.

Bit BL also retains its potential for the return of the transistor T2 is in the closed state, as applied to the output gate of the transistor T4, the potential of the bus (mass) toggles through the transistor T4, the voltage VDDon bit bus.

The described process is the same for all memory cells of the field memory.

First will be described the inclusion remembered this from memory cells selected for silage preparation (bus words WL is suitable for reading the voltage, for example +5 V bus source SL also suitable for reading the voltage, for example 0 or, respectively, the mass) on the bus BUS.

The transistor T1 corresponds shown in Figure 3 conventional transistor memory cells of the ROM.

When submitting to him (elektrownie) these signals through smasse), since the transistor T1 is strong relative to the transistor T4.

Due to a change in potential of the bit bus transistor T5 becomes conductive and includes UDDto the bus. Due to the inclusion of the pass transistor T5, the transistor T4 is locked so that the bit BL through the transistor T1 is securely on the ground.

If the selection contains the transistor T1 of the storage cell main BUS is thus at a high potential, that has been installed at the expense of the transistor.

If selectonemenu with no transistor memory cells of the ROM is the state that existed after the application of the voltage pre-charge via the bus pre-charge PC, as without the transistor T1 is held at the expense of the transistor T4 is actively high potential of the bit BL cannot be discharged. That is, in the case of Elektrownia with no transistor T1 memory cells of the ROM main BUS remains at the potential of the masses.

On the main BUS, as already mentioned, there are many other memory cells of the other groups (one storage cell to another group).

To ensure the appropriate assignment of work shown in the Figure 2 schematic neselektivnye memory cells should not have any influence on the bus BUS, because otherwise you can change the data obtained through electrovanne storage cells.

That shown in Figure 2 the device, despite its simple design, it really is automatically occurs explained below.

The memory cell is not selectonemenu if the tire source has a high level and/or if the bus words has a low level. One of these conditions (partly both conditions) performed on all memory cells that lie or the number of fields of memory cells selected by bus words, but not in the group selected by bus source, or not in the selected row of the field of memory cells.

If containing the transistor T1 memory cell serves available if neselektivnye potentials tires and tire source, the transistor remains or closed (with low capacity bus words) or bit bus is connected through a transistor with a high capacity bus source.

In both cases, the bit can not be discharged, and orazem, excludes active influence on the bus.

Containing the transistor T1 memory cell in neselektivno condition thus behaves neutrally relative to assigned field bus.

The same is true also for not containing the transistor T1 memory cells because of the absence of the transistor T1 bit BL, regardless of the state of Elektrownia memory cells may not actively be discharged so that also here the transistor T5 remains closed and thus an active impact on the bus are eliminated.

Does not contain transistor T1 memory cell in neselektivno condition thus behaves neutrally relative to assigned field bus.

Although each main bus connected so many memory cells as the number of groups exist within the field of memory cells, the only electrovanne group and only she can give to the bus signals corresponding to the saved data.

From those usually multiplexers through which in each cycle of reading among the read data corresponding to the full ragatale can be waived.

Although in the described device and the described method should provide for the decoder, which is based on the read from memory address determines to be selectonemenu group, that is, determines the group on the bus which has its source in contrast to all the other tires of the source must be made suitable for reading the potential, however, such decoders can be very simple and small so that the costs which have to be considered due to this are negligible.

The previous description, in particular the description of Figure 2, pertained primarily to the fact that all groups of memory cells have the same magnitude. However, this is not mandatory. Moreover, groups of memory cells can be different from each other and to have any value. The number of memory cells maximum group of memory cells must then, however, correspond to the maximum number available, as described, trunk lines.

Worthy of mention and can be advantageously used to the effect that a field bus, if it is simultaneously connected to multiple electrovanne storage of ACE the Vienna OR or EXCLUSIVE OR.

The design corresponding to the invention, the permanent storage device and corresponding to the invention the method for its control have been explained above on the example of the ROM. The same actions and advantages of the described measures can be however achieved also when they provide other kinds of permanent storage devices (EPROM, EPROM, EEPROM, and so on).

1. A persistent storage device, containing a number of memory cells, configured to read when running through a bus words bit bus and bus source (WL, BL, SL), and scanned via a single bus words (WL) of the memory cells are divided into many groups, each of which is set in accordance with a separate common bus source (SL) and buses bit different groups of memory cells through the switch (T5) are connected to a common output busses (BUS) for data output from the storage device, characterized in that that provided the switch is controlled by the potential of the bit bus (BL).

2. A persistent storage device under item 1, characterized in that at least part of the memory cells includes a transistor (T1).

3. A persistent storage device is Noah bus (BL) and bus source (SL).

4. A persistent storage device according to any one of paragraphs. 1-3, characterized in that the memory cells of each row are connected to corresponding bus words (WL).

5. A persistent storage device according to any one of paragraphs. 1-4, characterized in that the memory cells of each column are connected with the corresponding the bit-line (BL).

6. A persistent storage device according to any one of paragraphs. 1-5, characterized in that the memory cells of each column are connected to the corresponding bus source (SL).

7. A persistent storage device according to any one of paragraphs. 1-6, characterized in that the memory cell is designed for memorizing one bit of data.

8. A persistent storage device according to any one of paragraphs. 1-7, characterized in that the group of memory cells designed for memorizing data words consisting of any number of data bits.

9. A persistent storage device on p. 8, characterized in that the data word is a data byte.

10. A persistent storage device according to any one of paragraphs. 1-9, characterized in that the cells of the group of memory cells are distributed randomly along the row.

11. A persistent storage device lure> 12. A persistent storage device according to any one of paragraphs. 1-11, characterized in that each of the provided output data bus (BUS) is connected via a separate device enable (T5), respectively, with one of the bit-line (BL) on one group of memory cells.

13. A persistent storage device according to p. 12, characterized in that each memory cell is connected to only one output data bus (BUS).

14. A persistent storage device under item 12 or 13, characterized in that the output data bus (BUS) is provided in the number corresponding to the number of cells in the largest group of memory cells.

15. A persistent storage device according to any one of paragraphs. 12-14, characterized in that the switch (T5) is designed so that United with one output data bus (BUS) memory cells only electrovanne cell may include the signal on the output data bus.

16. A persistent storage device according to p. 15, characterized in that the switch (T5) is designed in such a way that they include the signal on the corresponding output data bus (BUS), if the assigned bit changes its potential in a given direction is a separate bus, layer (WL) of the memory cells are divided into many groups and conduct group read these memory cells, wherein each group of memory cells assigned a separate common bus source (SL), and bus source (SL) to be read groups of cells applied voltage, allowing you to change the potential of the corresponding bit buses (BL), and to the tires of the source (SL) does not need to be read groups of cells applied voltage, not allowing you to change the potential of the corresponding bit buses (BL).

18. The method according to p. 17, wherein the read only memory cells, the contents of which are then removed from device.

19. The method according to p. 17 or 18, characterized in that the read only data of one group of memory cells.

 

Same patents:

The invention relates to a semiconductor memory device with multiple memory cells and is used mainly in the cards with an embedded microchip, such as card ID, credit cards, payment cards, etc

The invention relates to programmable permanent storage devices such as electrically erasable ROM (EEPROM)

The invention relates to non-volatile memory and method of programming

The invention relates to a method of programming a memory device and enables the simultaneous control of threshold levels when performing a two-level or multi-level programming

FIELD: semiconductor memory devices.

SUBSTANCE: device has a lot of memory elements, each of which contains input and output areas, isolating film, channel area, shutter electrode, area for storing electric charges, device also contains large number of periphery circuits, containing reading amplifier, register for storing recorded data of memory elements, register, which preserves the flag, indicating end of record during its check, and circuit, which after recording operation compares value, read from memory cell, to value, fixed by flag at the end of record, and overwrites value indicated by the flag.

EFFECT: higher reliability of operation.

5 cl, 71 dwg

FIELD: information technology.

SUBSTANCE: flash memory element for electrically programmable read-only memory is meant for data storage when power is off. On a semiconductor base with a source and drain between the latter, there is a tunnelling layer, an auxiliary tunnelling layer, a memory layer, blocking layer and a switch. The auxiliary tunnelling and blocking layers are made from material with high dielectric permeability, from 5 to 2000, exceeding the dielectric permeability of the material of the tunnelling layer made from SiO2.

EFFECT: as a result there is reduction of voltage (4 V) and time (10-7 s) for recording/erasing information and increase in data storage time (up to 12 years).

7 cl, 1 dwg

FIELD: information technology.

SUBSTANCE: memory cell for high-speed controlled gate-region potential EEPROM, the electric circuit of the memory cell having an n(p)-MOS transistor, first and second diodes, a capacitor, a number, an address and a bit line, wherein the cathode (anode) of the first diode is connected to the number line and the source of the n(p)-MOS transistor, its anode is connected to the anode of the second diode, the region under the gate of the n(p)-MOS transistor and the first lead of the capacitor, the second lead of which is connected to the gate of the n(p)-MOS transistor and the address line, and the cathode of the second diode is connected to the drain region of the n(p)-MOS transistor and the bit line, wherein the electric circuit of the memory cell additionally includes a p(n)-field-effect transistor, a common and control line, wherein its source is connected to the region under the gate of a MOS transistor, the gate is connected to the control line and the drain is connected to the common line.

EFFECT: higher reliability of memory cell work.

2 cl, 6 dwg

FIELD: electronics.

SUBSTANCE: invention relates to microelectronics. Restoring memory element has a substrate with a conducting electrode located on its working surface. Said conducting electrode has an active layer of dielectric. Second conducting electrode is located on the active layer. Conducting electrode located on the working surface and/or the second conducting electrode are made from metal. Dielectric layer is metal oxide from which conducting electrode located on the working surface and/or the second conducting electrode is made.

EFFECT: technical result is lower voltage of reprogramming, as well as reduction of consumed power for reprogramming.

14 cl, 1 dwg

Up!