Device for frame synchronization

 

(57) Abstract:

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal. The device frame synchronization contains the decoder of synchronously, generating equipment, consisting of a counter position, the loop counter, pulse generator and decoder zero state of the counter, environment device and the first inverter, as well as the newly introduced random access memory device, a distributor, a trigger, second, third and fourth inverters, the first and second elements And the element OR, register memory, and to set the device. Device for frame synchronization can reduce the search time synchronism with distributed synchronously while reducing hardware tools, which is the technical result achieved when implementing the present invention. 2 Il.

The device relates to techniques for digital communication, namely, devices for frame synchronization in digital transmission systems with a temporary seal.

A device for frame synchronization [1], containing case crater pulses, two elements OR three elements is NOT critical device, two elements And the element OR NOT, United in a certain way.

This device provides increased robustness of digital transmission systems with a temporary seal when the distortion of the interference signals about the presence or absence of staffing.

However, this device has the following disadvantages. Realization of the sequential search synchronization increases the time of entering into synchronism, and the application of the input register, especially when synchronizing digital transmission with distributed by synchronously, increases the hardware costs, since the bit width of the register is equal to the length in positions of the transmission cycle, the length of which can reach several thousand items.

The closest to the technical nature of the claimed invention is selected as a prototype device for frame synchronization [2] , containing the detector clock cycle, the analyzer coincidence signal, the block selection clock frequency pulse distributor, trigger, register, members, And and OR, United in a certain way.

The disadvantages of the prototype are uvelichenie input register, especially when you synchronize digital transmission with distributed by synchronously, increases the hardware costs, since the bit width of the register is equal to the length in positions of the transmission cycle, the length of which can reach several thousand items.

An object of the invention is to reduce the search time of synchronism when distributed synchronously with a simultaneous reduction of the hardware.

This task is solved in that the device for frame synchronization, containing the decoder, generating equipment (TH), consisting of an item counter, cycle counter, pulse generator, decoder zero state of the counter (NCC), environment unit (FU), the first inverter and the clock signal received from input device for frame synchronization (CA ) through the first inverter to the clock input of counter positions and the loop counter, the address outputs 1,...,m and 1,...,n TH is connected to the address outputs of the device for the CA, the output FU is connected with the corresponding output device for the CA, according to the invention introduced random access memory (RAM), a distributor, a trigger, second, third and fourth inverters, the first and second elements of the targeted outputs 1,...,m, the selection input of RAM is connected to the earth bus, the output of the third inverter is connected to the enable input of the RAM read and with the control input of RH, the enable input write RAM is connected to the output of the second inverter, the input/output 1,2,...,N-1,N RAM connected to inputs/outputs 1,2,..., N-1,N RZ, the clock input of the distributor is connected to the output of the first inverter and the input of the distributor is connected to the output of the pulse generator, the first output of the distributor is connected to a clock input of the trigger information input trigger is connected to the power bus, the second output of the distributor is connected to the input of the AG, the third output of the distributor is connected with the input set to zero trigger and clock input FU, the fourth output of the distributor is connected to the input of the second inverter, the output of the decoder NSS TH is connected to the second input of the first element And the outputs 0p, 1p, 2p,...,(N-1)p, Np, RP is connected to the corresponding inputs of the decoder, the output of the decoder is connected to the third input of the first element And the second input of the second element And the first input of the first element And is connected to the output of the fourth inverter, the output of the first element And connected with the second input member OR the output of the second element And connected to the first input element OR the input of usten to the input of the fourth inverter and the first input of the second element, And outputs 1,...,k ZU connected to inputs 1,...,k FU, outputs 1,...,R ZU connected to inputs 1,...,R FU, an information input device for the CA is connected with the information input RZ.

The known device for frame synchronization digital streams distributed by synchronously usually searching (sequential) detection method of the first synchronously. Implementation of optimal (parallel) method requires a large hardware cost, because it uses the input register, bit width which is determined by the number of positions corresponding digital stream and can reach several thousand.

The main time when searching for synchronization is determined by the time of the first synchronously.

The maximum time that the first distributed synchronously sequential search is

< / BR>
The maximum time that the first distributed synchronously with a parallel search is

< / BR>
where T is the detection time of the first synchronously, s;

N - cut between adjacent elements synchronously, in positions;

n is the length of synchronously, in positions;

F - speed digital peredatochnoi synchronously with a parallel search in N/2 times smaller than the sequential.

The proposed device for frame synchronization enables distributed parallel search of synchronously without increasing hardware costs.

The novelty of technical solutions is the use in the inventive device of new circuit elements: random access memory RAM, the distributor, the register storing the AG specifying device memory trigger, second, third and fourth inverters, the first and second elements And, OR.

Thus, the invention meets the criterion of "novelty."

Analysis of the known technical solutions in the study and related fields allows to conclude that the introduced functional units known. However, their introduction into the device for frame synchronization with the above links gives this unit the new properties. Introduced functional units interact in such a way that allows parallel distributed search of synchronously without increasing hardware costs and, therefore, reduce the time of entering into synchronism while reducing equipment.

Thus, izopet the match technique.

The invention can be used in digital transmission systems with a temporary seal.

Thus, the invention meets the criterion of "industrial applicability".

In Fig.1 shows a block electrical diagram of an apparatus for frame synchronization, Fig. 2 shows a block electrical diagram of the environment of the device.

Device for frame synchronization (Fig.1) contains the decoder 1, the generating equipment (TH) 2, consisting of item counter 3, count 4, the pulse generator 5, the decoder of the zero state of the counter (NCC) 6, environment unit (FU) 7, the first inverter 8, a random access memory (RAM) 9, the dispenser 10, the trigger 11, the second 12 and third 13 and fourth 14 inverters, the first 15 and second 16 elements And the element OR 17, the register memory (RA) 18 specifying the device (memory) 19, moreover, the clock signal received from input device for frame synchronization (CA) through the first inverter 8 to the clock inputs of the counter positions 3 and count 4 2, the address outputs 1,...,m and 1,...,n TH 2 are connected to the address outputs of the device for the CA, the output FU 7 is connected with the corresponding output device for the CA, the address inputs 1,...,m OZ the RA 13 is connected to the input of the read permission for the RAM 9 and the control input RZ 18, the enable input write RAM 9 is connected to the output of the second inverter 12, the inputs/outputs 1,2,...,N-1,N RAM 9 is connected with the inputs/outputs 1,2, ...,N-1,N P3 18, the clock input of the distributor 10 is connected to the output of the first inverter 8, and the entrance of the distributor 10 is connected to the output of the pulse generator 5 TH 2, the first output of the distributor 10 is connected to a clock input of the trigger 11, the information input trigger 11 is connected to the power bus, the second output of the distributor 10 is connected to the input of P3 18, the third output of the distributor 10 is connected with the input set to zero trigger 11 and a clock input FU 7, the fourth output of the distributor 10 is connected to the input of the second inverter 12, the output of the decoder NSS 6 TH 2 is connected with the second input of the first element And 15, the outputs 0p, 1p, 2p,...,(N-1)p, Np, P3 18 connected to respective inputs of the decoder 1, the output of the decoder 1 is connected to the third input of the first element And 15 and with a second input of the second element And 16, the first input of the first element And 15 is connected to the output of the fourth inverter 14, the output of the first element And 15 is connected with the second input of the OR element 17, the output of the second element And 16 connected to the first input of the OR element 17 and the input set to zero TH 2, the output of the OR element 17 is connected to the input of synchronously FU 7, the output of nulesu 19 are connected to inputs 1,...,k FU 7, outputs 1,...,R memory 19 is connected to the inputs 1, . . .,R FU 7, an information input device for the CA is connected with the information input P3 18.

Environment the device (Fig.2) contains the inverters 20, 21, 22, 23, elements I, 25, I and I, elements ILI and ILO, reversible counter 30, the trigger 31, the decoder of the zero state of the reversible counter 32, the decoder maximum state reversible counter 33, the elements match 34 and 35, and the input of synchronously (log SK) FU 7 is connected to the input of the inverter 20, the first input element 25 and sign up or count +/- reversible counter 30, a clock input (input RHS) FU 7 is connected with a clock input (entrance) of the trigger 31, the second input element I and a second input element 25, the inputs 1,...,k FU 7 connected to respective inputs of the element matches 34, the inputs 1, . . .,R FU 7 connected to respective inputs of the element matches 35, the output of inverter 20 is connected to the first input element I, the output of the inverter 21 is connected with the third input element I, the output of which is connected to the first input of the OR element 28, the output of inverter 22 is connected to the third input of the element 25, the output of which is connected with the second input element ILI, the output of which is connected with a clock input (entrance To) the reverse is Oceania reversible counter 32, decoder maximum state of the reversible counter 33 and elements match 34 and 35, the output of the decoder, the zero state of the reversible counter 32 is connected to the input of the inverter 21 and the zero output state (output DCO) FU 7, the output of the decoder, a maximum state of the reversible counter 33 is connected to the input of the inverter 22 and the second input of the OR element 29, the output of which is connected with the information input (D input) trigger 31, the output element of coincidence 34 is connected with the second input element I, the output of which is connected with the input set to the maximum condition (input SET) reversible counter 30, the output element of coincidence 35 is connected with the second input element I, the output of which is connected with the input set to zero R trigger 31 and the input set to zero RES reversible counter 30, the output of the trigger 31 is connected to the input of the inverter 23, the first input element I, the first input element ILI and exit FU 7, the output of the inverter 23 is connected to the first input element I.

Device for frame synchronization works as follows.

To clock signals from input (input T) devices for frame synchronization through the first inverter 8 to the clock inputs (inputs) counter pazistami dispersed synchronously digital stream, and the cycle counter 4 counts the number of cycles, the number of which is determined by the number of elements in synchronously. Outputs 1,...,m bits of the counter positions 3 2 enter the address inputs 1,...,m RAM 9. The work RAM 9 is allowed zero potential at its input selection CE connected to earth ground. If the enable input read TH RAM 9 signal Log. "1" and the enable input WE write signal Log. "0" is recorded information on 1,2...N-1,N inputs/outputs of the RAM 9 in the cells of the selected address. If the enable input WE write signal Log. "1" and the enable input of the read SECOND signal Log. "0" by reading data from the corresponding cells in the selected address of the RAM 9 at its 1,2...N-1,N inputs/outputs. Clock signals are also received at the clock input T of the dispenser 10, the other input of G which receives signals from the pulse generator 5 TH 2. The frequency of the pulse generator 5 are selected in such a way that during the period of the clock signal received at the clock input T of the dispenser 10, the latter formed distributed in time sequence signals PC1, RS, RS, RS. Information signals from the output of And device for the CA act on the information W To) trigger 11, the latter is set in one state, because the information input (D input) this trigger is connected to the power bus. The output signal from the trigger 11 through the third inverter 13 is supplied to the control input (input control) RH 18. While the outputs of gates RH 18 are transferred to the third state, blocking the passage through them of the signals from the triggers 0rur, 1p, 2p,..., (N-1 )p, Np. Also the signal from the output of the inverter 13 to the input of read permissions OE RAM 9, the latter carries out the reading of data stored in the corresponding address in the previous cycle. The signal received from the second exit (exit RC) dispenser 10 to the input RZ 18, trigger'or remember the current information signal from the information input (input) device for the CA, and triggers 1p, 2p,..., (N-1)p, Np, P3 18 is previously memorized in the RAM 9 and read the corresponding address signals on the inputs/outputs 1,2, . . . ,N-1,N RAM 9. The signal received from the third exit (exit RC) dispenser 10 on the input set to zero (log R) flip-flop 11, the latter is set in the zero state. This ends the enable signal is read at the input resolution read SECOND RAM 9, and permits the operation of the managed veins of the or and its inputs/outputs 1,2,...,N-1,N is supplied respectively to the inputs/outputs 1,2, . ..,N-1,N RAM 9. The signal received from the fourth exit (exit RC) dispenser 10 through the second inverter 12 to the input of the write-enable WE RAM 9, is the last record came to its inputs/outputs information. Thus, the work RAM 9 in cooperation with the work of P3 18 can be represented as the work of the M shift registers, where M equals the number of positions between the elements of the dispersed synchronously, and the bit width of each register is equal to the number N, where N is the length of synchronously, in the positions. In each address of the RAM 9 the stored value of the previous N-1 bits P3 18, and the current value stored in the trigger 0rur P3 18. With outputs P3 18 current information signal and the signals read from the RAM 9, proceed to the inputs of the decoder 1. Before the first positive response at the output of decoder 1 signal log. "1" output from the zero state DCO FU 7 received at the first input of the second element And 16, may be permitted the latter, and through the fourth inverter 14 are prohibited from working the first item And 15. The first signal of the positive feedback about deciphering synchronously received through the open second And gate 16 to the input set to zero (log R) item counter 3 and counter 4 cycles of RD 2, latter IC FU 7, increases the state of its reversible counter 30 by one. Then the signal Log. "0" at the output of the zero state DCO FU 7 the second And gate 16 is closed, and through the fourth inverter 14 is opened at the first input of the first element And 15. After that check the correctness of the decryption of synchronously is at the zero state of the counter positions 3 and count 4 2. Now at zero States of the counters 3 and 4 2 and the output signal of the decoder of the zero state of the counter NSS 6 TH 2 permitted on the second input of the first element And 15. When this signal is positive or negative response from the output of the decoder 1 via the first item 15 and item OR 17 is fed to the input of synchronously IC FU 7 and the signal from the third output RS dispenser 10 to the appropriate input FU 7, the latter changes its state.

Fairhouse the device operates as follows.

In the absence of input of synchronously IC FU 7 of the first signal positive response decode synchronously reversible counter 30 is in the zero state. When this signal with the output of the decoder, the zero state of the reversible counter 32 FU 7 through the inverter is its device 7 on the clock input To the reversible counter 30 and the latter is held in the zero state. When the input of synchronously IC FU 7 of the first signal positive response decode synchronously reversible counter 30 at its entrance up or count +/- is set in the positive mode account and a clock signal RC FU 7 coming through the open on the first and third input element And element 25 and 28 on the clock input To the reversible counter 30, the latter increases its state unit. After that, the signal Log. "0" of the decoder of the zero state of the reversible counter 32 through the inverter 21 is permitted when the signal of the negative feedback input of synchronously SK passes the clock signal from input RS through the open element And element 24 and 28 on the clock input To the reversible counter 30. Thus, when the positive signal response on input SK FU 7 reversible counter 30 increments its state by one, and when the negative signal response on input SK - reduces your status on the unit. When the difference in the number of signals of positive and negative feedback when deciphering synchronously reaches the specified criteria value is input in synchronism, the output signal from the element of coincidence 34 through the open element And 27 pic is combinatie IC FU 7 the next signal of the positive feedback signal from the clock input RS reversible counter 30 is set to the maximum condition, and the trigger 31 of the negative front of the clock input RS FU 7 is set in one state. Thus, the device for the CA enters the mode matching and retention, which is indicated by a signal having a synchronization f coming from the trigger output 31 output FU 7 and further to the output device for the CA. Single output signal from the trigger 31 through the inverter 23 is prohibited work item And 27 and permits the work item And 26. The signals of the selected criteria input in synchronism come with inputs 1,...,k FU 7 to the inputs 1,...,k element of coincidence 34. The signals of the selected criterion exit synchronism come with inputs 1,...,R FU 7 to the inputs 1,...,R element of coincidence 35.

When the difference in the number of signals of negative and positive responses when deciphering synchronously reaches the specified criteria value output from the synchronism, the output signal from the element of coincidence 35 through the open element And 26 is supplied to the input set to zero RES reversible counter 30 and the input set to zero R trigger 31, installing them in the initial state. The device again enters the search mode matching, as described above.

For the technical realization of the device for the CEC is of the type S (firm CYPRESS SEMICONDICTOR) and user programmable logical integrated circuit (PPLIS) imported type XC 3195(firm XILINX).

The present invention allows to reduce the search time synchronism with distributed synchronously with a simultaneous reduction of the hardware.

Sources of information

1. RF patent 2136111, CL H 04 L 7/08.

2. RF patent 2019046, CL H 04 L 7/08.

Device for frame synchronization, containing the decoder, generating equipment (TH), consisting of an item counter, cycle counter, pulse generator, decoder zero state of the counter (NCC), environment unit (FU), the first inverter and the clock signal received from input device for frame synchronization (CA) through the first inverter to the clock input of counter positions and the loop counter, the address outputs 1, . . . , m and 1, . . . n TH is connected to the address outputs of the device for the CA, the output FU is connected with the corresponding output device for the CA, characterized in that the input random access memory (RAM), a distributor, a trigger, second, third and fourth inverters, the first and second elements And the element OR register recall (RA) that specifies the device (memory), and the address inputs 1, . . . m RAM connected to the address outputs 1, . . . m , TH, input, select RAM is connected to the earth bus, closed the ISI RAM is connected to the output of the second inverter, inputs/outputs 1,2, . . . , N-1, N RAM connected to inputs/outputs 1,2, . . . , N-1, N RZ, the clock input of the distributor is connected to the output of the first inverter and the input of the distributor is connected to the output of the pulse generator, the first output of the distributor is connected to a clock input of the trigger information input trigger is connected to the power bus, the second output of the distributor is connected to the input of the AG, the third output of the distributor is connected with the input set to zero trigger and clock input FU, the fourth output of the distributor is connected to the input of the second invertigo, the output of the decoder NSS TH is connected to the second input of the first element And the outputs 0rur, 1p, 2p, . . . , (N-1)p, Np, RP is connected to the corresponding inputs of the decoder, the output of the decoder is connected to the third input of the first element And the second input of the second element And the first input of the first element And is connected to the output of the fourth inverter, the output of the first element And connected with the second input member OR the output of the second element And connected to the first input of the OR element and the input set to zero, the output element OR is connected to the input of synchronously FU, the output of the zero state FU is connected to the input of the fourth inverter and the first input of the second element, And outputs 1, . . . , the device for the CA is connected with the information input RZ.

 

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FIELD: radiophone groups servicing distant subscribers.

SUBSTANCE: proposed radiophone system has base station, plurality of distant subscriber stations, group of modems, each affording direct digital synthesizing of any frequency identifying frequency channel within serial time spaces, and cluster controller incorporating means for synchronizing modems with base station and used to submit any of modems to support communications between subscriber stations and base station during sequential time intervals.

EFFECT: enhanced quality of voice information.

12 cl, 11 dwg

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