The circuit for generating negative voltage

 

(57) Abstract:

The circuit for generating negative voltage to the first transistor (TX2), the first output of which is connected with an input / output (E), and the second output of which is connected to the output pin (A) circuit and the output of the gate through which the first capacitor (b2) is connected to the first output clock signal, the second transistor (TL2), the first output of which is connected to the output of gate TX2, the second terminal of which is connected with the second output TX2 and the output gate of which is connected to the first output TX2 and the second capacitor CR, the first output of which is connected with the second output TX2 and the second output of which is connected with the second output clock signal, and TX2, TU2 are MOS transistors, made in the technique of triple pocket. The first output of the third transistor (Tz2) is connected with the second output TX2, the second conclusion Tz2 connected with pocket/pockets (Kw) containing transistors TX2, TU2, Tz2, and the output of gate Tz2 is connected to the first output TX2. Effect: increased efficiency by reducing leakage currents. 3 S. and 3 C.p. f-crystals, 6 ill.

The invention relates to a circuit for generating negative voltage to the first transistor, the first output to the thief which is connected through the first capacitor to the first output clock signal, with the second transistor, the first output of which is connected to the output gate of the first transistor, the second terminal of which is connected with the second output of the first transistor and the output gate of which is connected to the first output of the first transistor and the second capacitor, the first output of which is connected with the second output of the first transistor and the second output of which is connected with the second output clock signal, and the transistors are MOS transistors, made at least one triple pocket (Triple Well).

This scheme is known from the patent DE 196 01 369 C1. There, the transistors are implemented as n-channel transistors in the p-pocket. P-pocket with his hand made in deep, isolating the n-pocket, which is located in the p-substrate.

In principle, the scheme can be implemented so also with the p-channel MOS transistors in the n-substrate.

Deep n-pocket connected, as well as the p-substrate, the housing potential. If now n-afford to put the more negative bias voltage than the negative voltage or the output flow, or on the output of the source of the first transistor, in the steady state of the circuit through the parasitic bipolar transistor is a CMOS n-MOS transistor, which serves as the emitter, the p-pocket, which forms the base, and the n-pocket, which forms the collector. If the potential pocket is more positive than the drain region of the n-MOSFET, the parasitic PDP-transistor will conduct and the negative impact on the efficiency of the generator charge pump.

The principle is known, acting as a generator charge pump circuit is based on the fact that the charges from the capacitor, which is connected to the output of the drain of the first transistor, "pumped up" to the capacitor, which is connected with its output source, due to the fact that alternately applied voltage to respectively as condenser conclusions. If each other include N such circuits, the input of the first circuit and the following output connected to the output of the capacitor connected to the output of the hull, it can theoretically be achieved output voltage |(N-1)U0| and U0is the voltage on the findings of a clock signal.

The charge process is a dynamic process in which the voltage at the terminals of the source and drain of the first transistor circuit are constantly changing, so regularly turns on the parasitic bipolar transistor.

Already for inclusion in the case of a known schema pocket will be at the proper voltage to the clock signal of higher potential than the output flow, and thereby to turn on the bipolar transistor, which leads to severe loss of efficiency, as the generator charge pump, on the one hand, does not reach theoretically maximum possible output voltage and, on the other hand, takes subject to the achievement of the output voltage is significantly slower.

The objective of the invention is therefore to specify a schema for generating negative voltages with higher efficiency.

This problem is solved by a scheme under paragraph 1 of the claims. A preferred form of execution specified in the dependent claims, from the poison, formed of several such schemes, there is a third transistor that connects the pocket with the output of the first source (charger) transistor only when the potential at the output of the source is more negative than the potential at the output drain of the first transistor. In this case, pocket capacitor, which is obtained by RP-barrier layer between the two pockets is charged to a potential source and supports pocket long enough on this potential, if the third transistor is again locked, since the potential of the output drain of the first transistor becomes more negative than the potential output of the source.

In a further form of execution of the invention provides a fourth transistor that connects the pocket with the output of the drain of the first transistor when the potential of the output flow is more negative than the potential of the output source of the first transistor. In this form of execution pocket capacitor thus always charged to a more negative potential so that the static state in which the pocket is more positive than the one of the conclusions of the first transistor may not occur, and thus the parasitic bipolarisation the location of the capacitor between the output of the drain of the first transistor and a pocket. This capacitor is charged during the phase of incorporation of the third capacitor, as well as pocket capacitor to the potential of the output source and included in the phase locking of the third transistor in series with pocket capacitor so that when the lower potential output drain voltage on the handheld condenser is shifted to negative values. The pocket is therefore more negative than it would have been possible due to the net charge through the output source of the first transistor.

Due to the inclusion of each other several relevant to the invention of schemes you can get a generator charge pump, which can generate voltage - 12 or even 20, as is required for programming and/or erasing non-volatile memory devices, in particular, fast EPROM (erasable programmable ROM) when the supply voltage of the chip, only 2.5 Century.

In such a generator charge pump odd scheme serves the first and second clock signals, and even schema serves the third and fourth clock signals that have the same characteristics as the first and second clock signals, however, shifted by half a period. In the preferred form gave the e, than 0.5, so that the second and fourth clock signals are superimposed on each other. Due to this, the first transistor is pre-charged, which leads to increased efficiency.

The invention is illustrated in further detail in the examples with the help of drawings on which is shown:

Fig. 1 is a detailed block diagram corresponding to the invention schema;

Fig. 2 - schematic representation of the implementation of this scheme in the p-substrate in the technique of triple pocket (Triple Well);

Fig. 3 - the first form of the generator charge pump;

Fig. 4 - the second form of execution of the generator charge pump;

Fig. 5 - the third form of execution of the generator charge pump;

Fig. 6 - temporal characteristics of the clock signals.

According Fig. 1 in the related invention to the scheme which can be viewed as a cascade of multi-stage generator charge pump for generating a negative voltage between the input output E and the output pin And the first n-MOS transistor TX2.

As is shown in Fig. 2, the first transistor TX2 is made in the p-pocket, which is, for its part, in a deep, isolating the n-pocket. This deep n-pocket made in TX2 through the first capacitor b2 is connected to the first output clock signal, to which may be applied to the first clock signal F1. Conclusion the source of the first transistor TX2 is connected to the first output of the second capacitor CR, the second terminal of which is connected with the second output clock signal, which can be applied to the second clock signal F2.

Input output S of the circuit can be connected to the output pin following a similar scheme as it is presented in detail in Fig. 3 and outlined in Fig. 1 by the second capacitor CP1 this subsequent schemes.

As is shown in Fig. 6, the second and fourth clock signals F2, F4 have the same temporal characteristic, but offset from each other by half of the duration of the period. Due to this alternating supply a positive voltage to the second and fourth conclusions the clock signal charges of the second capacitor CP1 next or previous schemes chain of circuits according to Fig. 3 "pumped" to the second capacitor CR following, shown in Fig. 1 circuit through the first transistor TX2. His conclusion shutter during the phase of the pump due to the first clock signal F1, the time response of which is also shown in Fig. 6, is pulled to a positive concerning Vivi F2 and F4 few overlap, so the first transistor pre-charged up until it does not turn on the first clock signal F1 to the conducting state.

By pumping charge to the second capacitor CR he is charging and after disconnection of the second clock signal F2 output or, respectively, associated with the output source of the first transistor TX2 becomes negative. Thus the output of the source would be more negative than the output gate of the first transistor TX2, which he would not have locked the door, and a second capacitor CR could again be discharged. So between the output speed and the output source of the first transistor TX2 enabled, the second transistor TL2, the output gate of which is connected with the output of the drain of the first transistor TX2. Due to this, the second transistor TU2 also the output gate of the first transistor TX2 is given to the potential output of the source of the first transistor TX2 so that he locked.

To prevent discharge of the second capacitor CR through the second transistor TL2 and the first output clock signal, provides a first capacitor b2.

According to the invention between the output of the source of the first transistor TX2 and output pocket Kw, in which the transistor TX2,x2.

As can be understood from Fig. 2, the second and third transistors TL2, Tz2 are also located in the region of the pocket in which the first transistor TX2. As outlined by the dashed lines, they can be performed also in their own pockets, and pockets the preferred way connected to each other by wires.

At the expense of the third transistor Tz2 pocket, which is shown in Fig. 1 node HP, is held at a negative potential so that the PN-junction between the p-pocket and the n-pocket included in the direction of locking and can no leakage no leakage current. At the expense of the third transistor Tz2 additionally charging the capacitor pocket pocket-lock Cw layer so that the p-pocket when the locking of the third transistor Tz2 is held at a negative potential.

In Fig. 2 also presents the parasitic PDP-transistor Tr, which is formed of n+the drain region of the first transistor TX2, p-pocket, and n-pocket. This parasitic transistor Tr shown in Fig. 1. You clearly to understand that this transistor Tr would become conductive and would lead to leakage currents, if the p-pocket would be more positive than the output of the drain of the first transistor TX2. This, however, effectively prevented due to sootla corresponding to such invention diagrams in order to generate not only a negative voltage, and compared with the supply voltage of a high negative voltage, which, for example, is required for programming and erasing quick EPROM.

In Fig. 3 one after the other included the number N of such schemes according to Fig. 1. The first transistors marked Txl-TxN. Other parts of the circuit is equipped with a numbers equivalent way. On the second capacitor CpN n-th circuit is not energized clock signal as it should appear high negative voltage. This generator charge pump, as represented in Fig. 3, which consists of N-stages pump, you can get the voltage of (N-l)U0if the input of the first stage pump connected to the housing and U0is the level of the clock signal. The clock signals F1...F4 are the temporal characteristics of that shown in Fig. 6. Clock signals F3 and F4 have the same temporal characteristics as the clock signals F1 and F2, but shifted by half of the duration of the period.

Odd cascades pump generator charge pump according to Fig. 3 serves the clock signal F3 and F4, and the even - numbered clock signals F1 and F2.

Fig. 4 shows the form of execution is placed between the drain of the first transistor TX1 should be...TxN and pockets. The findings of the gate of the fourth transistor Tzal...TzaN connected respectively with the terminals of the source of the first transistor Zxl...TxN. Third transistors are Tzbl...TzbN.

Fourth transistors Tzal...TzaN serve to also in the case when the findings of the drain of the first transistor Txl...TxN applied a lower potential than on their findings to the source, this is the lowest potential was switched to the pockets and the pockets thereby always been at the lowest of the two potentials.

Instead of the fourth transistor Tzal. . . TzaN in the preferred form of further development of the scheme according to Fig. 1 or, respectively, the generator charge pump according to Fig. 3 may be included third capacitor C3 between the terminals of the drain of the first transistor Txl. ..TxN and pockets Kw. This is shown in Fig. 5. The third capacitor C3 in conjunction with capacitors pocket-pocket Cw (Fig. 5 does not explicitly shown) lead to a further decline of the capacity of the pocket.

Presented on Fig. 3-5 correspond to the invention generators charge pump have a higher efficiency, so that also at low supply voltage of about 2.5 can be achieved In the output voltage of -20 C.

1. the one output (F), and the second output of which is connected to the output pin (A) circuit, and the output of the gate through which the first capacitor (b2) is connected to the first output clock signal, the second transistor (TL2), the first output of which is connected to the output gate of the first transistor (TX2), the second terminal of which is connected with the second output of the first transistor (TX2) and the output gate of which is connected to the first output of the first transistor (TX2), and with the second capacitor (CR), the first output of which is connected with the second output of the first transistor (TX2), and the second output of which is connected with the second output clock signal, and the transistors (TX2, TU2) are MOS transistors, made in the technique of triple pocket, wherein the first output of the third transistor (Tz2) is connected with the second output of the first transistor (TX2), the second terminal of the third transistor (Tz2) is connected with pocket/pockets (Kw) containing transistors (TX2, TU2, Tz2), and the output gate of the third transistor (Tz2) is connected to the first output of the first transistor (TX2).

2. The diagram on p. 1, characterized in that the first output of the fourth transistor (Tza2) is connected to the first output of the first transistor (TX2), the second terminal of the fourth transistor (Tza2) connected with the AC the n with the second output of the first transistor (TX2).

3. The diagram on p. 1, characterized in that the first output of the third capacitor (C3) is connected to the first output of the first transistor (TX2) and the second terminal of the third capacitor (C3) connected with pocket/pockets (Kw) containing transistors (TX2, TU2, Tz2).

4. Generator charge pump for generating a negative voltage, which is sequentially enabled, at least two circuit according to any one of paragraphs. 1-3, the input and the output of the first of these circuits is connected to the housing potential.

5. The method of operation of the generator charge pump under item 4, characterized in that the clock signals (F1, F2, or F3, F4) on the conclusions of the clock signals corresponding scheme is shifted by half of the duration of the period compared with a clock signal (F3, F4, or, respectively, F1, F2) in the previous diagram.

6. The method according to p. 5, characterized in that the duty cycle of at least a clock signal (F2, F4) conclusions on the second clock signal is greater than 0.5.

 

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